From mboxrd@z Thu Jan 1 00:00:00 1970 From: Albert ARIBAUD Date: Thu, 27 Oct 2011 22:05:38 +0200 Subject: [U-Boot] [PATCH 3/9] arm: Move CP15 init out of cpu_init_crit() In-Reply-To: References: <1318539963-3329-1-git-send-email-sjg@chromium.org> <1318539963-3329-4-git-send-email-sjg@chromium.org> <4EA1DD04.3010808@aribaud.net> <4EA1E797.1070600@aribaud.net> <4EA1F12A.5090108@aribaud.net> <4EA27738.4060102@aribaud.net> <4EA5C4C7.9060106@aribaud.net> <4EA5D6BE.8060206@aribaud.net> <4EA65A17.3000609@aribaud.net> Message-ID: <4EA9B992.909@aribaud.net> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Simon, Le 25/10/2011 23:16, Simon Glass a ?crit : >> But please think about what you actually want in start.S. Do you >> really want an #ifdef TEGRA2 with a check of a SOC register, followed >> by a branch around the cp15_init code? > > ^^^^ > This is the bit we need to sort out. Indeed, but I dont want a '#ifdef TEGRA2'. In the worst case I want a 'if (!core_is_avp())' by way of an identification register, and in the best case, I just want cp15 to be set unconditionally. >>>>> According to ARM, coprocessors 14 and 15 should always be supported from >>>>> ARMv6 up. Are you sure the AVP does not have it? If there is a Tegra >>>>> specification available, I'd like to have a look at it. >>>> >>>> Sorry I meant caches/MMU, etc. I should try doing the CP15 cache/MMU >>>> init on the AVP and see what happens. >>> >>> Please do check this. It may be that you can actually write to it from AVP >>> even though it has no or not all expected effect; and if that is confirmed, >>> then you don't have to separate the boot paths any more, >> >> Yes I'm tempted to go with this even if the ARM ARM is silent on the >> matter. I will try it out today. > > Silly me of course it doesn't work - since if the CP15 doesn't have > those features then you get undef instruction exception. Please see > ^^^ above! Are you stating a reasoning here or the results of an actual test? What causes an undefined instruction exception is the absence of a coprocessor to handle the instruction, not the presence of a coprocessor which incidentally cannot perform all of what"s being asked. > Regards, > Simon Amicalement, -- Albert.