From mboxrd@z Thu Jan 1 00:00:00 1970 From: Igor Grinberg Date: Mon, 31 Oct 2011 10:11:28 +0200 Subject: [U-Boot] [PATCH 3/4] EHCI: adjust for mx5 In-Reply-To: <1317253971-24558-4-git-send-email-fermata7@gmail.com> References: <1317253971-24558-1-git-send-email-fermata7@gmail.com> <1317253971-24558-4-git-send-email-fermata7@gmail.com> Message-ID: <4EAE5830.8050700@compulab.co.il> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Jana, On 09/29/11 02:52, Jana Rapava wrote: > Add macros and structures needed by Efika USB support code. > Move shared offset and bits definitions into common header file. > > Signed-off-by: Jana Rapava > Cc: Marek Vasut > Cc: Remy Bohmer > Cc: Stefano Babic > --- > drivers/usb/host/ehci-mxc.c | 31 +-------- > include/usb/ehci-fsl.h | 146 ++++++++++++++++++++++++++++++++++++++++++- > 2 files changed, 148 insertions(+), 29 deletions(-) > [...] > diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h > index 67600ed..727134f 100644 > --- a/include/usb/ehci-fsl.h > +++ b/include/usb/ehci-fsl.h [...] > @@ -169,6 +169,106 @@ > #define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR > #endif > > +#if defined(CONFIG_MX25) || defined(CONFIG_MX31) > +#define USBCTRL_OTGBASE_OFFSET 0x600 > +#endif > + > +#ifdef CONFIG_MX25 > +#define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6) > +#define MX25_USB_CTRL_HSTD_BIT (1<<5) > +#define MX25_USB_CTRL_USBTE_BIT (1<<4) > +#define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3) Why not align the above? Also, there should be spaces around the shift operators. > +#endif > + > +#ifdef CONFIG_MX31 > +#define MX31_H2_SIC_SHIFT 21 > +#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT) > +#define MX31_H2_PM_BIT (1 << 16) > +#define MX31_H2_DT_BIT (1 << 5) Alignment? > + > +#define MX31_H1_SIC_SHIFT 13 > +#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) > +#define MX31_H1_PM_BIT (1 << 8) > +#define MX31_H1_DT_BIT (1 << 4) ditto > +#endif > + > +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) > +/* offset for first USB CTRL register */ > +#define MX5_CTRL_REGS_OFFSET 0x800 > +#endif > + > +#if defined(CONFIG_MX51) || defined(CONFIG_MX31) > +/* USB_CTRL register bits of interest*/ > +#define MXC_OTG_SIC_SHIFT 29 > +#define MXC_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) > +#define MXC_OTG_WUE (1 << 27) > +#define MXC_OTG_PM (1 << 24) > +#endif > + > +#ifdef CONFIG_MX51 > +#define MX51_REGISTER_LAYOUT_LENGTH 0x200 > + > +/* Register offsets for MX51 */ > +#define MX51_OTG_ID 0x000 > +#define MX51_UH1_ID 0x200 > +#define MX51_UH2_ID 0x400 > + > +/* USB_CTRL register bits of interest*/ > +#define MX51_OTG_PM (1 << 24) > +#define MX51_H1_ULPI_IE (1 << 12) > +#define MX51_H1_WUE (1 << 11) > +#define MX51_H1_PM (1 << 8) > + > +/* PHY_CTRL_0 register bits of interest */ > +#define MX51_OTG_OVERCURD (1 << 8) > +#define MX51_EHCI_POWERPINSE (1 << 5) > + > +/* PHY_CTRL_1 register bits of interest */ > +#define MX51_SYSCLOCK_24_MHZ (1 << 0) > +#define MX51_SYSCLOCK_MASK (~(0xffffffff << 2)) This is something, I don't understand. Isn't it just 0x3? > + > +/* USB_CTRL_1 register bits of interest */ > +#define MX51_H1_EXTCLKE (1 << 25) > + > +/* USB Host 2 CTRL register bits of interest */ > +#define MX51_H2_ULPI_IE (1 << 8) > +#define MX51_H2_WUE (1 << 7) > +#define MX51_H2_PM (1 << 4) > + > +/* PORTSCx bits of interest */ > +#define MX51_ULPI_MODE_MASK (2 << 30) > +#define MX51_16BIT_UTMI (1 << 28) > + > +/* USBCMD bits of interest */ > +#define MX51_ITC_IMMEDIATE_MASK (0xff << 16) > +#endif > + > +/* > +* ULPI > +*/ Something went wrong with the comment formatting here... > +#define ULPI_ID_REGS_COUNT 4 > +#define ULPI_TEST_VALUE 0x55 > +#define ULPI_TIMEOUT 1000 /* some reasonable value */ > + > +/* ULPI viewport control bits */ > +#define ULPI_WU (1 << 31) > +#define ULPI_SS (1 << 27) > +#define ULPI_RWRUN (1 << 30) > +#define ULPI_RWCTRL (1 << 29) > + > +/* ULPI OTG Control bits of interest */ > +#define ULPI_OTG_EXT_VBUS_IND (1 << 7) > +#define ULPI_OTG_DM_PULLDOWN (1 << 2) > +#define ULPI_OTG_DP_PULLDOWN (1 << 1) > +#define ULPI_OTG_DRV_VBUS (1 << 5) > +#define ULPI_OTG_DRV_VBUS_EXT (1 << 6) > +#define ULPI_OTG_CHRG_VBUS (1 << 4) alignment > + > +/* ULPI Function Control bits of interest */ > +#define ULPI_FC_XCVR_SELECT (1 << 0) > +#define ULPI_FC_OPMODE_NORMAL (0 << 3) > +#define ULPI_FC_SUSPENDM_PWRED (1 << 6) ditto [...] > + > +struct mxc_ulpi_regs { > + u8 vendor_id_low; /* 0x00 - Vendor ID lower byte */ > + u8 vendor_id_high; /* 0x01 - Vendor ID upper byte */ > + u8 product_id_low; /* 0x02 - Product ID lower byte */ > + u8 product_id_high; /* 0x03 - Product ID higher byte */ > + /* Function Control; 0x04 - 0x06 Read, 0x04 Write */ > + u8 function_ctrl_write; > + u8 function_ctrl_set; /* 0x05 Set */ > + u8 function_ctrl_clear; /* 0x06 Clear */ > + /* Interface Control; 0x07 - 0x09 Read, 0x07 Write */ > + u8 iface_ctrl_write; > + u8 iface_ctrl_set; /* 0x08 Set */ > + u8 iface_ctrl_clear; /* 0x09 Clear */ > + /* OTG Control; 0x0A - 0x0C Read, 0x0A Write */ > + u8 otg_ctrl_write; > + u8 otg_ctrl_set; /* 0x0B Set */ > + u8 otg_ctrl_clear; /* 0x0C Clear */ > + /* USB Interrupt Enable Rising; 0x0D - 0x0F Read, 0x0D Write */ > + u8 usb_ie_rising_write; > + u8 usb_ie_rising_set; /* 0x0E Set */ > + u8 usb_ie_rising_clear; /* 0x0F Clear */ > + /* USB Interrupt Enable Falling; 0x10 - 0x12 Read, 0x10 Write */ > + u8 usb_ie_falling_write; > + u8 usb_ie_falling_set; /* 0x11 Set */ > + u8 usb_ie_falling_clear; /* 0x12 Clear */ > + u8 usb_int_status; /* 0x13 - USB Interrupt Status */ > + u8 usb_int_latch; /* 0x14 - USB Interrupt Latch */ > + u8 debug; /* 0x15 - Debug */ > + /* Scratch Register; 0x16 - 0x18 Read, 0x16 Write */ > + u8 scratch_write; > + u8 scratch_set; /* 0x17 Set */ > + u8 scratch_clear; /* 0x18 Clear*/ > +}; These are the generic ULPI specification registers and not mxc specific. I'd expect to have them in a more generic location. > + > #endif /* _EHCI_FSL_H */ -- Regards, Igor.