[U-Boot] [PATCH v5] MPC8360EMDS: 512MB DDR and 33.33MHz oscillator support

[U-Boot] [PATCH v5] MPC8360EMDS: 512MB DDR and 33.33MHz oscillator support

[Chang-Ming.Huang at freescale.com]

From: Jerry Huang <Chang-Ming.Huang@freescale.com>

The new MPC8360EMDS board changes the oscillator to 33.33MHz in order to
support QE 500MHZ and this new board supports 512MB DDR since 2008,
but the u-boot only supports 256MB DDR and 66.6MHz oscillator on top tree,

For 512MB DDR:
BAT0 is used for the first 256MB memory, BAT4 is used for the second
256MB memory and the address space of SDRAM follows the DDR, so if the size
of DDR is 256MB, the BAT4 will be used for SDRAM and if the size of DDR
is 512MB, the BAT4 will be used for the second 256MB memory and there is no BAT
for SDRAM.
Therefore, if the size of DDR is 512MB, this patch will use BAT6 for SDRAM
and BAT5 will be used for PCI MEM to replace the BAT6 after the codes relocates
to the DDR.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
---
cahnges for v2:
	- fix multiline comment wrong
changes for v3:
	- change the oscillator to 33330000, not 33300000
changes for v4:
	- add the mandatory history of changes
changes for v5:
	- move the code to platform file from lib/board.c
	- add 2011 copyright

 board/freescale/mpc8360emds/mpc8360emds.c |   36 ++++++++++++++++++++++++++++-
 include/configs/MPC8360EMDS.h             |   13 +++++-----
 2 files changed, 42 insertions(+), 7 deletions(-)

diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index 0babd26..7906f5e 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2006,2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006,2010-2011 Freescale Semiconductor, Inc.
  * Dave Liu <daveliu@freescale.com>
  *
  * See file CREDITS for list of people who contributed to this
@@ -23,6 +23,7 @@
 #include <asm/mmu.h>
 #include <asm/io.h>
 #include <asm/fsl_enet.h>
+#include <asm/mmu.h>
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
 #endif
@@ -138,9 +139,26 @@ int board_early_init_f(void)
 
 int board_early_init_r(void)
 {
+	gd_t *gd;
 #ifdef CONFIG_PQ_MDS_PIB
 	pib_init();
 #endif
+	/*
+	 * BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB
+	 * So re-setup PCI MEM space used BAT5 after relocated to DDR
+	 */
+	gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+	if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
+		/* Clear the BAT5 */
+		write_bat(DBAT5, 0, 0);
+		write_bat(IBAT5, 0, 0);
+		asm("sync");
+		/* Setup BAT5 for PCI MEM */
+		write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L);
+		write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L);
+		asm("sync");
+	}
+
 	return 0;
 }
 
@@ -290,6 +308,22 @@ static int sdram_init(unsigned int base)
 	if (rem)
 		base = base - rem + sdram_size;
 
+	/*
+	 * Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB
+	 * After relocated to DDR, re-setup PCI MEM space used BAT5
+	 */
+	if (base > CONFIG_MAX_MEM_MAPPED) {
+		unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE;
+		unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP;
+
+		write_bat(DBAT6, 0, 0);		/* Clear the BAT6 */
+		write_bat(IBAT6, 0, 0);
+		asm("sync");
+		write_bat(DBAT6, batu, batl);	/* Setup the BAT6 for SDRAM */
+		write_bat(IBAT6, batu, batl);
+		asm("sync");
+	}
+
 	sdram_addr = (uint *)base;
 	/*
 	 * Setup SDRAM Base and Option Registers
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index a959940..00ea85a 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006,2011 Freescale Semiconductor, Inc.
  *
  * Dave Liu <daveliu@freescale.com>
  *
@@ -40,13 +40,13 @@
  * System Clock Setup
  */
 #ifdef CONFIG_PCISLAVE
-#define CONFIG_83XX_PCICLK	66000000 /* in HZ */
+#define CONFIG_83XX_PCICLK	33330000 /* in HZ */
 #else
-#define CONFIG_83XX_CLKIN	66000000 /* in Hz */
+#define CONFIG_83XX_CLKIN	33330000 /* in Hz */
 #endif
 
 #ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ	66000000
+#define CONFIG_SYS_CLK_FREQ	33330000
 #endif
 
 /*
@@ -55,11 +55,11 @@
 #define CONFIG_SYS_HRCW_LOW (\
 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
-	HRCWL_CSB_TO_CLKIN_4X1 |\
+	HRCWL_CSB_TO_CLKIN_8X1 |\
 	HRCWL_VCO_1X2 |\
 	HRCWL_CE_PLL_VCO_DIV_4 |\
 	HRCWL_CE_PLL_DIV_1X1 |\
-	HRCWL_CE_TO_PLL_1X6 |\
+	HRCWL_CE_TO_PLL_1X15 |\
 	HRCWL_CORE_TO_CSB_2X1)
 
 #ifdef CONFIG_PCISLAVE
@@ -506,6 +506,7 @@
  */
 
 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
+#define CONFIG_BAT_RW
 
 /* DDR/LBC SDRAM: cacheable */
 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-- 
1.6.4

[U-Boot] [PATCH v5] MPC8360EMDS: 512MB DDR and 33.33MHz oscillator support

[Kim Phillips]

On Thu, 27 Oct 2011 13:47:48 +0800
<Chang-Ming.Huang@freescale.com> wrote:

> From: Jerry Huang <Chang-Ming.Huang@freescale.com>
> 
> The new MPC8360EMDS board changes the oscillator to 33.33MHz in order to
> support QE 500MHZ and this new board supports 512MB DDR since 2008,
> but the u-boot only supports 256MB DDR and 66.6MHz oscillator on top tree,
> 
> For 512MB DDR:
> BAT0 is used for the first 256MB memory, BAT4 is used for the second
> 256MB memory and the address space of SDRAM follows the DDR, so if the size
> of DDR is 256MB, the BAT4 will be used for SDRAM and if the size of DDR
> is 512MB, the BAT4 will be used for the second 256MB memory and there is no BAT
> for SDRAM.
> Therefore, if the size of DDR is 512MB, this patch will use BAT6 for SDRAM
> and BAT5 will be used for PCI MEM to replace the BAT6 after the codes relocates
> to the DDR.
> 
> Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
> ---
> cahnges for v2:
> 	- fix multiline comment wrong
> changes for v3:
> 	- change the oscillator to 33330000, not 33300000
> changes for v4:
> 	- add the mandatory history of changes
> changes for v5:
> 	- move the code to platform file from lib/board.c
> 	- add 2011 copyright

NAK - this patch bricks my (older) mpc8360emds board.

Kim

[U-Boot] [PATCH v5] MPC8360EMDS: 512MB DDR and 33.33MHz oscillator support

[Huang Changming-R66093]

Kim,
Since 2008, the boards shipped to customer are the new boards with 33.33MHz oscillator and 512MB DDR.
How can I deal with the new board and old board?

Thanks and Best Regards
Jerry Huang


> -----Original Message-----
> From: Phillips Kim-R1AAHA
> Sent: Wednesday, November 02, 2011 7:53 AM
> To: Huang Changming-R66093
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH v5] MPC8360EMDS: 512MB DDR and 33.33MHz
> oscillator support
> 
> On Thu, 27 Oct 2011 13:47:48 +0800
> <Chang-Ming.Huang@freescale.com> wrote:
> 
> > From: Jerry Huang <Chang-Ming.Huang@freescale.com>
> >
> > The new MPC8360EMDS board changes the oscillator to 33.33MHz in order
> > to support QE 500MHZ and this new board supports 512MB DDR since 2008,
> > but the u-boot only supports 256MB DDR and 66.6MHz oscillator on top
> > tree,
> >
> > For 512MB DDR:
> > BAT0 is used for the first 256MB memory, BAT4 is used for the second
> > 256MB memory and the address space of SDRAM follows the DDR, so if
> the
> > size of DDR is 256MB, the BAT4 will be used for SDRAM and if the size
> > of DDR is 512MB, the BAT4 will be used for the second 256MB memory
> and
> > there is no BAT for SDRAM.
> > Therefore, if the size of DDR is 512MB, this patch will use BAT6 for
> > SDRAM and BAT5 will be used for PCI MEM to replace the BAT6 after the
> > codes relocates to the DDR.
> >
> > Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
> > ---
> > cahnges for v2:
> > 	- fix multiline comment wrong
> > changes for v3:
> > 	- change the oscillator to 33330000, not 33300000 changes for v4:
> > 	- add the mandatory history of changes changes for v5:
> > 	- move the code to platform file from lib/board.c
> > 	- add 2011 copyright
> 
> NAK - this patch bricks my (older) mpc8360emds board.
> 
> Kim

[U-Boot] [PATCH v5] MPC8360EMDS: 512MB DDR and 33.33MHz oscillator support

[Tabi Timur-B04825]

On Tue, Nov 1, 2011 at 9:08 PM, Huang Changming-R66093
<r66093@freescale.com> wrote:
> Kim,
> Since 2008, the boards shipped to customer are the new boards with 33.33MHz oscillator and 512MB DDR.
> How can I deal with the new board and old board?

Check the board revision at runtime.

-- 
Timur Tabi
Linux kernel developer at Freescale

[U-Boot] [PATCH v5] MPC8360EMDS: 512MB DDR and 33.33MHz oscillator support

[Huang Changming-R66093]

Thanks and Best Regards
Jerry Huang


> -----Original Message-----
> From: Tabi Timur-B04825
> Sent: Wednesday, November 02, 2011 11:25 AM
> To: Huang Changming-R66093
> Cc: Phillips Kim-R1AAHA; u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH v5] MPC8360EMDS: 512MB DDR and 33.33MHz
> oscillator support
> 
> On Tue, Nov 1, 2011 at 9:08 PM, Huang Changming-R66093
> <r66093@freescale.com> wrote:
> > Kim,
> > Since 2008, the boards shipped to customer are the new boards with
> 33.33MHz oscillator and 512MB DDR.
> > How can I deal with the new board and old board?
> 
> Check the board revision at runtime.
> 
Board Specification says, there is one EEPROM to contain all board history, and I found it:
On I2C2 bus, there is one EEPROM BRD(0x50) from the schematics, but the content of this EEPROM is 0xff.
That's to say, we can't check the board information from this EEPROM.

[U-Boot] [PATCH v5] MPC8360EMDS: 512MB DDR and 33.33MHz oscillator support

[McClintock Matthew-B29882]

On Wed, Nov 2, 2011 at 2:34 AM, Huang Changming-R66093
<r66093@freescale.com> wrote:
>> > How can I deal with the new board and old board?
>>
>> Check the board revision at runtime.
>>
> Board Specification says, there is one EEPROM to contain all board history, and I found it:
> On I2C2 bus, there is one EEPROM BRD(0x50) from the schematics, but the content of this EEPROM is 0xff.
> That's to say, we can't check the board information from this EEPROM.
> From the code of mpc8360emds platform, there is not the interface to check the board information.
>
> So, there is no way to check the board revision at runtime.

Is your board special? Maybe the ones customers get go through the
proper process to have EEPROM updated? Otherwise, you will probably
need to create a new board type:

$ make mpc8360emds_newmodifier

-M

[U-Boot] [PATCH v5] MPC8360EMDS: 512MB DDR and 33.33MHz oscillator support

[Kim Phillips]

On Wed, 2 Nov 2011 09:52:17 -0500
McClintock Matthew-B29882 <B29882@freescale.com> wrote:

> On Wed, Nov 2, 2011 at 2:34 AM, Huang Changming-R66093
> <r66093@freescale.com> wrote:
> >> > How can I deal with the new board and old board?
> >>
> >> Check the board revision at runtime.
> >>
> > Board Specification says, there is one EEPROM to contain all board history, and I found it:
> > On I2C2 bus, there is one EEPROM BRD(0x50) from the schematics, but the content of this EEPROM is 0xff.
> > That's to say, we can't check the board information from this EEPROM.
> > From the code of mpc8360emds platform, there is not the interface to check the board information.
> >
> > So, there is no way to check the board revision at runtime.

Board revision information should be in BCSR12. I'm curious whether
yours contains a higher board revision level than mine:

=> md.b f8000000 e
f8000000: 04 04 00 c6 94 60 00 00 ac 2e 00 b8 10 3f    .....`.......?
                                      BCSR12->^^

because the sticker on the FPGA says "BCSR 2.1" vs. the "1.0"
encoding above.  Best case explanation would be the h/w encoding is
0-based and they don't bother to update the minor revision number...

> Is your board special? Maybe the ones customers get go through the
> proper process to have EEPROM updated? Otherwise, you will probably
> need to create a new board type:
> 
> $ make mpc8360emds_newmodifier

wrt setting CONFIG_83XX_CLKIN, it's a little harder to do at
runtime, so we should do as Matt says instead of checking the board
revision at runtime - see e.g., the MPC8313ERDB_33 vs.
MPC8313ERDB_66 targets.  The HRCW_LOW change should also be
#ifdeffed.

Some other comments on this patch, now that I've taken a closer look:

1. it should be two patches - one for the CLKIN change, the other
for the dynamic remapping change.

2. update doc/README.mpc8360emds for 33 vs. 66 a la
doc/README.mpc8313erdb, and also for the remapping change, each
update in its corresponding patch.  Might want to mention any dip
switch setting changes and the physical location of the oscillator
so the user is sure which one to use - CLKIN is the one closest to
the JTAG connector, right?

3. no need to sync after write_bat(); write_bat() does this already.

4. no need to clear BATs before writing them either.

5. I can't comprehend the comment "re-setup PCI MEM space used BAT5
after relocated to DDR" - do you mean something like "reuse BAT5 for
PCI MEM space after relocation to RAM"?

6. re-post patches to this thread - see the 3rd bullet in:

http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions

Thanks,

Kim

[U-Boot] [PATCH v5] MPC8360EMDS: 512MB DDR and 33.33MHz oscillator support

[Timur Tabi]

Kim Phillips wrote:
> 4. no need to clear BATs before writing them either.

FYI, take a look at Becky's BAT patch from a month ago:

	http://patchwork.ozlabs.org/patch/117523/

The patch is for 86xx, so I have no idea if it's relevant to this discussion.

-- 
Timur Tabi
Linux kernel developer at Freescale

[U-Boot] [PATCH v5] MPC8360EMDS: 512MB DDR and 33.33MHz oscillator support

[Huang Changming-R66093]

Thanks and Best Regards
Jerry Huang


> -----Original Message-----
> From: McClintock Matthew-B29882
> Sent: Wednesday, November 02, 2011 10:52 PM
> To: Huang Changming-R66093
> Cc: Tabi Timur-B04825; u-boot at lists.denx.de; Phillips Kim-R1AAHA
> Subject: Re: [U-Boot] [PATCH v5] MPC8360EMDS: 512MB DDR and 33.33MHz
> oscillator support
> 
> On Wed, Nov 2, 2011 at 2:34 AM, Huang Changming-R66093
> <r66093@freescale.com> wrote:
> >> > How can I deal with the new board and old board?
> >>
> >> Check the board revision at runtime.
> >>
> > Board Specification says, there is one EEPROM to contain all board
> history, and I found it:
> > On I2C2 bus, there is one EEPROM BRD(0x50) from the schematics, but
> the content of this EEPROM is 0xff.
> > That's to say, we can't check the board information from this EEPROM.
> > From the code of mpc8360emds platform, there is not the interface to
> check the board information.
> >
> > So, there is no way to check the board revision at runtime.
> 
> Is your board special? Maybe the ones customers get go through the
> proper process to have EEPROM updated? Otherwise, you will probably
> need to create a new board type:


No, I have two boards, one was used for BSP development, and the other was ordered in Aug.

> $ make mpc8360emds_newmodifier
> 
It make sense.

[U-Boot] [PATCH v5] MPC8360EMDS: 512MB DDR and 33.33MHz oscillator support

[McClintock Matthew-B29882]

On Wed, Nov 2, 2011 at 9:16 PM, Huang Changming-R66093
<r66093@freescale.com> wrote:
> No, I have two boards, one was used for BSP development, and the other was ordered in Aug.
>
>> $ make mpc8360emds_newmodifier
>>
> It make sense.

Kim's way makes more sense if those values are different though.

-M

[U-Boot] [PATCH v5] MPC8360EMDS: 512MB DDR and 33.33MHz oscillator support

[Huang Changming-R66093]

Thanks and Best Regards
Jerry Huang


> -----Original Message-----
> From: Phillips Kim-R1AAHA
> Sent: Thursday, November 03, 2011 4:37 AM
> To: McClintock Matthew-B29882
> Cc: Huang Changming-R66093; Tabi Timur-B04825; u-boot at lists.denx.de;
> Phillips Kim-R1AAHA
> Subject: Re: [U-Boot] [PATCH v5] MPC8360EMDS: 512MB DDR and 33.33MHz
> oscillator support
> 
> On Wed, 2 Nov 2011 09:52:17 -0500
> McClintock Matthew-B29882 <B29882@freescale.com> wrote:
> 
> > On Wed, Nov 2, 2011 at 2:34 AM, Huang Changming-R66093
> > <r66093@freescale.com> wrote:
> > >> > How can I deal with the new board and old board?
> > >>
> > >> Check the board revision at runtime.
> > >>
> > > Board Specification says, there is one EEPROM to contain all board
> history, and I found it:
> > > On I2C2 bus, there is one EEPROM BRD(0x50) from the schematics, but
> the content of this EEPROM is 0xff.
> > > That's to say, we can't check the board information from this
> EEPROM.
> > > From the code of mpc8360emds platform, there is not the interface
> to check the board information.
> > >
> > > So, there is no way to check the board revision at runtime.
> 
> Board revision information should be in BCSR12. I'm curious whether
> yours contains a higher board revision level than mine:
> 
> => md.b f8000000 e
> f8000000: 04 04 00 c6 94 60 00 00 ac 2e 00 b8 10 3f    .....`.......?
>                                       BCSR12->^^
My board BCSR info:
=> md.b f8000000 e
f8000000: 0a 04 00 8f 94 60 00 00 ac 2e 00 b8 22 3f    .....`......"?

> because the sticker on the FPGA says "BCSR 2.1" vs. the "1.0"
> encoding above.  Best case explanation would be the h/w encoding is 0-
> based and they don't bother to update the minor revision number...
> 
> > Is your board special? Maybe the ones customers get go through the
> > proper process to have EEPROM updated? Otherwise, you will probably
> > need to create a new board type:
> >
> > $ make mpc8360emds_newmodifier
> 
> wrt setting CONFIG_83XX_CLKIN, it's a little harder to do at runtime,
> so we should do as Matt says instead of checking the board revision at
> runtime - see e.g., the MPC8313ERDB_33 vs.
> MPC8313ERDB_66 targets.  The HRCW_LOW change should also be #ifdeffed.
> 
> Some other comments on this patch, now that I've taken a closer look:
> 
> 1. it should be two patches - one for the CLKIN change, the other for
> the dynamic remapping change.
> 
> 2. update doc/README.mpc8360emds for 33 vs. 66 a la
> doc/README.mpc8313erdb, and also for the remapping change, each update
> in its corresponding patch.  Might want to mention any dip switch
> setting changes and the physical location of the oscillator so the user
> is sure which one to use - CLKIN is the one closest to the JTAG
> connector, right?
Yes, it is U41.

> 3. no need to sync after write_bat(); write_bat() does this already.
> 
> 4. no need to clear BATs before writing them either.
> 
> 5. I can't comprehend the comment "re-setup PCI MEM space used BAT5
> after relocated to DDR" - do you mean something like "reuse BAT5 for
> PCI MEM space after relocation to RAM"?
Yes,  I will change the comment.

> 6. re-post patches to this thread - see the 3rd bullet in:
> 
> http://www.denx.de/wiki/view/U-
> Boot/Patches#Sending_updated_patch_versions
> 
> Thanks,
> 
> Kim