From mboxrd@z Thu Jan 1 00:00:00 1970 From: Albert ARIBAUD Date: Mon, 07 Nov 2011 13:21:43 +0100 Subject: [U-Boot] [PATCH] ARM: Generic cache ops skeleton In-Reply-To: <1320542183-20309-1-git-send-email-marek.vasut@gmail.com> References: <1320542183-20309-1-git-send-email-marek.vasut@gmail.com> Message-ID: <4EB7CD57.3050207@aribaud.net> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Le 06/11/2011 02:16, Marek Vasut a ?crit : > This patch should allow a CPU to register it's own cache ops. This shall allow > multiple CPUs with different cache handlings to be supported. I don't really like the idea of a system of dynamic cache ops right now, because as discussed by Mike, we're far from a one-size-fits-all multiple-SoC binary, and in the current context of a single-SoC binary, this patch is overkill for cache management IMO. OTOH, I am not against rationalizing the cache code, along the lines already discussed, i.e. factorizing cache code as much as possible (just as we should factorize start.S code for instance). Amicalement, -- Albert.