From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Tue, 8 Nov 2011 08:28:34 -0700 Subject: [U-Boot] [PATCH 09/12] OMAP3: Add SPL support to Beagleboard In-Reply-To: <4EB8E100.6030308@compulab.co.il> References: <1320696348-11664-1-git-send-email-trini@ti.com> <1320696348-11664-10-git-send-email-trini@ti.com> <4EB8E100.6030308@compulab.co.il> Message-ID: <4EB94AA2.8000608@ti.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 11/08/2011 12:57 AM, Igor Grinberg wrote: > On 11/07/11 22:05, Tom Rini wrote: >> This introduces 200MHz Micron parts timing information based on x-loader >> to . The memory init logic is also based on what >> x-loader does in these cases. Note that while previously u-boot would >> be flashed in with SW ECC in this case it now must be flashed with HW >> ECC. [snip] >> +#ifdef CONFIG_SPL_BUILD >> +/* >> + * Routine: board_early_sdrc_init > > s/board_early_sdrc_init/get_board_mem_timings/ > >> + * Description: If we use SPL then there is no x-loader nor config header >> + * so we have to setup the DDR timings outself on both banks. > > s/outself/ourself/ Thanks. [snip] >> + case REVISION_C4: >> + if ((pop_mfr == NAND_MFR_STMICRO) && (pop_id == 0xba)) { > > No need for extra parenthesis. I'll double check all these cases, thanks. >> + *mcfg = 0x04590099; >> + *ctrla = NUMONYX_V_ACTIMA_165; >> + *ctrlb = NUMONYX_V_ACTIMB_165; >> + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; > > This will look much better if it will be aligned. It's not in CodingStyle tho ;) [snip] >> -# For use with external or internal boots. >> -CONFIG_SYS_TEXT_BASE = 0x80008000 > > Removing needless crap is a very good thing, but does not > belong to this patch, is it? I thought I said in this commit message, but I know I did for am3517 evm/crane, we change CONFIG_SYS_TEXT_BASE which is why we remove this file here. It could be done as a two-step if it's a hard objection tho. -- Tom