From mboxrd@z Thu Jan 1 00:00:00 1970 From: Albert ARIBAUD Date: Tue, 08 Nov 2011 21:57:38 +0100 Subject: [U-Boot] [PATCH] ARM: FIX for dcache_disable() for ARM926ej-s In-Reply-To: <20111104094048.GA13470@altenpts-laptop> References: <20111104094048.GA13470@altenpts-laptop> Message-ID: <4EB997C2.2080809@aribaud.net> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Bas, Le 04/11/2011 10:40, Bas van den Berg a ?crit : > the cache also needs to be invalidated, not just flushed, Since re-enabling it, > can cause inconsistent data without invalidation. > > Signed-off-by: Bas van den Berg > --- > arch/arm/lib/cache.c | 2 ++ > 1 files changed, 2 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c > index b545fb7..10eb8c9 100644 > --- a/arch/arm/lib/cache.c > +++ b/arch/arm/lib/cache.c > @@ -37,6 +37,8 @@ void __flush_cache(unsigned long start, unsigned long size) > asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); > /* disable write buffer as well (page 2-22) */ > asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); > + /* Invalidate dcache as well */ > + asm("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); > #endif > return; > } Come to think of it... NAK, sorry. Flushing should do what it says on the tin, and invalidating is not what it says -- especially considering your intent is not about flushing but about disabling ('re-enabling...') If you need the cache to be flushed then invalidated then disabled, then call all three functions where you need that, i.e. find the place where there is only a call to __flush_cache() and append a call to __invalidate_cache(), and if that happens a lot, then feel free to provide a new function that will sequence flush and invalidate. Amicalement, -- Albert.