From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ilya Yanok Date: Sat, 12 Nov 2011 02:26:23 +0400 Subject: [U-Boot] [PATCH 05/13] davinci_emac: fix for running with dcache enabled In-Reply-To: References: <1320971988-23525-1-git-send-email-yanok@emcraft.com> <1320971988-23525-6-git-send-email-yanok@emcraft.com> Message-ID: <4EBDA10F.60306@emcraft.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Andy, On 12.11.2011 02:11, Andy Fleming wrote: >> DaVinci EMAC is present on TI AM35xx SoCs (ARMv7) which run with D-Cache >> enabled by default. So we have to take care and flush/invalidate the >> cache before/after the DMA operations. >> >> Please note that the receive buffer alignment to 32 byte boundary comes >> from the old driver version I don't know if it is really needed or >> alignment to cache line size is enough. >> >> Signed-off-by: Ilya Yanok > > I don't understand. Didn't you just submit a patch to disable dcache > on all boards with EMAC? Yes, on all arm926ejs boards. Look, arm926ejs has no implementation for {flush,invalidate}_dcache_range and I really have no time now to implement them. So I've just added no-op cache operations for CONFIG_SYS_DCACHE_OFF case to fix the compilation of DaVinci board. But it turned out that the builds are still broken because some DaVinci boards using EMAC do not disable D-Cache. Regards, Ilya.