From mboxrd@z Thu Jan 1 00:00:00 1970 From: Igor Grinberg Date: Mon, 14 Nov 2011 13:00:50 +0200 Subject: [U-Boot] [PATCH] Improve Power Management in SMC911X driver. In-Reply-To: <1321259903-15001-2-git-send-email-bertrand.cachet@heig-vd.ch> References: <1321259903-15001-1-git-send-email-bertrand.cachet@heig-vd.ch> <1321259903-15001-2-git-send-email-bertrand.cachet@heig-vd.ch> Message-ID: <4EC0F4E2.3040800@compulab.co.il> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Bertrand, On 11/14/11 10:38, bertrand.cachet at heig-vd.ch wrote: > From: Bertrand Cachet > >>>From datasheet, when READY bit is set inside PM_CTRL register, it means that > device is already in *normal* (D0) mode => it doesn't need to be wake-up. > > With this patch, we only wake-up (writing on TEST_BYTE register) if PM_MODE > bits of PM_CTRL register is in D1/D2 mode. > > Signed-off-by: Bertrand Cachet > --- > drivers/net/smc911x.h | 6 ++++-- > 1 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h > index 8ce08a9..258b9b6 100644 > --- a/drivers/net/smc911x.h > +++ b/drivers/net/smc911x.h > @@ -471,8 +471,10 @@ static void smc911x_reset(struct eth_device *dev) > { > int timeout; > > - /* Take out of PM setting first */ > - if (smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) { > + /* Take out of PM setting first */ > + /* If PMT_CTRL_READY bit is set to 1b => power management is > + already ready */ The multi-line comments should look like this: /* * blablabla */ > + if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0) { > /* Write to the bytetest will take out of powerdown */ > smc911x_reg_write(dev, BYTE_TEST, 0x0); > -- Regards, Igor.