* [U-Boot] [PATCH v4 1/5] x86: Add a target for running as a coreboot payload
2011-11-17 0:27 [U-Boot] [PATCH v4 0/5] Add a coreboot board, CPU, and configuration, and target Gabe Black
@ 2011-11-17 0:27 ` Gabe Black
2011-11-17 9:43 ` Graeme Russ
2011-11-17 0:27 ` [U-Boot] [PATCH v4 2/5] x86: Add a basic implementation for a coreboot board Gabe Black
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Gabe Black @ 2011-11-17 0:27 UTC (permalink / raw)
To: u-boot
Add a target for running u-boot as a coreboot payload in boards.cfg.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
---
Changes in v2:
Change capitalization of the x86 tag.
Changes in v3:
Move the Signed-off-by line up.
Changes in v4:
Change the summary tag style.
boards.cfg | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/boards.cfg b/boards.cfg
index 8b7a03b..4b2a1a7 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -272,6 +272,7 @@ tcm-bf518 blackfin blackfin
tcm-bf537 blackfin blackfin
eNET x86 x86 eNET - sc520 eNET:SYS_TEXT_BASE=0x38040000
eNET_SRAM x86 x86 eNET - sc520 eNET:SYS_TEXT_BASE=0x19000000
+coreboot-x86 x86 x86 coreboot chromebook-x86 coreboot coreboot:SYS_TEXT_BASE=0xFC0000
sandbox sandbox sandbox sandbox sandbox -
cobra5272 m68k mcf52x2 cobra5272 -
idmr m68k mcf52x2
--
1.7.3.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [U-Boot] [PATCH v4 1/5] x86: Add a target for running as a coreboot payload
2011-11-17 0:27 ` [U-Boot] [PATCH v4 1/5] x86: Add a target for running as a coreboot payload Gabe Black
@ 2011-11-17 9:43 ` Graeme Russ
2011-11-17 10:11 ` Gabe Black
0 siblings, 1 reply; 11+ messages in thread
From: Graeme Russ @ 2011-11-17 9:43 UTC (permalink / raw)
To: u-boot
Hi Gabe,
On 17/11/11 11:27, Gabe Black wrote:
> Add a target for running u-boot as a coreboot payload in boards.cfg.
>
> Signed-off-by: Gabe Black <gabeblack@chromium.org>
> ---
> Changes in v2:
> Change capitalization of the x86 tag.
>
> Changes in v3:
> Move the Signed-off-by line up.
>
> Changes in v4:
> Change the summary tag style.
>
> boards.cfg | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/boards.cfg b/boards.cfg
> index 8b7a03b..4b2a1a7 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -272,6 +272,7 @@ tcm-bf518 blackfin blackfin
> tcm-bf537 blackfin blackfin
> eNET x86 x86 eNET - sc520 eNET:SYS_TEXT_BASE=0x38040000
> eNET_SRAM x86 x86 eNET - sc520 eNET:SYS_TEXT_BASE=0x19000000
> +coreboot-x86 x86 x86 coreboot chromebook-x86 coreboot coreboot:SYS_TEXT_BASE=0xFC0000
> sandbox sandbox sandbox sandbox sandbox -
> cobra5272 m68k mcf52x2 cobra5272 -
> idmr m68k mcf52x2
As mentioned by others before, there is no reason to have these as discrete
patches - Please merge into a single 'Add coreboot payload'
Is there any real reason to reference 'chromebook-x86'?
And finally, what is the plan for motherboard specific coreboot variants?
Regards,
Graeme
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH v4 1/5] x86: Add a target for running as a coreboot payload
2011-11-17 9:43 ` Graeme Russ
@ 2011-11-17 10:11 ` Gabe Black
2011-11-17 10:26 ` Graeme Russ
0 siblings, 1 reply; 11+ messages in thread
From: Gabe Black @ 2011-11-17 10:11 UTC (permalink / raw)
To: u-boot
On Thu, Nov 17, 2011 at 1:43 AM, Graeme Russ <graeme.russ@gmail.com> wrote:
> Hi Gabe,
>
> On 17/11/11 11:27, Gabe Black wrote:
> > Add a target for running u-boot as a coreboot payload in boards.cfg.
> >
> > Signed-off-by: Gabe Black <gabeblack@chromium.org>
> > ---
> > Changes in v2:
> > Change capitalization of the x86 tag.
> >
> > Changes in v3:
> > Move the Signed-off-by line up.
> >
> > Changes in v4:
> > Change the summary tag style.
> >
> > boards.cfg | 1 +
> > 1 files changed, 1 insertions(+), 0 deletions(-)
> >
> > diff --git a/boards.cfg b/boards.cfg
> > index 8b7a03b..4b2a1a7 100644
> > --- a/boards.cfg
> > +++ b/boards.cfg
> > @@ -272,6 +272,7 @@ tcm-bf518 blackfin blackfin
> > tcm-bf537 blackfin blackfin
> > eNET x86 x86 eNET
> - sc520 eNET:SYS_TEXT_BASE=0x38040000
> > eNET_SRAM x86 x86 eNET
> - sc520 eNET:SYS_TEXT_BASE=0x19000000
> > +coreboot-x86 x86 x86 coreboot
> chromebook-x86 coreboot coreboot:SYS_TEXT_BASE=0xFC0000
> > sandbox sandbox sandbox sandbox
> sandbox -
> > cobra5272 m68k mcf52x2 cobra5272
> -
> > idmr m68k mcf52x2
>
> As mentioned by others before, there is no reason to have these as discrete
> patches - Please merge into a single 'Add coreboot payload'
>
Ok. Since there are more patches here than I sent out previously and one
big patch seemed like it was more than "exactly one complete logical
change" I wanted to find out how these should be merged. If they should all
be merged, then that answers the question.
>
> Is there any real reason to reference 'chromebook-x86'?
>
I don't follow. I'm not referencing it, that's what we're calling our board
since it's an x86 chromebook.
>
> And finally, what is the plan for motherboard specific coreboot variants?
>
We haven't worked out all the details, but our current working plan is that
coreboot itself will be specialized per board and that U-Boot will stay
fairly generic and be specialized as needed using the device tree. We may
find that a single version of U-Boot with a superset of drivers is too big
and we need to have different configs for each variant.
Gabe
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH v4 1/5] x86: Add a target for running as a coreboot payload
2011-11-17 10:11 ` Gabe Black
@ 2011-11-17 10:26 ` Graeme Russ
2011-11-17 12:33 ` Alan Carvalho de Assis
2011-11-17 21:31 ` Gabe Black
0 siblings, 2 replies; 11+ messages in thread
From: Graeme Russ @ 2011-11-17 10:26 UTC (permalink / raw)
To: u-boot
Hi Gabe,
On 17/11/11 21:11, Gabe Black wrote:
>
>
> On Thu, Nov 17, 2011 at 1:43 AM, Graeme Russ <graeme.russ@gmail.com
> <mailto:graeme.russ@gmail.com>> wrote:
>
> Hi Gabe,
>
> On 17/11/11 11:27, Gabe Black wrote:
> > Add a target for running u-boot as a coreboot payload in boards.cfg.
> >
> > Signed-off-by: Gabe Black <gabeblack@chromium.org
[snip]
>
> As mentioned by others before, there is no reason to have these as discrete
> patches - Please merge into a single 'Add coreboot payload'
>
>
>
> Ok. Since there are more patches here than I sent out previously and one
> big patch seemed like it was more than "exactly one complete logical
> change" I wanted to find out how these should be merged. If they should all
> be merged, then that answers the question.
Well, if a given patch is meaningless without another, they really should
be combined. Of course there are exceptions, like adding a new driver - The
code for it gets added in one patch, and the usage in a board in another
> Is there any real reason to reference 'chromebook-x86'?
>
> I don't follow. I'm not referencing it, that's what we're calling our board
> since it's an x86 chromebook.
I mean, if this is 'generic', why is there a reference to the chromebook?
> And finally, what is the plan for motherboard specific coreboot variants?
>
>
>
> We haven't worked out all the details, but our current working plan is that
> coreboot itself will be specialized per board and that U-Boot will stay
> fairly generic and be specialized as needed using the device tree. We may
> find that a single version of U-Boot with a superset of drivers is too big
> and we need to have different configs for each variant.
This probably won't work in and of itself without a major overhaul of the
U-Boot driver architecture :)
Boards will need their own config for Ethernet drivers for example
Regards,
Graeme
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH v4 1/5] x86: Add a target for running as a coreboot payload
2011-11-17 10:26 ` Graeme Russ
@ 2011-11-17 12:33 ` Alan Carvalho de Assis
2011-11-17 21:31 ` Gabe Black
1 sibling, 0 replies; 11+ messages in thread
From: Alan Carvalho de Assis @ 2011-11-17 12:33 UTC (permalink / raw)
To: u-boot
On 11/17/11, Graeme Russ <graeme.russ@gmail.com> wrote:
> Hi Gabe,
>
[snip]
>> I don't follow. I'm not referencing it, that's what we're calling our
>> board
>> since it's an x86 chromebook.
>
> I mean, if this is 'generic', why is there a reference to the chromebook?
>
I think a name like coreboot-x86 could make sense here, but it
shouldn't have dependence on drivers specific for chromebook hardware.
Only 'generic' drivers as vesa video and keyboard input needs to be
referenced on it. Then others developers could extend it to their
specific hardware, adding items like ethernet, mmc/sd driver, etc
Best Regards,
Alan
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH v4 1/5] x86: Add a target for running as a coreboot payload
2011-11-17 10:26 ` Graeme Russ
2011-11-17 12:33 ` Alan Carvalho de Assis
@ 2011-11-17 21:31 ` Gabe Black
1 sibling, 0 replies; 11+ messages in thread
From: Gabe Black @ 2011-11-17 21:31 UTC (permalink / raw)
To: u-boot
On Thu, Nov 17, 2011 at 2:26 AM, Graeme Russ <graeme.russ@gmail.com> wrote:
> Hi Gabe,
>
> On 17/11/11 21:11, Gabe Black wrote:
> >
> >
> > On Thu, Nov 17, 2011 at 1:43 AM, Graeme Russ <graeme.russ@gmail.com
> > <mailto:graeme.russ@gmail.com>> wrote:
> >
> > Hi Gabe,
> >
> > On 17/11/11 11:27, Gabe Black wrote:
> > > Add a target for running u-boot as a coreboot payload in
> boards.cfg.
> > >
> > > Signed-off-by: Gabe Black <gabeblack@chromium.org
>
> [snip]
>
> >
> > As mentioned by others before, there is no reason to have these as
> discrete
> > patches - Please merge into a single 'Add coreboot payload'
> >
> >
> >
> > Ok. Since there are more patches here than I sent out previously and one
> > big patch seemed like it was more than "exactly one complete logical
> > change" I wanted to find out how these should be merged. If they should
> all
> > be merged, then that answers the question.
>
> Well, if a given patch is meaningless without another, they really should
> be combined. Of course there are exceptions, like adding a new driver - The
> code for it gets added in one patch, and the usage in a board in another
>
> > Is there any real reason to reference 'chromebook-x86'?
> >
> > I don't follow. I'm not referencing it, that's what we're calling our
> board
> > since it's an x86 chromebook.
>
> I mean, if this is 'generic', why is there a reference to the chromebook?
>
The way it's ended up, the coreboot "CPU" is generic to coreboot, the
"board" is generic to chromebooks, and the config is either generic to
chromebooks or, if we decide we need it to be, specialized per specific
chromebook.
>
> > And finally, what is the plan for motherboard specific coreboot
> variants?
> >
> >
> >
> > We haven't worked out all the details, but our current working plan is
> that
> > coreboot itself will be specialized per board and that U-Boot will stay
> > fairly generic and be specialized as needed using the device tree. We may
> > find that a single version of U-Boot with a superset of drivers is too
> big
> > and we need to have different configs for each variant.
>
> This probably won't work in and of itself without a major overhaul of the
> U-Boot driver architecture :)
>
> Boards will need their own config for Ethernet drivers for example
>
This is working just fine so far, actually. It may not scale and we won't
be able to have more than one kind of certain things, but in the mean time
it's working for us. We are aware of these potential/eventual problems
though.
Gabe
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH v4 2/5] x86: Add a basic implementation for a coreboot board
2011-11-17 0:27 [U-Boot] [PATCH v4 0/5] Add a coreboot board, CPU, and configuration, and target Gabe Black
2011-11-17 0:27 ` [U-Boot] [PATCH v4 1/5] x86: Add a target for running as a coreboot payload Gabe Black
@ 2011-11-17 0:27 ` Gabe Black
2011-11-17 0:27 ` [U-Boot] [PATCH v4 3/5] x86: Add a preliminary coreboot configuration header Gabe Black
` (2 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Gabe Black @ 2011-11-17 0:27 UTC (permalink / raw)
To: u-boot
Signed-off-by: Gabe Black <gabeblack@chromium.org>
---
Changes in v2:
Get rid of some dead/unnecessary code in the Makefile and coreboot.c.
Changes in v3:
Change the summary line tag style.
board/chromebook-x86/coreboot/Makefile | 53 +++++++++++++++
board/chromebook-x86/coreboot/coreboot.c | 77 ++++++++++++++++++++++
board/chromebook-x86/coreboot/coreboot_pci.c | 30 +++++++++
board/chromebook-x86/coreboot/coreboot_start.S | 29 ++++++++
board/chromebook-x86/coreboot/coreboot_start16.S | 46 +++++++++++++
5 files changed, 235 insertions(+), 0 deletions(-)
create mode 100644 board/chromebook-x86/coreboot/Makefile
create mode 100644 board/chromebook-x86/coreboot/coreboot.c
create mode 100644 board/chromebook-x86/coreboot/coreboot_pci.c
create mode 100644 board/chromebook-x86/coreboot/coreboot_start.S
create mode 100644 board/chromebook-x86/coreboot/coreboot_start16.S
diff --git a/board/chromebook-x86/coreboot/Makefile b/board/chromebook-x86/coreboot/Makefile
new file mode 100644
index 0000000..cfcc0df
--- /dev/null
+++ b/board/chromebook-x86/coreboot/Makefile
@@ -0,0 +1,53 @@
+#
+# Copyright (c) 2011 The Chromium OS Authors.
+# (C) Copyright 2008
+# Graeme Russ, graeme.russ at gmail.com.
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2002
+# Daniel Engstr?m, Omicron Ceti AB, daniel at omicron.se.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += coreboot.o
+COBJS-$(CONFIG_PCI) += coreboot_pci.o
+SOBJS-y += coreboot_start16.o
+SOBJS-y += coreboot_start.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/chromebook-x86/coreboot/coreboot.c b/board/chromebook-x86/coreboot/coreboot.c
new file mode 100644
index 0000000..44c6f15
--- /dev/null
+++ b/board/chromebook-x86/coreboot/coreboot.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ at gmail.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/u-boot-x86.h>
+#include <flash.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+int board_early_init_f(void)
+{
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ /* CPU Speed to 100MHz */
+ gd->cpu_clk = 100000000;
+
+ /* Crystal is 33.000MHz */
+ gd->bus_clk = 33000000;
+
+ return 0;
+}
+
+void show_boot_progress(int val)
+{
+}
+
+
+int last_stage_init(void)
+{
+ return 0;
+}
+
+#ifndef CONFIG_SYS_NO_FLASH
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ return 0;
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+void setup_pcat_compatibility()
+{
+}
diff --git a/board/chromebook-x86/coreboot/coreboot_pci.c b/board/chromebook-x86/coreboot/coreboot_pci.c
new file mode 100644
index 0000000..732ca3c
--- /dev/null
+++ b/board/chromebook-x86/coreboot/coreboot_pci.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008,2009
+ * Graeme Russ, <graeme.russ@gmail.com>
+ *
+ * (C) Copyright 2002
+ * Daniel Engstr?m, Omicron Ceti AB, <daniel@omicron.se>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+void pci_init_board(void)
+{
+}
diff --git a/board/chromebook-x86/coreboot/coreboot_start.S b/board/chromebook-x86/coreboot/coreboot_start.S
new file mode 100644
index 0000000..8667d17
--- /dev/null
+++ b/board/chromebook-x86/coreboot/coreboot_start.S
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ at gmail.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* board early intialization */
+.globl early_board_init
+early_board_init:
+ /* No 32-bit board specific initialisation */
+ jmp early_board_init_ret
diff --git a/board/chromebook-x86/coreboot/coreboot_start16.S b/board/chromebook-x86/coreboot/coreboot_start16.S
new file mode 100644
index 0000000..9ad06df
--- /dev/null
+++ b/board/chromebook-x86/coreboot/coreboot_start16.S
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ at gmail.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * 16bit initialization code.
+ * This code have to map the area of the boot flash
+ * that is used by U-boot to its final destination.
+ */
+
+.text
+.section .start16, "ax"
+.code16
+.globl board_init16
+board_init16:
+ jmp board_init16_ret
+
+.section .bios, "ax"
+.code16
+.globl realmode_reset
+.hidden realmode_reset
+.type realmode_reset, @function
+realmode_reset:
+
+1: hlt
+ jmp 1
--
1.7.3.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [U-Boot] [PATCH v4 3/5] x86: Add a preliminary coreboot configuration header
2011-11-17 0:27 [U-Boot] [PATCH v4 0/5] Add a coreboot board, CPU, and configuration, and target Gabe Black
2011-11-17 0:27 ` [U-Boot] [PATCH v4 1/5] x86: Add a target for running as a coreboot payload Gabe Black
2011-11-17 0:27 ` [U-Boot] [PATCH v4 2/5] x86: Add a basic implementation for a coreboot board Gabe Black
@ 2011-11-17 0:27 ` Gabe Black
2011-11-17 0:27 ` [U-Boot] [PATCH v4 4/5] x86: Add an implementation for a coreboot CPU Gabe Black
2011-11-17 0:27 ` [U-Boot] [PATCH v4 5/5] x86: Make the serial port work for the coreboot board Gabe Black
4 siblings, 0 replies; 11+ messages in thread
From: Gabe Black @ 2011-11-17 0:27 UTC (permalink / raw)
To: u-boot
Signed-off-by: Gabe Black <gabeblack@chromium.org>
---
include/configs/coreboot.h | 225 ++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 225 insertions(+), 0 deletions(-)
create mode 100644 include/configs/coreboot.h
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
new file mode 100644
index 0000000..c658436
--- /dev/null
+++ b/include/configs/coreboot.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ at gmail.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/ibmpc.h>
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SYS_COREBOOT
+#undef CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_LAST_STAGE_INIT
+
+
+/*-----------------------------------------------------------------------
+ * Watchdog Configuration
+ */
+#undef CONFIG_WATCHDOG
+#undef CONFIG_HW_WATCHDOG
+
+/*-----------------------------------------------------------------------
+ * Real Time Clock Configuration
+ */
+#define CONFIG_RTC_MC146818
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
+
+/*-----------------------------------------------------------------------
+ * Serial Configuration
+ */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK 1843200
+#define CONFIG_BAUDRATE 9600
+#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
+ 9600, 19200, 38400, 115200}
+#define CONFIG_SYS_NS16550_COM1 UART0_BASE
+#define CONFIG_SYS_NS16550_COM2 UART1_BASE
+#define CONFIG_SYS_NS16550_PORT_MAPPED
+
+/* max. 2 IDE busses */
+#define CONFIG_SYS_IDE_MAXBUS 1
+/* max. 2 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
+
+#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0170
+#define CONFIG_SYS_ATA_IDE1_OFFSET 0x01F0
+#define CONFIG_SYS_ATA_DATA_OFFSET 0
+#define CONFIG_SYS_ATA_REG_OFFSET 0
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x200
+
+
+#define CONFIG_SUPPORT_VFAT
+/************************************************************
+ * ATAPI support (experimental)
+ ************************************************************/
+#define CONFIG_ATAPI
+
+/************************************************************
+ * DISK Partition support
+ ************************************************************/
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION /* Experimental */
+
+
+/*-----------------------------------------------------------------------
+ * Video Configuration
+ */
+#undef CONFIG_VIDEO
+#undef CONFIG_CFB_CONSOLE
+
+/*-----------------------------------------------------------------------
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ECHO
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ITEST
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_XIMG
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_BOOTDELAY 2
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 115200
+#define CONFIG_KGDB_SER_INDEX 2
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "boot > "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + \
+ 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x01000000
+#define CONFIG_SYS_LOAD_ADDR 0x100000
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_X86_ISR_TIMER
+
+/*-----------------------------------------------------------------------
+ * SDRAM Configuration
+ */
+#define CONFIG_NR_DRAM_BANKS 4
+
+/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
+#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
+#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
+#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
+#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
+
+/*-----------------------------------------------------------------------
+ * CPU Features
+ */
+
+#define CONFIG_SYS_GENERIC_TIMER
+#define CONFIG_SYS_PCAT_INTERRUPTS
+#define CONFIG_SYS_NUM_IRQS 16
+
+/*-----------------------------------------------------------------------
+ * Memory organization:
+ * 32kB Stack
+ * 16kB Cache-As-RAM @ 0x19200000
+ * 256kB Monitor
+ * (128kB + Environment Sector Size) malloc pool
+ */
+#define CONFIG_SYS_STACK_SIZE (32 * 1024)
+#define CONFIG_SYS_INIT_SP_ADDR (256 * 1024 + 16 * 1024)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (0x20000 + 128 * 1024)
+/* Address of temporary Global Data */
+#define CONFIG_SYS_INIT_GD_ADDR (256 * 1024)
+
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/*-----------------------------------------------------------------------
+ * FLASH configuration
+ */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_MAX_FLASH_SECT 1
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+
+/*-----------------------------------------------------------------------
+ * Environment configuration
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x01000
+
+/*-----------------------------------------------------------------------
+ * PCI configuration
+ */
+#define CONFIG_PCI
+
+/*-----------------------------------------------------------------------
+ * Network device support
+ */
+#define CONFIG_NET_MULTI
+
+
+#endif /* __CONFIG_H */
--
1.7.3.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [U-Boot] [PATCH v4 4/5] x86: Add an implementation for a coreboot CPU
2011-11-17 0:27 [U-Boot] [PATCH v4 0/5] Add a coreboot board, CPU, and configuration, and target Gabe Black
` (2 preceding siblings ...)
2011-11-17 0:27 ` [U-Boot] [PATCH v4 3/5] x86: Add a preliminary coreboot configuration header Gabe Black
@ 2011-11-17 0:27 ` Gabe Black
2011-11-17 0:27 ` [U-Boot] [PATCH v4 5/5] x86: Make the serial port work for the coreboot board Gabe Black
4 siblings, 0 replies; 11+ messages in thread
From: Gabe Black @ 2011-11-17 0:27 UTC (permalink / raw)
To: u-boot
This is a skeleton implementation which always reports the size of memory
as 64 MB.
Signed-off-by: Gabe Black: <gabeblack@chromium.org>
---
arch/x86/cpu/coreboot/Makefile | 55 ++++++++++++++++++++++++++++++++++
arch/x86/cpu/coreboot/asm-offsets.c | 25 +++++++++++++++
arch/x86/cpu/coreboot/coreboot_car.S | 29 ++++++++++++++++++
arch/x86/cpu/coreboot/sdram.c | 39 ++++++++++++++++++++++++
4 files changed, 148 insertions(+), 0 deletions(-)
create mode 100644 arch/x86/cpu/coreboot/Makefile
create mode 100644 arch/x86/cpu/coreboot/asm-offsets.c
create mode 100644 arch/x86/cpu/coreboot/coreboot_car.S
create mode 100644 arch/x86/cpu/coreboot/sdram.c
diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile
new file mode 100644
index 0000000..0444399
--- /dev/null
+++ b/arch/x86/cpu/coreboot/Makefile
@@ -0,0 +1,55 @@
+#
+# Copyright (c) 2011 The Chromium OS Authors.
+#
+# (C) Copyright 2008
+# Graeme Russ, graeme.russ at gmail.com.
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2002
+# Daniel Engstr?m, Omicron Ceti AB, daniel at omicron.se.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)lib$(SOC).o
+
+COBJS-$(CONFIG_SYS_COREBOOT) += sdram.o
+
+SOBJS-$(CONFIG_SYS_COREBOOT) += coreboot_car.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/x86/cpu/coreboot/asm-offsets.c b/arch/x86/cpu/coreboot/asm-offsets.c
new file mode 100644
index 0000000..97937da
--- /dev/null
+++ b/arch/x86/cpu/coreboot/asm-offsets.c
@@ -0,0 +1,25 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <linux/kbuild.h>
+
+int main(void)
+{
+ DEFINE(GENERATED_GD_RELOC_OFF, offsetof(gd_t, reloc_off));
+ return 0;
+}
diff --git a/arch/x86/cpu/coreboot/coreboot_car.S b/arch/x86/cpu/coreboot/coreboot_car.S
new file mode 100644
index 0000000..3cc2575
--- /dev/null
+++ b/arch/x86/cpu/coreboot/coreboot_car.S
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010-2011
+ * Graeme Russ, <graeme.russ@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.section .text
+
+.globl car_init
+car_init:
+ jmp car_init_ret
diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c
new file mode 100644
index 0000000..b56085a
--- /dev/null
+++ b/arch/x86/cpu/coreboot/sdram.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010,2011
+ * Graeme Russ, <graeme.russ@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/u-boot-x86.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init_f(void)
+{
+ gd->ram_size = 64*1024*1024;
+ return 0;
+}
+
+int dram_init(void)
+{
+ return 0;
+}
--
1.7.3.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [U-Boot] [PATCH v4 5/5] x86: Make the serial port work for the coreboot board
2011-11-17 0:27 [U-Boot] [PATCH v4 0/5] Add a coreboot board, CPU, and configuration, and target Gabe Black
` (3 preceding siblings ...)
2011-11-17 0:27 ` [U-Boot] [PATCH v4 4/5] x86: Add an implementation for a coreboot CPU Gabe Black
@ 2011-11-17 0:27 ` Gabe Black
4 siblings, 0 replies; 11+ messages in thread
From: Gabe Black @ 2011-11-17 0:27 UTC (permalink / raw)
To: u-boot
Signed-off-by: Gabe Black <gabeblack@chromium.org>
---
include/serial.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/serial.h b/include/serial.h
index 5926244..d27b850 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -31,7 +31,7 @@ extern struct serial_device * default_serial_console (void);
defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \
defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \
- defined(CONFIG_TEGRA2)
+ defined(CONFIG_TEGRA2) || defined(CONFIG_SYS_COREBOOT)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
#if defined(CONFIG_SYS_NS16550_SERIAL)
--
1.7.3.1
^ permalink raw reply related [flat|nested] 11+ messages in thread