From mboxrd@z Thu Jan  1 00:00:00 1970
From: Shinya Kuribayashi <skuribay@pobox.com>
Date: Tue, 29 Nov 2011 01:48:14 +0900
Subject: [U-Boot] [PATCH 08/11] MIPS: add additional reserved vectors
 for MIPS24K and MIPS34K cores
In-Reply-To: <1322143076-20349-9-git-send-email-daniel.schwierzeck@googlemail.com>
References: <1322143076-20349-1-git-send-email-daniel.schwierzeck@googlemail.com>
	<1322143076-20349-9-git-send-email-daniel.schwierzeck@googlemail.com>
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On 11/24/11 10:57 PM, Daniel Schwierzeck wrote:
> @@ -206,11 +206,28 @@ _start:
>   	RVECENT(romReserved,125)
>   	RVECENT(romReserved,126)
>   	RVECENT(romReserved,127)
> +	XVECENT(romExcHandle,0x400);
> +	RVECENT(romReserved,129);
> +	RVECENT(romReserved,130);
> +	RVECENT(romReserved,131);
> +	RVECENT(romReserved,132);
> +	RVECENT(romReserved,133);
> +	RVECENT(romReserved,134);
> +	RVECENT(romReserved,135);
> +	RVECENT(romReserved,136);
> +	RVECENT(romReserved,137);
> +	RVECENT(romReserved,138);
> +	RVECENT(romReserved,139);
> +	RVECENT(romReserved,140);
> +	RVECENT(romReserved,141);
> +	RVECENT(romReserved,142);
> +	RVECENT(romReserved,143);
> +	XVECENT(romExcHandle,0x480);	# bfc00480: EJTAG debug exception
>
>   	/*
>   	 * We hope there are no more reserved vectors!
> -	 * 128 * 8 == 1024 == 0x400
> -	 * so this is address R_VEC+0x400 == 0xbfc00400
> +	 * 144 * 8 == 1152 == 0x480
> +	 * so this is address R_VEC+0x480 == 0xbfc00480
>   	 */
>   	.align 4
>   reset:

IIUC those exception vectors of +0x400/+0x480 have nothing to do with
24K processor core nor 34K either.

The change itself is Ok, and any other version taking Marek's comment
into account is also welcome.