[U-Boot] [PATCH 5/5 v2] mtd/nand: workaround for Freescale FCM to support 4k pagesize Nand chip

[Scott Wood <scottwood@freescale.com>]

On 12/12/2011 03:49 AM, Shengzhou Liu wrote:
> Freescale FCM controller has a 2K size limitation of buffer RAM. In order
> to support the Nand flash chip with pagesize larger than 2K bytes,
> we read/write 2k data repeatedly by issuing FIR_OP_RB/FIR_OP_WB and save
> them to a large buffer.
> 
> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
> Signed-off-by: Liu Shuo <b35362@freescale.com>
> ---
>  drivers/mtd/nand/fsl_elbc_nand.c |  283 +++++++++++++++++++++++++++++++++----
>  1 files changed, 252 insertions(+), 31 deletions(-)

I've asked you several times what you're planning on doing for bad block
marker migration.  I am not going to let you ignore this.  NACK until
you have a migration tool, and a scheme for marking the flash as having
been migrated.

Also please mention below the --- what has changed since v1.

> @@ -393,9 +468,28 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
>  		     page_addr, column);
>  
>  		ctrl->column = column;
> -		ctrl->oob = 0;
> +		if (column >= mtd->writesize) {
> +			/* OOB area */
> +			column -= mtd->writesize;
> +			ctrl->oob = 1;
> +		} else {
> +			ctrl->oob = 0;
> +		}
[snip]
> @@ -432,12 +524,19 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
>  		}
>  
>  		out_be32(&lbc->fcr, fcr);
> -		set_addr(mtd, column, page_addr, ctrl->oob);
> +		if (column >= mtd->writesize && mtd->writesize > 2048) {

How can column >= mtd->writesize be true at this point?  You've already
subtracted it out.

>  		if (ctrl->oob || ctrl->column != 0 ||
> -		    ctrl->index != mtd->writesize + mtd->oobsize)
> -			out_be32(&lbc->fbcr, ctrl->index);
> -		else
> +				ctrl->index != mtd->writesize + mtd->oobsize) {
> +			if (ctrl->oob && mtd->writesize > 2048) {
> +				out_be32(&lbc->fbcr, 64);
> +			} else {
> +				out_be32(&lbc->fbcr, ctrl->index -
> +					ctrl->column);
> +			}
> +		} else {
>  			out_be32(&lbc->fbcr, 0);
> +		}

Again, if we're going to make an API assumption that we get either a
full page access or a full OOB access, then make the assumption fully.
Don't half-implement partial accessses.

> +int board_nand_init_tail(struct mtd_info *mtd)
> +{
> +	struct nand_chip *nand = mtd->priv;
> +	struct fsl_elbc_mtd *priv = nand->priv;
> +	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
> +
> +	/* adjust Option Register and ECC to match Flash page size */
> +	if (mtd->writesize == 512) {
> +		clrbits_be32(&ctrl->regs->bank[priv->bank].or, OR_FCM_PGS);
> +	} else if (mtd->writesize >= 2048 && mtd->writesize <= 8192) {
> +		setbits_be32(&ctrl->regs->bank[priv->bank].or, OR_FCM_PGS);
> +		/* adjust ecc setup if needed */
> +		if ((in_be32(&ctrl->regs->bank[priv->bank].br) & BR_DECC) ==
> +			BR_DECC_CHK_GEN) {
> +			nand->ecc.size = 512;

Please find some way to indent the continuation line so it doesn't line
up with the if-body.

> +			nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
> +			   &fsl_elbc_oob_lp_eccm1 : &fsl_elbc_oob_lp_eccm0;
> +			nand->badblock_pattern = &largepage_memorybased;

Those oob layouts won't be quite right for larger page sizes.

-Scott