[U-Boot] [PATCH v4] ARMV7: Add support For Logic OMAP35x/DM37x modules

Igor Grinberg
2011-12-19T07:37:46Z

Hi Peter,

Thanks for fixing all the issues pointed.
I have one last question (sorry for not seeing it earlier) and one neat below.

On 12/18/11 19:25, Peter Barada wrote:
> This patch adds basic support for OMAP35x/DM37x SOM LV/Torpedo
> reference boards. It assumes U-boot is loaded to SDRAM with the
> help of another small bootloader (x-load) running from SRAM.
>
> Signed-off-by: Peter Barada <peter.barada@logicpd.com>
> Cc: Tom Rini <tom.rini@gmail.com>
> Cc: Igor Grinberg <grinberg@compulab.co.il>
> Cc: Wolfgang Denk <wd@denx.de>
> ---

[...]

> diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
> new file mode 100644
> index 0000000..3a5d3d5
> --- /dev/null
> +++ b/board/logicpd/omap3som/omap3logic.c

[...]

> +/*
> + * Routine: set_muxconf_regs
> + * Description: Setting up the configuration Mux registers specific to the
> + * hardware. Many pins need to be moved from protect to primary
> + * mode.
> + */
> +void set_muxconf_regs(void)
> +{

[...]

> + MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M7)); /*safe mode */

[...]

> + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M7)); /*safe mode */
> + /*DSS*/
> + MUX_VAL(CP(DSS_PCLK), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_HSYNC), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_VSYNC), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_ACBIAS), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA0), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA1), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA2), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA3), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA4), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA5), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA6), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA7), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA10), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA11), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA12), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA13), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA14), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA15), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA16), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA17), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA18), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA19), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA20), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA21), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA22), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(DSS_DATA23), (IEN | PTD | EN | M7)); /*safe mode */
> + /*CAMERA*/
> + MUX_VAL(CP(CAM_HS), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_VS), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_PCLK), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M7)); /*safe mode */
> + /*Audio Interface */
> + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M7)); /*safe mode */

[...]

> + MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC1_DAT7), (IEN | PTD | EN | M7)); /*safe mode*/
> + /*Wireless LAN */
> + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_CMD), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT4), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT5), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT6), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MMC2_DAT7), (IEN | PTD | EN | M7)); /*safe mode*/
> + /*Bluetooth*/
> + MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(UART2_CTS), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M7)); /*safe mode*/

[...]

> + MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | EN | M7)); /*safe mode*/
> +
> + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | EN | M7)); /*safe mode*/
> + /*Serial Interface*/
> + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(UART3_TX_IRTX), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_STP), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | EN | M7)); /*safe mode*/

[...]

> + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M7)); /*safe mode*/
> + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M7)); /*safe mode*/

[...]

> + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | EN | M7)); /*safe mode */
> + MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | EN | M7)); /*safe mode */

[...]

> + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*safe mode*/

The TRM says that the initial state of pins is the safe mode (M7).
Also not every pin has this state by definition.
So the question is, wouldn't it be better to remove those lines
that setup the safe mode, or is there a purpose, which I don't see?
Removing those lines will make the file/patch much shorter.

[...]

> diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
> new file mode 100644
> index 0000000..1a30f63
> --- /dev/null
> +++ b/include/configs/omap3_logic.h

[...]

> +/* DDR - I use Micron DDR */
> +#define CONFIG_OMAP3_MICRON_DDR

You forgot to remove that one - it is not used anymore...

[...]

--
Regards,
Igor.