From mboxrd@z Thu Jan 1 00:00:00 1970 From: Michal Simek Date: Thu, 22 Dec 2011 10:09:30 +0100 Subject: [U-Boot] [PATCH v2 3/9] openrisc: Add cpu files In-Reply-To: <1322370297-22892-4-git-send-email-stefan.kristiansson@saunalahti.fi> References: <1322370297-22892-1-git-send-email-stefan.kristiansson@saunalahti.fi> <1322370297-22892-4-git-send-email-stefan.kristiansson@saunalahti.fi> Message-ID: <4EF2F3CA.9080303@monstr.eu> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Stefan Kristiansson wrote: > Signed-off-by: Stefan Kristiansson > --- > > Changes in v2: > - Fix missing newline > - Bugfix for cache line size reading > - Make l.nop asm statements volatile > - Fix include order (asm after non-asm) > - Add static to functions only called locally > - Make unhandled exception printout into a look-up table > > arch/openrisc/config.mk | 27 ++++ > arch/openrisc/cpu/Makefile | 47 ++++++ > arch/openrisc/cpu/cache.c | 151 ++++++++++++++++++ > arch/openrisc/cpu/cpu.c | 157 +++++++++++++++++++ > arch/openrisc/cpu/exceptions.c | 85 ++++++++++ > arch/openrisc/cpu/interrupts.c | 121 +++++++++++++++ > arch/openrisc/cpu/start.S | 335 ++++++++++++++++++++++++++++++++++++++++ > 7 files changed, 923 insertions(+), 0 deletions(-) > create mode 100644 arch/openrisc/config.mk > create mode 100644 arch/openrisc/cpu/Makefile > create mode 100644 arch/openrisc/cpu/cache.c > create mode 100644 arch/openrisc/cpu/cpu.c > create mode 100644 arch/openrisc/cpu/exceptions.c > create mode 100644 arch/openrisc/cpu/interrupts.c > create mode 100644 arch/openrisc/cpu/start.S > > diff --git a/arch/openrisc/config.mk b/arch/openrisc/config.mk > new file mode 100644 > index 0000000..521e73a > --- /dev/null > +++ b/arch/openrisc/config.mk > @@ -0,0 +1,27 @@ > +# > +# (C) Copyright 2011 > +# Julius Baxter > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, > +# MA 02111-1307 USA > +# > + > +CROSS_COMPILE ?= or32-elf- > + > +# r10 used for global object pointer, already set in OR32 GCC but just to be > +# clear > +PLATFORM_CPPFLAGS += -DCONFIG_OPENRISC -D__OR1K__ -ffixed-r10 > + > +CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 > diff --git a/arch/openrisc/cpu/Makefile b/arch/openrisc/cpu/Makefile > new file mode 100644 > index 0000000..b3b1a24 > --- /dev/null > +++ b/arch/openrisc/cpu/Makefile > @@ -0,0 +1,47 @@ > +# > +# (C) Copyright 2011 > +# Julius Baxter > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, > +# MA 02111-1307 USA > +# > + > +include $(TOPDIR)/config.mk > + > +LIB = $(obj)lib$(CPU).o > + > +START = start.o > +COBJS-y = cache.o cpu.o exceptions.o interrupts.o > + > +SRCS := $(START:.o=.S) $(COBJS-y:.o=.c) > +OBJS := $(addprefix $(obj),$(COBJS-y)) > +START := $(addprefix $(obj),$(START)) > + > +all: $(obj).depend $(START) $(LIB) > + > +$(LIB): $(OBJS) > + $(call cmd_link_o_target, $(OBJS)) > + > +######################################################################### > + > +# defines $(obj).depend target > +include $(SRCTREE)/rules.mk > + > +sinclude $(obj).depend > + > +######################################################################### > diff --git a/arch/openrisc/cpu/cache.c b/arch/openrisc/cpu/cache.c > new file mode 100644 > index 0000000..2a73a4f > --- /dev/null > +++ b/arch/openrisc/cpu/cache.c > @@ -0,0 +1,151 @@ > +/* > + * (C) Copyright 2011, Stefan Kristiansson > + * (C) Copyright 2011, Julius Baxter > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#include > +#include > + > +void flush_dcache_range(unsigned long addr, unsigned long stop) > +{ > + ulong block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16; > + > + while (addr < stop) { > + mtspr(SPR_DCBFR, addr); > + addr += block_size; > + } > +} > + > +void invalidate_dcache_range(unsigned long addr, unsigned long stop) > +{ > + ulong block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16; > + > + while (addr < stop) { > + mtspr(SPR_DCBIR, addr); > + addr += block_size; > + } > +} > + > +static void invalidate_icache_range(unsigned long addr, unsigned long stop) > +{ > + ulong block_size = (mfspr(SPR_ICCFGR) & SPR_ICCFGR_CBS) ? 32 : 16; > + > + while (addr < stop) { > + mtspr(SPR_ICBIR, addr); > + addr += block_size; > + } > +} > + > +void flush_cache(unsigned long addr, unsigned long size) > +{ > + flush_dcache_range(addr, addr + size); > + invalidate_icache_range(addr, addr + size); > +} > + > +int icache_status(void) > +{ > + return mfspr(SPR_SR) & SPR_SR_ICE; > +} > + > +int checkicache(void) > +{ > + unsigned long iccfgr; > + unsigned long cache_set_size; > + unsigned long cache_ways; > + unsigned long cache_block_size; > + > + iccfgr = mfspr(SPR_ICCFGR); > + cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW); > + cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3); > + cache_block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16; > + > + return cache_set_size * cache_ways * cache_block_size; > +} > + > +int dcache_status(void) > +{ > + return mfspr(SPR_SR) & SPR_SR_DCE; > +} > + > +int checkdcache(void) > +{ > + unsigned long dccfgr; > + unsigned long cache_set_size; > + unsigned long cache_ways; > + unsigned long cache_block_size; > + > + dccfgr = mfspr(SPR_DCCFGR); > + cache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW); > + cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3); > + cache_block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16; > + > + return cache_set_size * cache_ways * cache_block_size; > +} > + > +void dcache_enable(void) > +{ > + mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_DCE); > + asm volatile("l.nop"); > + asm volatile("l.nop"); > + asm volatile("l.nop"); > + asm volatile("l.nop"); > + asm volatile("l.nop"); > + asm volatile("l.nop"); > + asm volatile("l.nop"); > + asm volatile("l.nop"); This is interesting. Are there 8 nops? Is there any reason for that? Is it just any waiting? If yes, maybe it will be worth to add any comment. Michal -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian