[U-Boot] [PATCH v2] add nand spl boot for qi_lb60 board

[U-Boot] [PATCH v2] add nand spl boot for qi_lb60 board

[Xiangfu Liu]

Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net>
---
 arch/mips/cpu/xburst/cpu.c           |    4 +
 arch/mips/cpu/xburst/start_spl.S     |   65 ++++++++++++++++++++
 drivers/mtd/nand/jz4740_nand.c       |   40 +++++++++++-
 include/configs/qi_lb60.h            |    3 +
 nand_spl/board/qi/qi_lb60/Makefile   |  112 ++++++++++++++++++++++++++++++++++
 nand_spl/board/qi/qi_lb60/nand_spl.c |   37 +++++++++++
 nand_spl/board/qi/qi_lb60/u-boot.lds |   63 +++++++++++++++++++
 7 files changed, 321 insertions(+), 3 deletions(-)
 create mode 100644 arch/mips/cpu/xburst/start_spl.S
 create mode 100644 nand_spl/board/qi/qi_lb60/Makefile
 create mode 100644 nand_spl/board/qi/qi_lb60/nand_spl.c
 create mode 100644 nand_spl/board/qi/qi_lb60/u-boot.lds

diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
index e976341..afd166c 100644
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@@ -42,6 +42,8 @@
 		:			\
 		: "i" (op), "R" (*(unsigned char *)(addr)))
 
+#ifndef CONFIG_NAND_SPL
+
 void __attribute__((weak)) _machine_restart(void)
 {
 	struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
@@ -109,6 +111,8 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
 		cache_op(Hit_Invalidate_D, addr);
 }
 
+#endif
+
 void flush_icache_all(void)
 {
 	u32 addr, t = 0;
diff --git a/arch/mips/cpu/xburst/start_spl.S b/arch/mips/cpu/xburst/start_spl.S
new file mode 100644
index 0000000..f137ccd
--- /dev/null
+++ b/arch/mips/cpu/xburst/start_spl.S
@@ -0,0 +1,65 @@
+/*
+ *  Startup Code for MIPS32 XBURST CPU-core
+ *
+ *  Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 3 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/cacheops.h>
+
+#include <asm/jz4740.h>
+
+	.set noreorder
+
+	.globl _start
+	.text
+_start:
+	.word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */
+reset:
+	/*
+	 * STATUS register
+	 * CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
+	 */
+	li	t0, 0x0040FC04
+	mtc0	t0, CP0_STATUS
+	/*
+	 * CAUSE register
+	 * IV=1, use the specical interrupt vector (0x200)
+	 */
+	li	t1, 0x00800000
+	mtc0	t1, CP0_CAUSE
+
+	bal     1f
+	 nop
+	.word   _GLOBAL_OFFSET_TABLE_
+1:
+	move    gp, ra
+	lw      t1, 0(ra)
+	move	gp, t1
+
+	la	sp, 0x80004000
+	la	t9, nand_spl_boot
+	j	t9
+	 nop
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
index 3ec34f3..7ef07a5 100644
--- a/drivers/mtd/nand/jz4740_nand.c
+++ b/drivers/mtd/nand/jz4740_nand.c
@@ -15,6 +15,10 @@
 #include <asm/io.h>
 #include <asm/jz4740.h>
 
+#ifdef CONFIG_NAND_SPL
+  #define printf(arg...) do {} while (0)
+#endif
+
 #define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
 #define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
 #define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
@@ -176,7 +180,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
 		for (k = 0; k < 9; k++)
 			writeb(read_ecc[k], &emc->nfpar[k]);
 	}
-	/* Set PRDY */
+
 	writel(readl(&emc->nfecr) | EMC_NFECR_PRDY, &emc->nfecr);
 
 	/* Wait for completion */
@@ -184,7 +188,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
 		status = readl(&emc->nfints);
 	} while (!(status & EMC_NFINTS_DECF));
 
-	/* disable ecc */
+	/* Disable ECC */
 	writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
 
 	/* Check decoding */
@@ -192,7 +196,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
 		return 0;
 
 	if (status & EMC_NFINTS_UNCOR) {
-		printf("uncorrectable ecc\n");
+		printf("JZ4740 uncorrectable ECC\n");
 		return -1;
 	}
 
@@ -230,6 +234,32 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
 	return errcnt;
 }
 
+#ifdef CONFIG_NAND_SPL
+void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	int i;
+	struct nand_chip *this = mtd->priv;
+
+#if (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R3) || \
+	(JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R2)
+	for (i = 0; i < len; i += 2)
+		buf[i] = readw(this->IO_ADDR_R);
+#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R3) || \
+	(JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R2)
+	for (i = 0; i < len; i++)
+		buf[i] = readb(this->IO_ADDR_R);
+#else
+	#error JZ4740_NANDBOOT_CFG not defined or wrong
+#endif
+}
+
+uint8_t nand_read_byte(struct mtd_info *mtd)
+{
+	struct nand_chip *this = mtd->priv;
+	return readb(this->IO_ADDR_R);
+}
+#endif
+
 /*
  * Main initialization routine
  */
@@ -247,6 +277,10 @@ int board_nand_init(struct nand_chip *nand)
 	nand->IO_ADDR_W		= JZ_NAND_DATA_ADDR;
 	nand->cmd_ctrl		= jz_nand_cmd_ctrl;
 	nand->dev_ready		= jz_nand_device_ready;
+#ifdef CONFIG_NAND_SPL
+	nand->read_byte		= nand_read_byte;
+	nand->read_buf		= nand_read_buf;
+#endif
 	nand->ecc.hwctl		= jz_nand_hwctl;
 	nand->ecc.correct	= jz_nand_rs_correct_data;
 	nand->ecc.calculate	= jz_nand_rs_calculate_ecc;
diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h
index f989595..c40e4cc 100644
--- a/include/configs/qi_lb60.h
+++ b/include/configs/qi_lb60.h
@@ -35,6 +35,9 @@
 #define CONFIG_BOOTARGS		"mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
 #define CONFIG_BOOTCOMMAND	"nand read 0x80600000 0x400000 0x200000;bootm"
 
+#define JZ4740_NANDBOOT_CFG	JZ4740_NANDBOOT_B8R3
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+
 /*
  * Command line configuration.
  */
diff --git a/nand_spl/board/qi/qi_lb60/Makefile b/nand_spl/board/qi/qi_lb60/Makefile
new file mode 100644
index 0000000..0c4113d
--- /dev/null
+++ b/nand_spl/board/qi/qi_lb60/Makefile
@@ -0,0 +1,112 @@
+#
+# (C) Copyright 2006
+# Stefan Roese, DENX Software Engineering, sr at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_NAND_SPL_TEXT_BASE)
+AFLAGS	+= -DCONFIG_NAND_SPL
+CFLAGS	+= -DCONFIG_NAND_SPL -O2
+
+SOBJS	= start.o
+COBJS	= cpu.o jz4740.o jz_serial.o jz4740_nand.o nand_spl.o nand_boot.o
+
+SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS	:= $(SOBJS) $(COBJS)
+LNDIR	:= $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj	:= $(OBJTREE)/nand_spl/
+
+ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+all:	$(obj).depend $(ALL)
+
+# The JZ4740 CPU can load two areas of data from NAND flash to internal SRAM,
+# one is the normal area up to 8KB starting from NAND flash address 0, the
+# other is the backup area up to 8KB starting from NAND flash address 0x2000.
+
+# After reset, the boot program will first read the normal area data from NAND
+# flash using hardware Reed-Solomon ECC. If no ECC error is detected or ECC
+# error is correctable, the boot program then branches to internal SRAM at 4
+# bytes offset. ff it detects an uncorrectable ECC error, it will continue to
+# read the backup area of data from NAND flash using hardware Reed-Solomon ECC.
+
+# those 'dd' commands is for create such two 8KB for JZ4740 CPU
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin
+	dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1
+	cat $< $(nandobj)junk1 > $(nandobj)junk2
+	dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3
+	cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4
+	dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5
+	cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6
+	dd bs=1024 count=256 if=$(nandobj)junk6 of=$@
+	rm -f $(nandobj)junk*
+
+$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl:	$(OBJS)
+	cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
+		-Map $(nandobj)u-boot-spl.map \
+		-o $(nandobj)u-boot-spl
+
+# create symbolic links for common files
+$(obj)start.S:
+	@rm -f $@
+	ln -s $(SRCTREE)/arch/mips/cpu/xburst/start_spl.S $@
+
+$(obj)cpu.c:
+	@rm -f $@
+	ln -s $(SRCTREE)/arch/mips/cpu/xburst/cpu.c $@
+
+$(obj)jz4740.c:
+	@rm -f $@
+	ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz4740.c $@
+
+$(obj)jz_serial.c:
+	@rm -f $@
+	ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz_serial.c $@
+
+$(obj)jz4740_nand.c:
+	@rm -f $@
+	ln -s $(TOPDIR)/drivers/mtd/nand/jz4740_nand.c $@
+
+$(obj)nand_boot.c:
+	@rm -f $@
+	ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
+
+ifneq ($(OBJTREE), $(SRCTREE))
+$(obj)nand_spl.c:
+	@rm -f $@
+	ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_spl.c $@
+endif
+
+$(obj)%.o:	$(obj)%.S
+	$(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o:	$(obj)%.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/nand_spl/board/qi/qi_lb60/nand_spl.c b/nand_spl/board/qi/qi_lb60/nand_spl.c
new file mode 100644
index 0000000..6a0358a
--- /dev/null
+++ b/nand_spl/board/qi/qi_lb60/nand_spl.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2012 Xiangfu Liu <xiangfu@sharism.cc>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+
+#include <nand.h>
+#include <asm/io.h>
+#include <asm/jz4740.h>
+
+void nand_spl_boot(void)
+{
+	__gpio_as_sdram_16bit_4720();
+	__gpio_as_uart0();
+
+	pll_init();
+	serial_init();
+	sdram_init();
+
+	nand_boot();
+}
diff --git a/nand_spl/board/qi/qi_lb60/u-boot.lds b/nand_spl/board/qi/qi_lb60/u-boot.lds
new file mode 100644
index 0000000..7042388
--- /dev/null
+++ b/nand_spl/board/qi/qi_lb60/u-boot.lds
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2005
+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text       :
+	{
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata  : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data  : { *(.data) }
+
+	. = ALIGN(4);
+	.sdata  : { *(.sdata) }
+
+	_gp = ALIGN(16);
+
+	__got_start = .;
+	.got  : { *(.got) }
+	__got_end = .;
+
+	.sdata  : { *(.sdata) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	uboot_end_data = .;
+	num_got_entries = (__got_end - __got_start) >> 2;
+
+	. = ALIGN(4);
+	.sbss  : { *(.sbss) }
+	.bss  : { *(.bss) }
+	uboot_end = .;
+}
-- 
1.7.5.4

[U-Boot] [PATCH v2] add nand spl boot for qi_lb60 board

[Scott Wood]

On 01/06/2012 04:17 AM, Xiangfu Liu wrote:
> Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net>
> ---
>  arch/mips/cpu/xburst/cpu.c           |    4 +
>  arch/mips/cpu/xburst/start_spl.S     |   65 ++++++++++++++++++++
>  drivers/mtd/nand/jz4740_nand.c       |   40 +++++++++++-
>  include/configs/qi_lb60.h            |    3 +
>  nand_spl/board/qi/qi_lb60/Makefile   |  112 ++++++++++++++++++++++++++++++++++
>  nand_spl/board/qi/qi_lb60/nand_spl.c |   37 +++++++++++
>  nand_spl/board/qi/qi_lb60/u-boot.lds |   63 +++++++++++++++++++
>  7 files changed, 321 insertions(+), 3 deletions(-)
>  create mode 100644 arch/mips/cpu/xburst/start_spl.S
>  create mode 100644 nand_spl/board/qi/qi_lb60/Makefile
>  create mode 100644 nand_spl/board/qi/qi_lb60/nand_spl.c
>  create mode 100644 nand_spl/board/qi/qi_lb60/u-boot.lds

We are transitioning from nand_spl/ to spl/.  Please try to work within
the new infrastructure.  You may run into problems with size in spl/,
due to gc-sections not removing strings on components you don't need --
I plan to fix those issues (for NAND), hopefully this merge window, by
requiring all files to be explicitly asked for.  Feel free to fix them
first if you'd like. :-)

> diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
> index e976341..afd166c 100644
> --- a/arch/mips/cpu/xburst/cpu.c
> +++ b/arch/mips/cpu/xburst/cpu.c
> @@ -42,6 +42,8 @@
>  		:			\
>  		: "i" (op), "R" (*(unsigned char *)(addr)))
>  
> +#ifndef CONFIG_NAND_SPL
> +
>  void __attribute__((weak)) _machine_restart(void)
>  {
>  	struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
> @@ -109,6 +111,8 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
>  		cache_op(Hit_Invalidate_D, addr);
>  }
>  
> +#endif
> +
>  void flush_icache_all(void)
>  {
>  	u32 addr, t = 0;
> diff --git a/arch/mips/cpu/xburst/start_spl.S b/arch/mips/cpu/xburst/start_spl.S
> new file mode 100644
> index 0000000..f137ccd
> --- /dev/null
> +++ b/arch/mips/cpu/xburst/start_spl.S
> @@ -0,0 +1,65 @@
> +/*
> + *  Startup Code for MIPS32 XBURST CPU-core
> + *
> + *  Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 3 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <config.h>
> +#include <version.h>
> +#include <asm/regdef.h>
> +#include <asm/mipsregs.h>
> +#include <asm/addrspace.h>
> +#include <asm/cacheops.h>
> +
> +#include <asm/jz4740.h>
> +
> +	.set noreorder
> +
> +	.globl _start
> +	.text
> +_start:
> +	.word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */
> +reset:
> +	/*
> +	 * STATUS register
> +	 * CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
> +	 */
> +	li	t0, 0x0040FC04
> +	mtc0	t0, CP0_STATUS
> +	/*
> +	 * CAUSE register
> +	 * IV=1, use the specical interrupt vector (0x200)
> +	 */
> +	li	t1, 0x00800000
> +	mtc0	t1, CP0_CAUSE
> +
> +	bal     1f
> +	 nop
> +	.word   _GLOBAL_OFFSET_TABLE_
> +1:
> +	move    gp, ra
> +	lw      t1, 0(ra)
> +	move	gp, t1
> +
> +	la	sp, 0x80004000
> +	la	t9, nand_spl_boot
> +	j	t9
> +	 nop

Shinya, do the MIPS parts look OK?

> +include $(TOPDIR)/config.mk
> +
> +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
> +LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_NAND_SPL_TEXT_BASE)
> +AFLAGS	+= -DCONFIG_NAND_SPL
> +CFLAGS	+= -DCONFIG_NAND_SPL -O2

Why -O2 and not the -Os that you should already be inheriting from
config.mk?

> +# The JZ4740 CPU can load two areas of data from NAND flash to internal SRAM,
> +# one is the normal area up to 8KB starting from NAND flash address 0, the
> +# other is the backup area up to 8KB starting from NAND flash address 0x2000.
> +
> +# After reset, the boot program will first read the normal area data from NAND
> +# flash using hardware Reed-Solomon ECC. If no ECC error is detected or ECC
> +# error is correctable, the boot program then branches to internal SRAM at 4
> +# bytes offset. ff it detects an uncorrectable ECC error, it will continue to
> +# read the backup area of data from NAND flash using hardware Reed-Solomon ECC.

Why must the payload come at offset 256K, rather than 16K?

> +
> +# those 'dd' commands is for create such two 8KB for JZ4740 CPU
> +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin
> +	dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1
> +	cat $< $(nandobj)junk1 > $(nandobj)junk2
> +	dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3
> +	cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4
> +	dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5
> +	cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6
> +	dd bs=1024 count=256 if=$(nandobj)junk6 of=$@
> +	rm -f $(nandobj)junk*

This is overcomplicated and difficult to follow.

Try something like this:

# This target is misnamed, but that's the toplevel Makefile's fault
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin
	dd if=$< of=$@ conv=sync bs=8192 count=1
	dd if=$< of=$@ conv=sync,notrunc oflag=append \
		bs=8192 count=1
	dd if=/dev/zero of=$@ conv=sync,notrunc oflag=append \
		bs=245760 count=1

Or consider using --pad-to or the linker script to add the 8K padding
(also add an assert for too-large like
arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds does).  If you also get rid
of the need to pad to 256k, this step then becomes "cat $< $< > $@".

> diff --git a/nand_spl/board/qi/qi_lb60/u-boot.lds b/nand_spl/board/qi/qi_lb60/u-boot.lds
> new file mode 100644
> index 0000000..7042388
> --- /dev/null
> +++ b/nand_spl/board/qi/qi_lb60/u-boot.lds
> @@ -0,0 +1,63 @@
> +/*
> + * (C) Copyright 2005
> + * Ingenic Semiconductor, <jlwei@ingenic.cn>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
> +
> +OUTPUT_ARCH(mips)
> +ENTRY(_start)
> +SECTIONS
> +{
> +	. = 0x00000000;

include/configs/qi_lb60.h says CONFIG_NAND_SPL_TEXT_BASE is 0x80000000,
not zero.

-Scott

[U-Boot] [PATCH v3] add nand spl boot for qi_lb60 board

[Xiangfu Liu]

Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net>
---

Changes for v2:
 -Add CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 -Cleanup jz4740_nand.c a little

Changes for v3:
 -Remove CONFIG_NAND_SPL_TEXT_BASE, fix the wrong TEXT base under SPL u-boot.lds
 -Remove overcomplicated 'dd', pad to 32KB SPL instead of 256. comments added in Makefile
 -Cleanup the qi_lb60.h 

 arch/mips/cpu/xburst/cpu.c           |    4 +
 arch/mips/cpu/xburst/start_spl.S     |   65 +++++++++++++
 drivers/mtd/nand/jz4740_nand.c       |   40 ++++++++-
 include/configs/qi_lb60.h            |  166 ++++++++++++++++------------------
 nand_spl/board/qi/qi_lb60/Makefile   |  124 +++++++++++++++++++++++++
 nand_spl/board/qi/qi_lb60/nand_spl.c |   37 ++++++++
 nand_spl/board/qi/qi_lb60/u-boot.lds |   62 +++++++++++++
 7 files changed, 407 insertions(+), 91 deletions(-)
 create mode 100644 arch/mips/cpu/xburst/start_spl.S
 create mode 100644 nand_spl/board/qi/qi_lb60/Makefile
 create mode 100644 nand_spl/board/qi/qi_lb60/nand_spl.c
 create mode 100644 nand_spl/board/qi/qi_lb60/u-boot.lds

diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
index e976341..afd166c 100644
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@@ -42,6 +42,8 @@
 		:			\
 		: "i" (op), "R" (*(unsigned char *)(addr)))
 
+#ifndef CONFIG_NAND_SPL
+
 void __attribute__((weak)) _machine_restart(void)
 {
 	struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
@@ -109,6 +111,8 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
 		cache_op(Hit_Invalidate_D, addr);
 }
 
+#endif
+
 void flush_icache_all(void)
 {
 	u32 addr, t = 0;
diff --git a/arch/mips/cpu/xburst/start_spl.S b/arch/mips/cpu/xburst/start_spl.S
new file mode 100644
index 0000000..f137ccd
--- /dev/null
+++ b/arch/mips/cpu/xburst/start_spl.S
@@ -0,0 +1,65 @@
+/*
+ *  Startup Code for MIPS32 XBURST CPU-core
+ *
+ *  Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 3 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/cacheops.h>
+
+#include <asm/jz4740.h>
+
+	.set noreorder
+
+	.globl _start
+	.text
+_start:
+	.word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */
+reset:
+	/*
+	 * STATUS register
+	 * CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
+	 */
+	li	t0, 0x0040FC04
+	mtc0	t0, CP0_STATUS
+	/*
+	 * CAUSE register
+	 * IV=1, use the specical interrupt vector (0x200)
+	 */
+	li	t1, 0x00800000
+	mtc0	t1, CP0_CAUSE
+
+	bal     1f
+	 nop
+	.word   _GLOBAL_OFFSET_TABLE_
+1:
+	move    gp, ra
+	lw      t1, 0(ra)
+	move	gp, t1
+
+	la	sp, 0x80004000
+	la	t9, nand_spl_boot
+	j	t9
+	 nop
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
index 3ec34f3..7ef07a5 100644
--- a/drivers/mtd/nand/jz4740_nand.c
+++ b/drivers/mtd/nand/jz4740_nand.c
@@ -15,6 +15,10 @@
 #include <asm/io.h>
 #include <asm/jz4740.h>
 
+#ifdef CONFIG_NAND_SPL
+  #define printf(arg...) do {} while (0)
+#endif
+
 #define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
 #define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
 #define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
@@ -176,7 +180,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
 		for (k = 0; k < 9; k++)
 			writeb(read_ecc[k], &emc->nfpar[k]);
 	}
-	/* Set PRDY */
+
 	writel(readl(&emc->nfecr) | EMC_NFECR_PRDY, &emc->nfecr);
 
 	/* Wait for completion */
@@ -184,7 +188,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
 		status = readl(&emc->nfints);
 	} while (!(status & EMC_NFINTS_DECF));
 
-	/* disable ecc */
+	/* Disable ECC */
 	writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
 
 	/* Check decoding */
@@ -192,7 +196,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
 		return 0;
 
 	if (status & EMC_NFINTS_UNCOR) {
-		printf("uncorrectable ecc\n");
+		printf("JZ4740 uncorrectable ECC\n");
 		return -1;
 	}
 
@@ -230,6 +234,32 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
 	return errcnt;
 }
 
+#ifdef CONFIG_NAND_SPL
+void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	int i;
+	struct nand_chip *this = mtd->priv;
+
+#if (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R3) || \
+	(JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R2)
+	for (i = 0; i < len; i += 2)
+		buf[i] = readw(this->IO_ADDR_R);
+#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R3) || \
+	(JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R2)
+	for (i = 0; i < len; i++)
+		buf[i] = readb(this->IO_ADDR_R);
+#else
+	#error JZ4740_NANDBOOT_CFG not defined or wrong
+#endif
+}
+
+uint8_t nand_read_byte(struct mtd_info *mtd)
+{
+	struct nand_chip *this = mtd->priv;
+	return readb(this->IO_ADDR_R);
+}
+#endif
+
 /*
  * Main initialization routine
  */
@@ -247,6 +277,10 @@ int board_nand_init(struct nand_chip *nand)
 	nand->IO_ADDR_W		= JZ_NAND_DATA_ADDR;
 	nand->cmd_ctrl		= jz_nand_cmd_ctrl;
 	nand->dev_ready		= jz_nand_device_ready;
+#ifdef CONFIG_NAND_SPL
+	nand->read_byte		= nand_read_byte;
+	nand->read_buf		= nand_read_buf;
+#endif
 	nand->ecc.hwctl		= jz_nand_hwctl;
 	nand->ecc.correct	= jz_nand_rs_correct_data;
 	nand->ecc.calculate	= jz_nand_rs_calculate_ecc;
diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h
index f989595..16a755e 100644
--- a/include/configs/qi_lb60.h
+++ b/include/configs/qi_lb60.h
@@ -1,5 +1,5 @@
 /*
- * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
+ * Authors: Xiangfu Liu <xiangfu@openmobilefree.net>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -13,7 +13,6 @@
 #define CONFIG_MIPS32		/* MIPS32 CPU core */
 #define CONFIG_JZSOC		/* Jz SoC */
 #define CONFIG_JZ4740		/* Jz4740 SoC */
-#define CONFIG_NAND_JZ4740
 
 #define CONFIG_SYS_CPU_SPEED	336000000	/* CPU clock: 336 MHz */
 #define CONFIG_SYS_EXTAL	12000000	/* EXTAL freq: 12 MHz */
@@ -24,24 +23,43 @@
 #define CONFIG_BAUDRATE		57600
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAUL)
+#define CONFIG_BOOTDELAY	0
+#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
+#define CONFIG_BOOTCOMMAND	"nand read 0x80600000 0x400000 0x280000;bootm"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000	/* Cached addr */
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+#define CONFIG_SYS_LOAD_ADDR		0x80600000
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#define CONFIG_SYS_MEMTEST_END		0x80A00000
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
+
+#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_PROMPT	"NanoNote# "
+
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_SYS_FLASH_BASE	0 /* init flash_base as 0 */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAUL)
-#define CONFIG_BOOTDELAY	0
-#define CONFIG_BOOTARGS		"mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
-#define CONFIG_BOOTCOMMAND	"nand read 0x80600000 0x400000 0x200000;bootm"
 
 /*
- * Command line configuration.
+ * Command line configuration
  */
 #define CONFIG_CMD_BOOTD	/* bootd			*/
 #define CONFIG_CMD_CONSOLE	/* coninfo			*/
 #define CONFIG_CMD_ECHO		/* echo arguments		*/
-
 #define CONFIG_CMD_LOADB	/* loadb			*/
 #define CONFIG_CMD_LOADS	/* loads			*/
 #define CONFIG_CMD_MEMORY	/* md mm nm mw cp cmp crc base loop mtest */
@@ -58,45 +76,16 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 
 /*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT "NanoNote# "
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-
-#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
-#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
-
-#define CONFIG_SYS_SDRAM_BASE		0x80000000	/* Cached addr */
-#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
-#define CONFIG_SYS_LOAD_ADDR		0x80600000
-#define CONFIG_SYS_MEMTEST_START	0x80100000
-#define CONFIG_SYS_MEMTEST_END		0x80800000
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_NAND		/* use NAND for environment vars */
-
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-/*
- * if board nand flash is 1GB, set to 1
- * if board nand flash is 2GB, set to 2
- * for change the PAGE_SIZE and BLOCK_SIZE
- * will delete when there is no 1GB flash
+ * NAND driver configuration
  */
-#define NANONOTE_NAND_SIZE	2
-
-#define CONFIG_SYS_NAND_PAGE_SIZE	(2048 * NANONOTE_NAND_SIZE)
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(256 * NANONOTE_NAND_SIZE << 10)
-/* nand bad block was marked at this page in a block, start from 0 */
+#define CONFIG_NAND_JZ4740
+#define CONFIG_SYS_NAND_PAGE_SIZE	4096
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(512 << 10)
+/* NAND bad block was marked at this page in a block, start from 0 */
 #define CONFIG_SYS_NAND_BADBLOCK_PAGE	127
 #define CONFIG_SYS_NAND_PAGE_COUNT	128
 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
-/* ECC offset position in oob area, default value is 6 if it isn't defined */
-#define CONFIG_SYS_NAND_ECC_POS		(6 * NANONOTE_NAND_SIZE)
+#define CONFIG_SYS_NAND_ECC_POS		12
 #define CONFIG_SYS_NAND_ECCSIZE		512
 #define CONFIG_SYS_NAND_ECCBYTES	9
 #define CONFIG_SYS_NAND_ECCSTEPS	\
@@ -120,10 +109,9 @@
 #define NAND_MAX_CHIPS			1
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_SELECT_DEVICE	1 /* nand driver supports mutipl.*/
-#define CONFIG_NAND_SPL_TEXT_BASE	0x80000000
 
 /*
- * IPL (Initial Program Loader, integrated inside CPU)
+ * IPL (Initial Program Loader, integrated inside Ingenic Xburst JZ4740 CPU)
  * Will load first 8k from NAND (SPL) into cache and execute it from there.
  *
  * SPL (Secondary Program Loader)
@@ -135,77 +123,79 @@
  * NUB (NAND U-Boot)
  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
- *
  */
+
+/*
+ * NAND SPL configuration
+ */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define JZ4740_NANDBOOT_CFG		JZ4740_NANDBOOT_B8R3
+
 #define CONFIG_SYS_NAND_U_BOOT_DST	0x80100000 /* Load NUB to this addr */
 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
-/* Start NUB from this addr*/
+					/* Start NUB from this addr */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (32  << 10) /* Offset of NUB */
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (256 << 10) /* Size of NUB */
 
 /*
- * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
+ * Environment configuration
  */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
-
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE		(4 << 10)
 #define CONFIG_ENV_OFFSET	\
 	(CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE)
 #define CONFIG_ENV_OFFSET_REDUND \
 	(CONFIG_ENV_OFFSET  + CONFIG_SYS_NAND_BLOCK_SIZE)
 
-#define CONFIG_SYS_TEXT_BASE	0x80100000
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-
 /*
- * SDRAM Info.
+ * CPU cache configuration
  */
-#define CONFIG_NR_DRAM_BANKS	1
+#define CONFIG_SYS_DCACHE_SIZE		16384
+#define CONFIG_SYS_ICACHE_SIZE		16384
+#define CONFIG_SYS_CACHELINE_SIZE	32
 
 /*
- * Cache Configuration
+ * SDRAM configuration
  */
-#define CONFIG_SYS_DCACHE_SIZE	16384
-#define CONFIG_SYS_ICACHE_SIZE	16384
-#define CONFIG_SYS_CACHELINE_SIZE	32
+#define CONFIG_NR_DRAM_BANKS	1
+
+#define SDRAM_BW16		1	/* Data bus width: 0-32bit, 1-16bit */
+#define SDRAM_BANK4		1	/* Banks each chip: 0-2bank, 1-4bank */
+#define SDRAM_ROW		13	/* Row address: 11 to 13 */
+#define SDRAM_COL		9	/* Column address: 8 to 12 */
+#define SDRAM_CASL		2	/* CAS latency: 2 or 3 */
+#define SDRAM_TRAS		45	/* RAS# Active Time */
+#define SDRAM_RCD		20	/* RAS# to CAS# Delay */
+#define SDRAM_TPC		20	/* RAS# Precharge Time */
+#define SDRAM_TRWL		7	/* Write Latency Time */
+#define SDRAM_TREF		15625	/* Refresh period: 8192 cycles/64ms */
 
 /*
- * GPIO definition
+ * GPIO configuration
  */
-#define GPIO_LCD_CS	(2 * 32 + 21)
-#define GPIO_AMP_EN	(3 * 32 + 4)
+#define GPIO_LCD_CS		(2 * 32 + 21)
+#define GPIO_AMP_EN		(3 * 32 + 4)
 
-#define GPIO_SDPW_EN	(3 * 32 + 2)
-#define GPIO_SD_DETECT	(3 * 32 + 0)
+#define GPIO_SDPW_EN		(3 * 32 + 2)
+#define GPIO_SD_DETECT		(3 * 32 + 0)
 
-#define GPIO_BUZZ_PWM	(3 * 32 + 27)
-#define GPIO_USB_DETECT	(3 * 32 + 28)
+#define GPIO_BUZZ_PWM		(3 * 32 + 27)
+#define GPIO_USB_DETECT		(3 * 32 + 28)
 
-#define GPIO_AUDIO_POP	(1 * 32 + 29)
-#define GPIO_COB_TEST	(1 * 32 + 30)
+#define GPIO_AUDIO_POP		(1 * 32 + 29)
+#define GPIO_COB_TEST		(1 * 32 + 30)
 
 #define GPIO_KEYOUT_BASE	(2 * 32 + 10)
-#define GPIO_KEYIN_BASE	(3 * 32 + 18)
-#define GPIO_KEYIN_8	(3 * 32 + 26)
+#define GPIO_KEYIN_BASE		(3 * 32 + 18)
+#define GPIO_KEYIN_8		(3 * 32 + 26)
 
-#define GPIO_SD_CD_N	GPIO_SD_DETECT		/* SD Card insert detect */
+#define GPIO_SD_CD_N		GPIO_SD_DETECT	/* SD Card insert detect */
 #define GPIO_SD_VCC_EN_N	GPIO_SDPW_EN	/* SD Card Power Enable */
 
 #define SPEN	GPIO_LCD_CS	/* LCDCS :Serial command enable      */
 #define SPDA	(2 * 32 + 22)	/* LCDSCL:Serial command clock input */
 #define SPCK	(2 * 32 + 23)	/* LCDSDA:Serial command data input  */
 
-/* SDRAM paramters */
-#define SDRAM_BW16		1	/* Data bus width: 0-32bit, 1-16bit */
-#define SDRAM_BANK4		1	/* Banks each chip: 0-2bank, 1-4bank */
-#define SDRAM_ROW		13	/* Row address: 11 to 13 */
-#define SDRAM_COL		9	/* Column address: 8 to 12 */
-#define SDRAM_CASL		2	/* CAS latency: 2 or 3 */
-
-/* SDRAM Timings, unit: ns */
-#define SDRAM_TRAS		45	/* RAS# Active Time */
-#define SDRAM_RCD		20	/* RAS# to CAS# Delay */
-#define SDRAM_TPC		20	/* RAS# Precharge Time */
-#define SDRAM_TRWL		7	/* Write Latency Time */
-#define SDRAM_TREF		15625	/* Refresh period: 8192 cycles/64ms */
-
 #endif
diff --git a/nand_spl/board/qi/qi_lb60/Makefile b/nand_spl/board/qi/qi_lb60/Makefile
new file mode 100644
index 0000000..fbc5994
--- /dev/null
+++ b/nand_spl/board/qi/qi_lb60/Makefile
@@ -0,0 +1,124 @@
+#
+# (C) Copyright 2006
+# Stefan Roese, DENX Software Engineering, sr at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS	= -Bstatic -T$(LDSCRIPT)
+AFLAGS	+= -DCONFIG_NAND_SPL
+CFLAGS	+= -DCONFIG_NAND_SPL -O2
+
+SOBJS	= start.o
+COBJS	= cpu.o jz4740.o jz_serial.o jz4740_nand.o nand_spl.o nand_boot.o
+
+SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS	:= $(SOBJS) $(COBJS)
+LNDIR	:= $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj	:= $(OBJTREE)/nand_spl/
+
+ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+all:	$(obj).depend $(ALL)
+
+# The JZ4740 CPU can load two areas of data from NAND flash to internal SRAM,
+# one is the normal area up to 8KB starting from NAND flash address 0, the
+# other is the backup area up to 8KB starting from NAND flash address 0x2000.
+
+# After reset, the boot program will first read the normal area data from NAND
+# flash using hardware Reed-Solomon ECC. If no ECC error is detected or ECC
+# error is correctable, the boot program then branches to internal SRAM at 4
+# bytes offset. ff it detects an uncorrectable ECC error, it will continue to
+# read the backup area of data from NAND flash using hardware Reed-Solomon ECC.
+
+# The JZ4740 CPU only support 512B or 2KB nand page. if the NAND is 4KB page
+# it will assume the NAND is 2KB and CPU only read the first 2KB of the page.
+# that means we have to flash the 16K SPL like this:
+# |---2k---.---2k---|  <-- 4KB page
+# #### First  Area ##
+# |--spl1--.--------|
+# |--spl2--.--------|
+# |--spl3--.--------|
+# |--spl4--.--------|
+# #### Second Area ##
+# |--spl1--.--------|
+# |--spl2--.--------|
+# |--spl3--.--------|
+# |--spl4--.--------|
+# which mean we needs at least pad to 32KB data when we using 4KB NAND page.
+
+# those 'dd' commands is for create such two 8KB for JZ4740 CPU and pad to 32KB
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin
+	dd if=$< of=$@ conv=sync bs=8192 count=1
+	dd if=$< of=$@ conv=sync,notrunc oflag=append bs=8192 count=1
+	tr '\0' '\377' < /dev/zero | dd of=$@ conv=sync,notrunc oflag=append \
+		bs=16384 count=1
+
+$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl:	$(OBJS)
+	cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
+		-Map $(nandobj)u-boot-spl.map \
+		-o $(nandobj)u-boot-spl
+
+# create symbolic links for common files
+$(obj)start.S:
+	@rm -f $@
+	ln -s $(SRCTREE)/arch/mips/cpu/xburst/start_spl.S $@
+
+$(obj)cpu.c:
+	@rm -f $@
+	ln -s $(SRCTREE)/arch/mips/cpu/xburst/cpu.c $@
+
+$(obj)jz4740.c:
+	@rm -f $@
+	ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz4740.c $@
+
+$(obj)jz_serial.c:
+	@rm -f $@
+	ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz_serial.c $@
+
+$(obj)jz4740_nand.c:
+	@rm -f $@
+	ln -s $(TOPDIR)/drivers/mtd/nand/jz4740_nand.c $@
+
+$(obj)nand_boot.c:
+	@rm -f $@
+	ln -s $(SRCTREE)/nand_spl/nand_boot.c $@
+
+ifneq ($(OBJTREE), $(SRCTREE))
+$(obj)nand_spl.c:
+	@rm -f $@
+	ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_spl.c $@
+endif
+
+$(obj)%.o:	$(obj)%.S
+	$(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o:	$(obj)%.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/nand_spl/board/qi/qi_lb60/nand_spl.c b/nand_spl/board/qi/qi_lb60/nand_spl.c
new file mode 100644
index 0000000..6a0358a
--- /dev/null
+++ b/nand_spl/board/qi/qi_lb60/nand_spl.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2012 Xiangfu Liu <xiangfu@sharism.cc>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+
+#include <nand.h>
+#include <asm/io.h>
+#include <asm/jz4740.h>
+
+void nand_spl_boot(void)
+{
+	__gpio_as_sdram_16bit_4720();
+	__gpio_as_uart0();
+
+	pll_init();
+	serial_init();
+	sdram_init();
+
+	nand_boot();
+}
diff --git a/nand_spl/board/qi/qi_lb60/u-boot.lds b/nand_spl/board/qi/qi_lb60/u-boot.lds
new file mode 100644
index 0000000..dbb9609
--- /dev/null
+++ b/nand_spl/board/qi/qi_lb60/u-boot.lds
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2005
+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x80000000;
+	.text       :
+	{
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata  : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data  : { *(.data) }
+
+	. = ALIGN(4);
+	.sdata  : { *(.sdata) }
+
+	_gp = ALIGN(16);
+
+	__got_start = .;
+	.got  : { *(.got) }
+	__got_end = .;
+
+	.sdata  : { *(.sdata) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	uboot_end_data = .;
+	num_got_entries = (__got_end - __got_start) >> 2;
+
+	. = ALIGN(4);
+	.sbss  : { *(.sbss) }
+	.bss  : { *(.bss) }
+	uboot_end = .;
+}
+ASSERT(uboot_end <= 0x80008000, "NAND bootstrap too big");
-- 
1.7.5.4

[U-Boot] [PATCH v2] add nand spl boot for qi_lb60 board

[Xiangfu Liu]

Hi Scott

thanks for your comments. PATCH v3 have sent out for you to review.

On 01/07/2012 06:36 AM, Scott Wood wrote:
> We are transitioning from nand_spl/ to spl/.  Please try to work within
> the new infrastructure.  You may run into problems with size in spl/,
> due to gc-sections not removing strings on components you don't need --
> I plan to fix those issues (for NAND), hopefully this merge window, by
> requiring all files to be explicitly asked for.  Feel free to fix them
> first if you'd like. :-)
>

I'd like to move the new spl/. I have one question about the new spl/
I didn't see the new spl/ link to nand_spl/nand_boot.c. so how the new
spl/ using nand_boot()?

can we add a new define 'CONFIG_SPL_START_S_NAME', since qi_lb60 using
start_spl.S for SPL, not start.S.

I think better I make the nand_spl/ working. then move to the new spl/ :)

>> +include $(TOPDIR)/config.mk
>> +
>> +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
>> +LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_NAND_SPL_TEXT_BASE)
>> +AFLAGS	+= -DCONFIG_NAND_SPL
>> +CFLAGS	+= -DCONFIG_NAND_SPL -O2
>
> Why -O2 and not the -Os that you should already be inheriting from
> config.mk?

when I remove the -O2. it give me error:
  jz4740.c:(.text.sdram_init+0x14): undefined reference to `memcpy'
so I keep the -O2 there. please anyone give me some advice on how to fix this.
that will be great.

thanks again
xiangfu

[U-Boot] [PATCH v2] add nand spl boot for qi_lb60 board

[Daniel Schwierzeck]

On Tue, Jan 10, 2012 at 4:13 PM, Xiangfu Liu <xiangfu@openmobilefree.net> wrote:
> Hi Scott
>
> thanks for your comments. PATCH v3 have sent out for you to review.
>
>
> On 01/07/2012 06:36 AM, Scott Wood wrote:
>>
>> We are transitioning from nand_spl/ to spl/. ?Please try to work within
>> the new infrastructure. ?You may run into problems with size in spl/,
>> due to gc-sections not removing strings on components you don't need --
>> I plan to fix those issues (for NAND), hopefully this merge window, by
>> requiring all files to be explicitly asked for. ?Feel free to fix them
>> first if you'd like. :-)
>>
>
> I'd like to move the new spl/. I have one question about the new spl/
> I didn't see the new spl/ link to nand_spl/nand_boot.c. so how the new
> spl/ using nand_boot()?
>
> can we add a new define 'CONFIG_SPL_START_S_NAME', since qi_lb60 using
> start_spl.S for SPL, not start.S.

you could create a spl/ directory under arch/mips/cpu/xburst/ and move
your start_spl.S
to arch/mips/cpu/xburst/spl/start.S.

Then define in your board config:

#define CONFIG_SPL
#define CONFIG_SPL_TEXT_BASE		YOUR_SPL_TEXT_BASE
#define CONFIG_SPL_START_S_PATH	"arch/mips/cpu/xburst/spl"

Add defines CONFIG_SPL_XXX_SUPPORT where XXX is an additional library you
need in your SPL binary. I guees you need at least CONFIG_SPL_NAND_SUPPORT.
Have a look at spl/Makefile or doc/README.SPL for reference.

You should also move your files from nand_spl/board/qi/qi_lb60/ to
board/qi/qi_lb60/ and
rename u-boot.lds to u-boot-spl.lds. The spl Makefile will
automatically use this script.

>
> I think better I make the nand_spl/ working. then move to the new spl/ :)
>
>
>>> +include $(TOPDIR)/config.mk
>>> +
>>> +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
>>> +LDFLAGS ? ? ? ?= -Bstatic -T $(LDSCRIPT) -Ttext
>>> $(CONFIG_NAND_SPL_TEXT_BASE)
>>> +AFLAGS += -DCONFIG_NAND_SPL
>>> +CFLAGS += -DCONFIG_NAND_SPL -O2
>>
>>
>> Why -O2 and not the -Os that you should already be inheriting from
>> config.mk?
>
>
> when I remove the -O2. it give me error:
> ?jz4740.c:(.text.sdram_init+0x14): undefined reference to `memcpy'
> so I keep the -O2 there. please anyone give me some advice on how to fix
> this.
> that will be great.

If you use the SPL framework, memcpy won't be linked if you don't use it
due to gc-sections.

-- 
Best regards,
Daniel

[U-Boot] [PATCH v2] add nand spl boot for qi_lb60 board

[Scott Wood]

On 01/10/2012 09:13 AM, Xiangfu Liu wrote:
> Hi Scott
> 
> thanks for your comments. PATCH v3 have sent out for you to review.
> 
> On 01/07/2012 06:36 AM, Scott Wood wrote:
>> We are transitioning from nand_spl/ to spl/.  Please try to work within
>> the new infrastructure.  You may run into problems with size in spl/,
>> due to gc-sections not removing strings on components you don't need --
>> I plan to fix those issues (for NAND), hopefully this merge window, by
>> requiring all files to be explicitly asked for.  Feel free to fix them
>> first if you'd like. :-)
>>
> 
> I'd like to move the new spl/. I have one question about the new spl/
> I didn't see the new spl/ link to nand_spl/nand_boot.c. so how the new
> spl/ using nand_boot()?

It's been moved to drivers/mtd/nand/nand_spl_simple.c and
drivers/mtd/nand/nand_spl_load.c.

> can we add a new define 'CONFIG_SPL_START_S_NAME', since qi_lb60 using
> start_spl.S for SPL, not start.S.

Heh, that didn't take long:
http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/108574

Or, could we just leave start.o up to the arch Makefile, and just make
sure the arch "library" is linked in first?

> I think better I make the nand_spl/ working. then move to the new spl/ :)
> 
>>> +include $(TOPDIR)/config.mk
>>> +
>>> +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
>>> +LDFLAGS    = -Bstatic -T $(LDSCRIPT) -Ttext
>>> $(CONFIG_NAND_SPL_TEXT_BASE)
>>> +AFLAGS    += -DCONFIG_NAND_SPL
>>> +CFLAGS    += -DCONFIG_NAND_SPL -O2
>>
>> Why -O2 and not the -Os that you should already be inheriting from
>> config.mk?
> 
> when I remove the -O2. it give me error:
>  jz4740.c:(.text.sdram_init+0x14): undefined reference to `memcpy'
> so I keep the -O2 there. please anyone give me some advice on how to fix
> this.
> that will be great.

GCC requires memcpy even in freestanding environments.  Can you fit a
minimal memcpy in, such as what's currently bcopy in lib/string.c?

-Scott

[U-Boot] [PATCH v3] add nand spl boot for qi_lb60 board

[Wolfgang Denk]

Dear Xiangfu Liu,

In message <1326207993-17791-1-git-send-email-xiangfu@openmobilefree.net> you wrote:
> Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net>
> ---
> 
> Changes for v2:
>  -Add CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
>  -Cleanup jz4740_nand.c a little
> 
> Changes for v3:
>  -Remove CONFIG_NAND_SPL_TEXT_BASE, fix the wrong TEXT base under SPL u-boot.lds
>  -Remove overcomplicated 'dd', pad to 32KB SPL instead of 256. comments added in Makefile
>  -Cleanup the qi_lb60.h 
> 
>  arch/mips/cpu/xburst/cpu.c           |    4 +
>  arch/mips/cpu/xburst/start_spl.S     |   65 +++++++++++++
>  drivers/mtd/nand/jz4740_nand.c       |   40 ++++++++-
>  include/configs/qi_lb60.h            |  166 ++++++++++++++++------------------
>  nand_spl/board/qi/qi_lb60/Makefile   |  124 +++++++++++++++++++++++++
>  nand_spl/board/qi/qi_lb60/nand_spl.c |   37 ++++++++
>  nand_spl/board/qi/qi_lb60/u-boot.lds |   62 +++++++++++++
>  7 files changed, 407 insertions(+), 91 deletions(-)
>  create mode 100644 arch/mips/cpu/xburst/start_spl.S
>  create mode 100644 nand_spl/board/qi/qi_lb60/Makefile
>  create mode 100644 nand_spl/board/qi/qi_lb60/nand_spl.c
>  create mode 100644 nand_spl/board/qi/qi_lb60/u-boot.lds

I don't want to see more boards added to the old /nand_spl/
infrastructure.  You said you were converting to /spl/ instead?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Die Scheu vor Verantwortung ist die Krankheit unserer Zeit.
                                                 -- Otto von Bismarck