[U-Boot] [PATCH 1/2 V2] arm926: Flush the data cache before disabling it.

[Albert ARIBAUD <albert.u.boot@aribaud.net>]

Le 12/01/2012 07:29, Sughosh Ganu a ?crit :
> On Thu Jan 12, 2012 at 06:56:01AM +0100, Christian Riesch wrote:
>> On Wednesday, January 11, 2012, Marek Vasut<marek.vasut@gmail.com>  wrote:
>
> <snip>
>
>>>> RBL executes an AIS script. Sughosh, could you please explain what your
>> AIS
>>>> does or how you create it?
>>>
>>> So basically, this SPL business can be avoided and this all can be done
>> in a
>>> standard way?
>>
>> I don't know, I never had to deal with booting from NAND. I was just
>> wondering what Sughosh's AIS is doing that he gets these SPL problems.
>> Christian
>
>    I have checked my ais ini file, and it does the normal pll/ddr
>    settings. I think it is the rbl which might be turning the cache
>    ON.

I do understand it is ROM code so no change can be done to it, but that 
a bootloader pass control to its payload with the cache still enabled 
and, worse yet, dirty, is Bad(tm).

Can the AIS not be augmented with instructions to flush and disable the 
cache?

Note: I do NOT intend to reject the U-Boot patch if the AIS can indeed 
be modified; I am just trying to apply the Postel principe fully, and 
while the patch would make U-Boot be (more) liberal in what it receives 
from the ROM bootloader, I would like the bootloader to be (more) 
conservative in what it gives U-Boot, i.e. give it a clean system with 
as little assumptions to make or constraints to respect.

Amicalement,
-- 
Albert.