From mboxrd@z Thu Jan 1 00:00:00 1970 From: Troy Kisky Date: Mon, 16 Jan 2012 12:51:15 -0700 Subject: [U-Boot] [PATCH 5/5] i.mx6q: mx6qsabrelite: Update the network configuration In-Reply-To: References: <1326456604-25137-1-git-send-email-dirk.behme@de.bosch.com> <1326456604-25137-5-git-send-email-dirk.behme@de.bosch.com> Message-ID: <4F147FB3.3050003@boundarydevices.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 1/16/2012 6:48 AM, Jason Hui wrote: > On Fri, Jan 13, 2012 at 8:10 PM, Dirk Behme wrote: >> From: Troy Kisky >> >> Enable the usage of PHY_MICREL_KSZ9021, force the master mode and >> minimize the tx clock delay. >> >> There is an issue with the gigabit ethernet mode at the SabreLite boards: >> When operating on a Gb LAN, the FEC occasionally receives packets larger >> than the MTU that appear to be caused by concatenation of multiple >> received packets into one. No, the extra length are usually zero bytes. >> The problem was identified on the phy side. The current schematic has the >> center tap pin 9 of the MAG/JAC USB combo to 3.3 filtered supply. Letting >> this pin float solves the problem. >> >> Signed-off-by: Troy Kisky >> CC: Troy Kisky >> CC: Stefano Babic >> CC: Jason Liu Dirk should either signoff or ack >> --- >> Note: This patch depends on the basic SabreLite ethernet patch >> http://patchwork.ozlabs.org/patch/135744/ >> >> board/freescale/mx6qsabrelite/mx6qsabrelite.c | 8 ++++++-- >> include/configs/mx6qsabrelite.h | 1 + >> 2 files changed, 7 insertions(+), 2 deletions(-) >> >> diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c >> index d80165e..7879049 100644 >> --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c >> +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c >> @@ -193,13 +193,17 @@ int board_mmc_init(bd_t *bis) >> >> int fecmxc_mii_postcall(int phy) >> { >> - /* prefer master mode */ >> - miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x0f00); >> + /* force master mode */ >> + miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x1f00); >> >> /* min rx data delay */ >> miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8105); >> miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000); >> >> + /* min tx data delay */ >> + miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8106); >> + miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000); >> + >> /* max rx/tx clock delay, min rx/tx control delay */ >> miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8104); >> miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0xf0f0); >> diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h >> index 840e271..6a29142 100644 >> --- a/include/configs/mx6qsabrelite.h >> +++ b/include/configs/mx6qsabrelite.h >> @@ -66,6 +66,7 @@ >> #define CONFIG_FEC_XCV_TYPE RGMII >> #define CONFIG_ETHPRIME "FEC" >> #define CONFIG_FEC_MXC_PHYADDR 6 >> +#define CONFIG_PHY_MICREL_KSZ9021 > Acked-by: Jason Liu > >> /* allow to overwrite serial and ethaddr */ >> #define CONFIG_ENV_OVERWRITE >> -- >> 1.7.0.4 >>