From mboxrd@z Thu Jan 1 00:00:00 1970 From: Aneesh V Date: Thu, 19 Jan 2012 17:24:45 +0530 Subject: [U-Boot] [PATCH 1/2 V2] arm926: Flush the data cache before disabling it. In-Reply-To: References: <1326133550-6706-1-git-send-email-urwithsughosh@gmail.com> <1326219136-1953-1-git-send-email-urwithsughosh@gmail.com> <20120113082618.GA1557@Hardy> <4F104DD9.2080308@denx.de> <20120113173821.GC4482@Hardy> <20120117064640.GA1547@Hardy> <20120119065332.GA21447@Hardy> <4F17EDBB.5000501@ti.com> Message-ID: <4F180485.7070004@ti.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Thursday 19 January 2012 05:00 PM, Christian Riesch wrote: > Hi Aneesh, > > On Thu, Jan 19, 2012 at 11:17 AM, Aneesh V wrote: >> On Thursday 19 January 2012 12:23 PM, Sughosh Ganu wrote: >>> Tried a few things on my end. >>> * Read the D-cache value in the spl, and confirmed that the data >>> cache is indeed not enabled. >> What is the value of the B bit in CP15 SCR register? I wonder if RBL is >> doing all the IMB operations required after copying the SPL image and >> before executing it. IMB is required for consistency between data and >> instruction sides. > > Only if caches are used, right? Or also without caches? > Tom wrote that RBL does not turn on cache. > Regards, Christian Only D-cache seems to be disabled in this case. I-cache and Write buffer are likely to be enabled. If so, all the IMB operations except the data-cache flushing are still relevant. br, Aneesh