From mboxrd@z Thu Jan 1 00:00:00 1970 From: Aneesh V Date: Fri, 20 Jan 2012 18:36:52 +0530 Subject: [U-Boot] [PATCH 1/2 V2] arm926: Flush the data cache before disabling it. In-Reply-To: References: <1326133550-6706-1-git-send-email-urwithsughosh@gmail.com> <1326219136-1953-1-git-send-email-urwithsughosh@gmail.com> <20120113082618.GA1557@Hardy> <4F104DD9.2080308@denx.de> <20120113173821.GC4482@Hardy> <20120117064640.GA1547@Hardy> <20120119065332.GA21447@Hardy> <4F17EDBB.5000501@ti.com> <4F180485.7070004@ti.com> <4F192B48.5040905@ti.com> <4F195A62.7030207@ti.com> Message-ID: <4F1966EC.4000309@ti.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Christian, On Friday 20 January 2012 06:18 PM, Christian Riesch wrote: > Hi Aneesh, > > On Fri, Jan 20, 2012 at 1:13 PM, Aneesh V wrote: >> On Friday 20 January 2012 02:51 PM, Christian Riesch wrote: >>> On Fri, Jan 20, 2012 at 9:52 AM, Aneesh V wrote: >>>> Sughosh, >>> >>> [...] >>>> >>>> Can you send the value of SCR you found at SPL entry? This will clarify >>>> what's enabled and what's not. >>> >>> I would like to try that on my board as well for comparison. Could you >>> please tell me how this register can be read? In the ARM manuals SCR >>> seems to have several meanings... Thank you! >>> Regards, Christian >> >> If you have a JTAG based debugger that has the capability of displaying >> CP15 registers, look for "CP15 System Control Register". Otherwise you >> will have to read it using an assembly instruction like below: >> >> >> mrc p15, 0, r0, c1, c0, 0 >> >> After this instruction r0 will contain the SCR value. arm926ejs/start.S >> has this instruction at line #367. You can put a breakpoint after this >> and look at r0. > > Thank you! > > I don't have a JTAG debugger so I stored it in a register, pushed it > later to the stack and then read it with md.l from the memory. I tried > it on my custom board (AM1808 SoC, direct boot from NOR flash) and on > both the da850evm (with AM1808 SoC, AIS boot from SPI flash). The > result was the same for both cases, 0x00052078. So DCache and ICache > are disabled after the RBL. > Regards, Christian Hmm.. That's different from the OMAP processors I have seen. At least OMAP4, that I verified again now, leaves the I-cache enabled (0x00C51878) So, Sughosh's problem still remains a mystery:) br, Aneesh