* [U-Boot] [PATCH v6 2/4] ARM: EXYNOS: Add support for Exynos5 based SoCs
2012-01-25 5:19 [U-Boot] [PATCH v6 0/4] Add SMDK5250 board support Chander Kashyap
2012-01-25 5:19 ` [U-Boot] [PATCH v6 1/4] Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macro Chander Kashyap
@ 2012-01-25 5:19 ` Chander Kashyap
2012-01-25 5:19 ` [U-Boot] [PATCH v6 3/4] EXYNOS: Add SMDK5250 board support Chander Kashyap
2012-01-25 5:19 ` [U-Boot] [PATCH v6 4/4] EXYNOS: SMDK5250: Add MMC SPL support Chander Kashyap
3 siblings, 0 replies; 7+ messages in thread
From: Chander Kashyap @ 2012-01-25 5:19 UTC (permalink / raw)
To: u-boot
Samsung's ARM Cortex-A15 based SoCs are known as Exynos5 series of
SoCs. This patch adds the support for Exynos5.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
---
Changes for v2:
- This patch was part of "EXYNOS: Add SMDK5250 board support"
- Now it is seprated as SoC support.
Changes for v3:
- Populated complete exynos5 gpio structures
Changes for v4:
- Added dmc.h and tzpc.h header files
- Renamed EXYNOS5_PHY*_CTRL_BASE to EXYNOS5_DMC_PHY*_BASE
Changes for v5:
- None
Changes for v5:
- None
arch/arm/cpu/armv7/exynos/clock.c | 208 +++++++++++++++++++-
arch/arm/include/asm/arch-exynos/clock.h | 326 ++++++++++++++++++++++++++++++
arch/arm/include/asm/arch-exynos/cpu.h | 35 +++-
arch/arm/include/asm/arch-exynos/dmc.h | 146 +++++++++++++
arch/arm/include/asm/arch-exynos/gpio.h | 99 +++++++++-
arch/arm/include/asm/arch-exynos/tzpc.h | 52 +++++
6 files changed, 854 insertions(+), 12 deletions(-)
create mode 100644 arch/arm/include/asm/arch-exynos/dmc.h
create mode 100644 arch/arm/include/asm/arch-exynos/tzpc.h
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 4d92c53..2f7048b 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -92,6 +92,72 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
return fout;
}
+/* exynos5: return pll clock frequency */
+static unsigned long exynos5_get_pll_clk(int pllreg)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned long r, m, p, s, k = 0, mask, fout;
+ unsigned int freq;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con0);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con0);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con0);
+ k = readl(&clk->epll_con1);
+ break;
+ case VPLL:
+ r = readl(&clk->vpll_con0);
+ k = readl(&clk->vpll_con1);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ /*
+ * APLL_CON: MIDV [25:16]
+ * MPLL_CON: MIDV [25:16]
+ * EPLL_CON: MIDV [24:16]
+ * VPLL_CON: MIDV [24:16]
+ */
+ if (pllreg == APLL || pllreg == MPLL)
+ mask = 0x3ff;
+ else
+ mask = 0x1ff;
+
+ m = (r >> 16) & mask;
+
+ /* PDIV [13:8] */
+ p = (r >> 8) & 0x3f;
+ /* SDIV [2:0] */
+ s = r & 0x7;
+
+ freq = CONFIG_SYS_CLK_FREQ;
+
+ if (pllreg == EPLL) {
+ k = k & 0xffff;
+ /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
+ fout = (m + k / 65536) * (freq / (p * (1 << s)));
+ } else if (pllreg == VPLL) {
+ k = k & 0xfff;
+ /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
+ fout = (m + k / 1024) * (freq / (p * (1 << s)));
+ } else {
+ if (s < 1)
+ s = 1;
+ /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
+ fout = m * (freq / (p * (1 << (s - 1))));
+ }
+
+ return fout;
+}
+
/* exynos4: return ARM clock frequency */
static unsigned long exynos4_get_arm_clk(void)
{
@@ -114,6 +180,28 @@ static unsigned long exynos4_get_arm_clk(void)
return armclk;
}
+/* exynos5: return ARM clock frequency */
+static unsigned long exynos5_get_arm_clk(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned long div;
+ unsigned long armclk;
+ unsigned int arm_ratio;
+ unsigned int arm2_ratio;
+
+ div = readl(&clk->div_cpu0);
+
+ /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
+ arm_ratio = (div >> 0) & 0x7;
+ arm2_ratio = (div >> 28) & 0x7;
+
+ armclk = get_pll_clk(APLL) / (arm_ratio + 1);
+ armclk /= (arm2_ratio + 1);
+
+ return armclk;
+}
+
/* exynos4: return pwm clock frequency */
static unsigned long exynos4_get_pwm_clk(void)
{
@@ -157,6 +245,27 @@ static unsigned long exynos4_get_pwm_clk(void)
return pclk;
}
+/* exynos5: return pwm clock frequency */
+static unsigned long exynos5_get_pwm_clk(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned long pclk, sclk;
+ unsigned int ratio;
+
+ /*
+ * CLK_DIV_PERIC3
+ * PWM_RATIO [3:0]
+ */
+ ratio = readl(&clk->div_peric3);
+ ratio = ratio & 0xf;
+ sclk = get_pll_clk(MPLL);
+
+ pclk = sclk / (ratio + 1);
+
+ return pclk;
+}
+
/* exynos4: return uart clock frequency */
static unsigned long exynos4_get_uart_clk(int dev_index)
{
@@ -204,6 +313,53 @@ static unsigned long exynos4_get_uart_clk(int dev_index)
return uclk;
}
+/* exynos5: return uart clock frequency */
+static unsigned long exynos5_get_uart_clk(int dev_index)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned long uclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ /*
+ * CLK_SRC_PERIC0
+ * UART0_SEL [3:0]
+ * UART1_SEL [7:4]
+ * UART2_SEL [8:11]
+ * UART3_SEL [12:15]
+ * UART4_SEL [16:19]
+ * UART5_SEL [23:20]
+ */
+ sel = readl(&clk->src_peric0);
+ sel = (sel >> (dev_index << 2)) & 0xf;
+
+ if (sel == 0x6)
+ sclk = get_pll_clk(MPLL);
+ else if (sel == 0x7)
+ sclk = get_pll_clk(EPLL);
+ else if (sel == 0x8)
+ sclk = get_pll_clk(VPLL);
+ else
+ return 0;
+
+ /*
+ * CLK_DIV_PERIC0
+ * UART0_RATIO [3:0]
+ * UART1_RATIO [7:4]
+ * UART2_RATIO [8:11]
+ * UART3_RATIO [12:15]
+ * UART4_RATIO [16:19]
+ * UART5_RATIO [23:20]
+ */
+ ratio = readl(&clk->div_peric0);
+ ratio = (ratio >> (dev_index << 2)) & 0xf;
+
+ uclk = sclk / (ratio + 1);
+
+ return uclk;
+}
+
/* exynos4: set the mmc clock */
static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
{
@@ -231,27 +387,69 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
writel(val, addr);
}
+/* exynos5: set the mmc clock */
+static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned int addr;
+ unsigned int val;
+
+ /*
+ * CLK_DIV_FSYS1
+ * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
+ * CLK_DIV_FSYS2
+ * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
+ */
+ if (dev_index < 2) {
+ addr = (unsigned int)&clk->div_fsys1;
+ } else {
+ addr = (unsigned int)&clk->div_fsys2;
+ dev_index -= 2;
+ }
+
+ val = readl(addr);
+ val &= ~(0xff << ((dev_index << 4) + 8));
+ val |= (div & 0xff) << ((dev_index << 4) + 8);
+ writel(val, addr);
+}
+
unsigned long get_pll_clk(int pllreg)
{
- return exynos4_get_pll_clk(pllreg);
+ if (cpu_is_exynos5())
+ return exynos5_get_pll_clk(pllreg);
+ else
+ return exynos4_get_pll_clk(pllreg);
}
unsigned long get_arm_clk(void)
{
- return exynos4_get_arm_clk();
+ if (cpu_is_exynos5())
+ return exynos5_get_arm_clk();
+ else
+ return exynos4_get_arm_clk();
}
unsigned long get_pwm_clk(void)
{
- return exynos4_get_pwm_clk();
+ if (cpu_is_exynos5())
+ return exynos5_get_pwm_clk();
+ else
+ return exynos4_get_pwm_clk();
}
unsigned long get_uart_clk(int dev_index)
{
- return exynos4_get_uart_clk(dev_index);
+ if (cpu_is_exynos5())
+ return exynos5_get_uart_clk(dev_index);
+ else
+ return exynos4_get_uart_clk(dev_index);
}
void set_mmc_clk(int dev_index, unsigned int div)
{
- exynos4_set_mmc_clk(dev_index, div);
+ if (cpu_is_exynos5())
+ exynos5_set_mmc_clk(dev_index, div);
+ else
+ exynos4_set_mmc_clk(dev_index, div);
}
diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h
index 483c911..50da958 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -250,6 +250,332 @@ struct exynos4_clock {
unsigned int div_iem_l2;
unsigned int div_iem_l1;
};
+
+struct exynos5_clock {
+ unsigned int apll_lock;
+ unsigned char res1[0xfc];
+ unsigned int apll_con0;
+ unsigned int apll_con1;
+ unsigned char res2[0xf8];
+ unsigned int src_cpu;
+ unsigned char res3[0x1fc];
+ unsigned int mux_stat_cpu;
+ unsigned char res4[0xfc];
+ unsigned int div_cpu0;
+ unsigned int div_cpu1;
+ unsigned char res5[0xf8];
+ unsigned int div_stat_cpu0;
+ unsigned int div_stat_cpu1;
+ unsigned char res6[0x1f8];
+ unsigned int gate_sclk_cpu;
+ unsigned char res7[0x1fc];
+ unsigned int clkout_cmu_cpu;
+ unsigned int clkout_cmu_cpu_div_stat;
+ unsigned char res8[0x5f8];
+ unsigned int armclk_stopctrl;
+ unsigned int atclk_stopctrl;
+ unsigned char res9[0x8];
+ unsigned int parityfail_status;
+ unsigned int parityfail_clear;
+ unsigned char res10[0x8];
+ unsigned int pwr_ctrl;
+ unsigned int pwr_ctr2;
+ unsigned char res11[0xd8];
+ unsigned int apll_con0_l8;
+ unsigned int apll_con0_l7;
+ unsigned int apll_con0_l6;
+ unsigned int apll_con0_l5;
+ unsigned int apll_con0_l4;
+ unsigned int apll_con0_l3;
+ unsigned int apll_con0_l2;
+ unsigned int apll_con0_l1;
+ unsigned int iem_control;
+ unsigned char res12[0xdc];
+ unsigned int apll_con1_l8;
+ unsigned int apll_con1_l7;
+ unsigned int apll_con1_l6;
+ unsigned int apll_con1_l5;
+ unsigned int apll_con1_l4;
+ unsigned int apll_con1_l3;
+ unsigned int apll_con1_l2;
+ unsigned int apll_con1_l1;
+ unsigned char res13[0xe0];
+ unsigned int div_iem_l8;
+ unsigned int div_iem_l7;
+ unsigned int div_iem_l6;
+ unsigned int div_iem_l5;
+ unsigned int div_iem_l4;
+ unsigned int div_iem_l3;
+ unsigned int div_iem_l2;
+ unsigned int div_iem_l1;
+ unsigned char res14[0x2ce0];
+ unsigned int mpll_lock;
+ unsigned char res15[0xfc];
+ unsigned int mpll_con0;
+ unsigned int mpll_con1;
+ unsigned char res16[0xf8];
+ unsigned int src_core0;
+ unsigned int src_core1;
+ unsigned char res17[0xf8];
+ unsigned int src_mask_core;
+ unsigned char res18[0x100];
+ unsigned int mux_stat_core1;
+ unsigned char res19[0xf8];
+ unsigned int div_core0;
+ unsigned int div_core1;
+ unsigned char res20[0xf8];
+ unsigned int div_stat_core0;
+ unsigned int div_stat_core1;
+ unsigned char res21[0x2f8];
+ unsigned int gate_ip_core;
+ unsigned char res22[0xfc];
+ unsigned int clkout_cmu_core;
+ unsigned int clkout_cmu_core_div_stat;
+ unsigned char res23[0x5f8];
+ unsigned int dcgidx_map0;
+ unsigned int dcgidx_map1;
+ unsigned int dcgidx_map2;
+ unsigned char res24[0x14];
+ unsigned int dcgperf_map0;
+ unsigned int dcgperf_map1;
+ unsigned char res25[0x18];
+ unsigned int dvcidx_map;
+ unsigned char res26[0x1c];
+ unsigned int freq_cpu;
+ unsigned int freq_dpm;
+ unsigned char res27[0x18];
+ unsigned int dvsemclk_en;
+ unsigned int maxperf;
+ unsigned char res28[0x3478];
+ unsigned int div_acp;
+ unsigned char res29[0xfc];
+ unsigned int div_stat_acp;
+ unsigned char res30[0x1fc];
+ unsigned int gate_ip_acp;
+ unsigned char res31[0x1fc];
+ unsigned int clkout_cmu_acp;
+ unsigned int clkout_cmu_acp_div_stat;
+ unsigned char res32[0x38f8];
+ unsigned int div_isp0;
+ unsigned int div_isp1;
+ unsigned int div_isp2;
+ unsigned char res33[0xf4];
+ unsigned int div_stat_isp0;
+ unsigned int div_stat_isp1;
+ unsigned int div_stat_isp2;
+ unsigned char res34[0x3f4];
+ unsigned int gate_ip_isp0;
+ unsigned int gate_ip_isp1;
+ unsigned char res35[0xf8];
+ unsigned int gate_sclk_isp;
+ unsigned char res36[0xc];
+ unsigned int mcuisp_pwr_ctrl;
+ unsigned char res37[0xec];
+ unsigned int clkout_cmu_isp;
+ unsigned int clkout_cmu_isp_div_stat;
+ unsigned char res38[0x3618];
+ unsigned int cpll_lock;
+ unsigned char res39[0xc];
+ unsigned int epll_lock;
+ unsigned char res40[0xc];
+ unsigned int vpll_lock;
+ unsigned char res41[0xdc];
+ unsigned int cpll_con0;
+ unsigned int cpll_con1;
+ unsigned char res42[0x8];
+ unsigned int epll_con0;
+ unsigned int epll_con1;
+ unsigned int epll_con2;
+ unsigned char res43[0x4];
+ unsigned int vpll_con0;
+ unsigned int vpll_con1;
+ unsigned int vpll_con2;
+ unsigned char res44[0xc4];
+ unsigned int src_top0;
+ unsigned int src_top1;
+ unsigned int src_top2;
+ unsigned int src_top3;
+ unsigned int src_gscl;
+ unsigned int src_disp0_0;
+ unsigned int src_disp0_1;
+ unsigned int src_disp1_0;
+ unsigned int src_disp1_1;
+ unsigned char res46[0xc];
+ unsigned int src_mau;
+ unsigned int src_fsys;
+ unsigned char res47[0x8];
+ unsigned int src_peric0;
+ unsigned int src_peric1;
+ unsigned char res48[0x18];
+ unsigned int sclk_src_isp;
+ unsigned char res49[0x9c];
+ unsigned int src_mask_top;
+ unsigned char res50[0xc];
+ unsigned int src_mask_gscl;
+ unsigned int src_mask_disp0_0;
+ unsigned int src_mask_disp0_1;
+ unsigned int src_mask_disp1_0;
+ unsigned int src_mask_disp1_1;
+ unsigned int src_mask_maudio;
+ unsigned char res52[0x8];
+ unsigned int src_mask_fsys;
+ unsigned char res53[0xc];
+ unsigned int src_mask_peric0;
+ unsigned int src_mask_peric1;
+ unsigned char res54[0x18];
+ unsigned int src_mask_isp;
+ unsigned char res55[0x9c];
+ unsigned int mux_stat_top0;
+ unsigned int mux_stat_top1;
+ unsigned int mux_stat_top2;
+ unsigned int mux_stat_top3;
+ unsigned char res56[0xf0];
+ unsigned int div_top0;
+ unsigned int div_top1;
+ unsigned char res57[0x8];
+ unsigned int div_gscl;
+ unsigned int div_disp0_0;
+ unsigned int div_disp0_1;
+ unsigned int div_disp1_0;
+ unsigned int div_disp1_1;
+ unsigned char res59[0x8];
+ unsigned int div_gen;
+ unsigned char res60[0x4];
+ unsigned int div_mau;
+ unsigned int div_fsys0;
+ unsigned int div_fsys1;
+ unsigned int div_fsys2;
+ unsigned int div_fsys3;
+ unsigned int div_peric0;
+ unsigned int div_peric1;
+ unsigned int div_peric2;
+ unsigned int div_peric3;
+ unsigned int div_peric4;
+ unsigned int div_peric5;
+ unsigned char res61[0x10];
+ unsigned int sclk_div_isp;
+ unsigned char res62[0xc];
+ unsigned int div2_ratio0;
+ unsigned int div2_ratio1;
+ unsigned char res63[0x8];
+ unsigned int div4_ratio;
+ unsigned char res64[0x6c];
+ unsigned int div_stat_top0;
+ unsigned int div_stat_top1;
+ unsigned char res65[0x8];
+ unsigned int div_stat_gscl;
+ unsigned int div_stat_disp0_0;
+ unsigned int div_stat_disp0_1;
+ unsigned int div_stat_disp1_0;
+ unsigned int div_stat_disp1_1;
+ unsigned char res67[0x8];
+ unsigned int div_stat_gen;
+ unsigned char res68[0x4];
+ unsigned int div_stat_maudio;
+ unsigned int div_stat_fsys0;
+ unsigned int div_stat_fsys1;
+ unsigned int div_stat_fsys2;
+ unsigned int div_stat_fsys3;
+ unsigned int div_stat_peric0;
+ unsigned int div_stat_peric1;
+ unsigned int div_stat_peric2;
+ unsigned int div_stat_peric3;
+ unsigned int div_stat_peric4;
+ unsigned int div_stat_peric5;
+ unsigned char res69[0x10];
+ unsigned int sclk_div_stat_isp;
+ unsigned char res70[0xc];
+ unsigned int div2_stat0;
+ unsigned int div2_stat1;
+ unsigned char res71[0x8];
+ unsigned int div4_stat;
+ unsigned char res72[0x180];
+ unsigned int gate_top_sclk_disp0;
+ unsigned int gate_top_sclk_disp1;
+ unsigned int gate_top_sclk_gen;
+ unsigned char res74[0xc];
+ unsigned int gate_top_sclk_mau;
+ unsigned int gate_top_sclk_fsys;
+ unsigned char res75[0xc];
+ unsigned int gate_top_sclk_peric;
+ unsigned char res76[0x1c];
+ unsigned int gate_top_sclk_isp;
+ unsigned char res77[0xac];
+ unsigned int gate_ip_gscl;
+ unsigned int gate_ip_disp0;
+ unsigned int gate_ip_disp1;
+ unsigned int gate_ip_mfc;
+ unsigned int gate_ip_g3d;
+ unsigned int gate_ip_gen;
+ unsigned char res79[0xc];
+ unsigned int gate_ip_fsys;
+ unsigned char res80[0x4];
+ unsigned int gate_ip_gps;
+ unsigned int gate_ip_peric;
+ unsigned char res81[0xc];
+ unsigned int gate_ip_peris;
+ unsigned char res82[0x1c];
+ unsigned int gate_block;
+ unsigned char res83[0x7c];
+ unsigned int clkout_cmu_top;
+ unsigned int clkout_cmu_top_div_stat;
+ unsigned char res84[0x37f8];
+ unsigned int src_lex;
+ unsigned char res85[0x2fc];
+ unsigned int div_lex;
+ unsigned char res86[0xfc];
+ unsigned int div_stat_lex;
+ unsigned char res87[0x1fc];
+ unsigned int gate_ip_lex;
+ unsigned char res88[0x1fc];
+ unsigned int clkout_cmu_lex;
+ unsigned int clkout_cmu_lex_div_stat;
+ unsigned char res89[0x3af8];
+ unsigned int div_r0x;
+ unsigned char res90[0xfc];
+ unsigned int div_stat_r0x;
+ unsigned char res91[0x1fc];
+ unsigned int gate_ip_r0x;
+ unsigned char res92[0x1fc];
+ unsigned int clkout_cmu_r0x;
+ unsigned int clkout_cmu_r0x_div_stat;
+ unsigned char res94[0x3af8];
+ unsigned int div_r1x;
+ unsigned char res95[0xfc];
+ unsigned int div_stat_r1x;
+ unsigned char res96[0x1fc];
+ unsigned int gate_ip_r1x;
+ unsigned char res97[0x1fc];
+ unsigned int clkout_cmu_r1x;
+ unsigned int clkout_cmu_r1x_div_stat;
+ unsigned char res98[0x3608];
+ unsigned int bpll_lock;
+ unsigned char res99[0xfc];
+ unsigned int bpll_con0;
+ unsigned int bpll_con1;
+ unsigned char res100[0xe8];
+ unsigned int src_cdrex;
+ unsigned char res101[0x1fc];
+ unsigned int mux_stat_cdrex;
+ unsigned char res102[0xfc];
+ unsigned int div_cdrex;
+ unsigned int div_cdrex2;
+ unsigned char res103[0xf8];
+ unsigned int div_stat_cdrex;
+ unsigned char res104[0x2fc];
+ unsigned int gate_ip_cdrex;
+ unsigned char res105[0xc];
+ unsigned int c2c_monitor;
+ unsigned int dmc_pwr_ctrl;
+ unsigned char res106[0x4];
+ unsigned int drex2_pause;
+ unsigned char res107[0xe0];
+ unsigned int clkout_cmu_cdrex;
+ unsigned int clkout_cmu_cdrex_div_stat;
+ unsigned char res108[0x8];
+ unsigned int lpddr3phy_ctrl;
+ unsigned char res109[0xf5f8];
+};
#endif
#endif
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index 3496616..89f2c2e 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -22,6 +22,8 @@
#ifndef _EXYNOS4_CPU_H
#define _EXYNOS4_CPU_H
+#define DEVICE_NOT_AVAILABLE 0
+
#define EXYNOS4_ADDR_BASE 0x10000000
/* EXYNOS4 */
@@ -46,7 +48,34 @@
#define EXYNOS4_ADC_BASE 0x13910000
#define EXYNOS4_PWMTIMER_BASE 0x139D0000
#define EXYNOS4_MODEM_BASE 0x13A00000
-#define EXYNOS4_USBPHY_CONTROL 0x10020704
+#define EXYNOS4_USBPHY_CONTROL 0x10020704
+
+#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE
+
+/* EXYNOS5 */
+#define EXYNOS5_GPIO_PART4_BASE 0x03860000
+#define EXYNOS5_PRO_ID 0x10000000
+#define EXYNOS5_CLOCK_BASE 0x10010000
+#define EXYNOS5_POWER_BASE 0x10040000
+#define EXYNOS5_SWRESET 0x10040400
+#define EXYNOS5_SYSREG_BASE 0x10050000
+#define EXYNOS5_WATCHDOG_BASE 0x101D0000
+#define EXYNOS5_DMC_PHY0_BASE 0x10C00000
+#define EXYNOS5_DMC_PHY1_BASE 0x10C10000
+#define EXYNOS5_GPIO_PART3_BASE 0x10D10000
+#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000
+#define EXYNOS5_GPIO_PART1_BASE 0x11400000
+#define EXYNOS5_MMC_BASE 0x12200000
+#define EXYNOS5_SROMC_BASE 0x12250000
+#define EXYNOS5_USBOTG_BASE 0x12480000
+#define EXYNOS5_USBPHY_BASE 0x12480000
+#define EXYNOS5_UART_BASE 0x12C00000
+#define EXYNOS5_PWMTIMER_BASE 0x12DD0000
+#define EXYNOS5_GPIO_PART2_BASE 0x13400000
+#define EXYNOS5_FIMD_BASE 0x14400000
+
+#define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE
#ifndef __ASSEMBLY__
#include <asm/io.h>
@@ -83,12 +112,15 @@ static inline int cpu_is_##type(void) \
}
IS_SAMSUNG_TYPE(exynos4, 0xc210)
+IS_SAMSUNG_TYPE(exynos5, 0xc520)
#define SAMSUNG_BASE(device, base) \
static inline unsigned int samsung_get_base_##device(void) \
{ \
if (cpu_is_exynos4()) \
return EXYNOS4_##base; \
+ else if (cpu_is_exynos5()) \
+ return EXYNOS5_##base; \
else \
return 0; \
}
@@ -99,6 +131,7 @@ SAMSUNG_BASE(fimd, FIMD_BASE)
SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
+SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE)
SAMSUNG_BASE(pro_id, PRO_ID)
SAMSUNG_BASE(mmc, MMC_BASE)
SAMSUNG_BASE(modem, MODEM_BASE)
diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h
new file mode 100644
index 0000000..debbe50
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/dmc.h
@@ -0,0 +1,146 @@
+#ifndef __DMC_H__
+#define __DMC_H__
+
+#ifndef __ASSEMBLY__
+struct exynos5_dmc {
+ unsigned int concontrol;
+ unsigned int memcontrol;
+ unsigned int memconfig0;
+ unsigned int memconfig1;
+ unsigned int directcmd;
+ unsigned int prechconfig;
+ unsigned int phycontrol0;
+ unsigned char res1[0xc];
+ unsigned int pwrdnconfig;
+ unsigned int timingpzq;
+ unsigned int timingref;
+ unsigned int timingrow;
+ unsigned int timingdata;
+ unsigned int timingpower;
+ unsigned int phystatus;
+ unsigned char res2[0x4];
+ unsigned int chipstatus_ch0;
+ unsigned int chipstatus_ch1;
+ unsigned char res3[0x4];
+ unsigned int mrstatus;
+ unsigned char res4[0x8];
+ unsigned int qoscontrol0;
+ unsigned char resr5[0x4];
+ unsigned int qoscontrol1;
+ unsigned char res6[0x4];
+ unsigned int qoscontrol2;
+ unsigned char res7[0x4];
+ unsigned int qoscontrol3;
+ unsigned char res8[0x4];
+ unsigned int qoscontrol4;
+ unsigned char res9[0x4];
+ unsigned int qoscontrol5;
+ unsigned char res10[0x4];
+ unsigned int qoscontrol6;
+ unsigned char res11[0x4];
+ unsigned int qoscontrol7;
+ unsigned char res12[0x4];
+ unsigned int qoscontrol8;
+ unsigned char res13[0x4];
+ unsigned int qoscontrol9;
+ unsigned char res14[0x4];
+ unsigned int qoscontrol10;
+ unsigned char res15[0x4];
+ unsigned int qoscontrol11;
+ unsigned char res16[0x4];
+ unsigned int qoscontrol12;
+ unsigned char res17[0x4];
+ unsigned int qoscontrol13;
+ unsigned char res18[0x4];
+ unsigned int qoscontrol14;
+ unsigned char res19[0x4];
+ unsigned int qoscontrol15;
+ unsigned char res20[0x14];
+ unsigned int ivcontrol;
+ unsigned int wrtra_config;
+ unsigned int rdlvl_config;
+ unsigned char res21[0x8];
+ unsigned int brbrsvconfig;
+ unsigned int brbqosconfig;
+ unsigned int membaseconfig0;
+ unsigned int membaseconfig1;
+ unsigned char res22[0xc];
+ unsigned int wrlvl_config;
+ unsigned char res23[0xc];
+ unsigned int perevcontrol;
+ unsigned int perev0config;
+ unsigned int perev1config;
+ unsigned int perev2config;
+ unsigned int perev3config;
+ unsigned char res24[0xdebc];
+ unsigned int pmnc_ppc_a;
+ unsigned char res25[0xc];
+ unsigned int cntens_ppc_a;
+ unsigned char res26[0xc];
+ unsigned int cntenc_ppc_a;
+ unsigned char res27[0xc];
+ unsigned int intens_ppc_a;
+ unsigned char res28[0xc];
+ unsigned int intenc_ppc_a;
+ unsigned char res29[0xc];
+ unsigned int flag_ppc_a;
+ unsigned char res30[0xac];
+ unsigned int ccnt_ppc_a;
+ unsigned char res31[0xc];
+ unsigned int pmcnt0_ppc_a;
+ unsigned char res32[0xc];
+ unsigned int pmcnt1_ppc_a;
+ unsigned char res33[0xc];
+ unsigned int pmcnt2_ppc_a;
+ unsigned char res34[0xc];
+ unsigned int pmcnt3_ppc_a;
+};
+
+struct exynos5_phy_control {
+ unsigned int phy_con0;
+ unsigned int phy_con1;
+ unsigned int phy_con2;
+ unsigned int phy_con3;
+ unsigned int phy_con4;
+ unsigned char res1[4];
+ unsigned int phy_con6;
+ unsigned char res2[4];
+ unsigned int phy_con8;
+ unsigned int phy_con9;
+ unsigned int phy_con10;
+ unsigned char res3[4];
+ unsigned int phy_con12;
+ unsigned int phy_con13;
+ unsigned int phy_con14;
+ unsigned int phy_con15;
+ unsigned int phy_con16;
+ unsigned char res4[4];
+ unsigned int phy_con17;
+ unsigned int phy_con18;
+ unsigned int phy_con19;
+ unsigned int phy_con20;
+ unsigned int phy_con21;
+ unsigned int phy_con22;
+ unsigned int phy_con23;
+ unsigned int phy_con24;
+ unsigned int phy_con25;
+ unsigned int phy_con26;
+ unsigned int phy_con27;
+ unsigned int phy_con28;
+ unsigned int phy_con29;
+ unsigned int phy_con30;
+ unsigned int phy_con31;
+ unsigned int phy_con32;
+ unsigned int phy_con33;
+ unsigned int phy_con34;
+ unsigned int phy_con35;
+ unsigned int phy_con36;
+ unsigned int phy_con37;
+ unsigned int phy_con38;
+ unsigned int phy_con39;
+ unsigned int phy_con40;
+ unsigned int phy_con41;
+ unsigned int phy_con42;
+};
+#endif
+#endif
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index 9863a12..7a9bb90 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -79,6 +79,59 @@ struct exynos4_gpio_part3 {
struct s5p_gpio_bank z;
};
+struct exynos5_gpio_part1 {
+ struct s5p_gpio_bank a0;
+ struct s5p_gpio_bank a1;
+ struct s5p_gpio_bank a2;
+ struct s5p_gpio_bank b0;
+ struct s5p_gpio_bank b1;
+ struct s5p_gpio_bank b2;
+ struct s5p_gpio_bank b3;
+ struct s5p_gpio_bank c0;
+ struct s5p_gpio_bank c1;
+ struct s5p_gpio_bank c2;
+ struct s5p_gpio_bank c3;
+ struct s5p_gpio_bank d0;
+ struct s5p_gpio_bank d1;
+ struct s5p_gpio_bank y0;
+ struct s5p_gpio_bank y1;
+ struct s5p_gpio_bank y2;
+ struct s5p_gpio_bank y3;
+ struct s5p_gpio_bank y4;
+ struct s5p_gpio_bank y5;
+ struct s5p_gpio_bank y6;
+ struct s5p_gpio_bank res1[0x980];
+ struct s5p_gpio_bank x0;
+ struct s5p_gpio_bank x1;
+ struct s5p_gpio_bank x2;
+ struct s5p_gpio_bank x3;
+};
+
+struct exynos5_gpio_part2 {
+ struct s5p_gpio_bank e0;
+ struct s5p_gpio_bank e1;
+ struct s5p_gpio_bank f0;
+ struct s5p_gpio_bank f1;
+ struct s5p_gpio_bank g0;
+ struct s5p_gpio_bank g1;
+ struct s5p_gpio_bank g2;
+ struct s5p_gpio_bank h0;
+ struct s5p_gpio_bank h1;
+};
+
+struct exynos5_gpio_part3 {
+ struct s5p_gpio_bank v0;
+ struct s5p_gpio_bank v1;
+ struct s5p_gpio_bank v2;
+ struct s5p_gpio_bank v3;
+ struct s5p_gpio_bank res1[0x20];
+ struct s5p_gpio_bank v4;
+};
+
+struct exynos5_gpio_part4 {
+ struct s5p_gpio_bank z;
+};
+
/* functions */
void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
@@ -98,21 +151,55 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
- EXYNOS4_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin)
-#define GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \
+#define EXYNOS4_GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
#define exynos4_gpio_part2_get_nr(bank, pin) \
(((((((unsigned int) &(((struct exynos4_gpio_part2 *) \
EXYNOS4_GPIO_PART2_BASE)->bank)) \
- EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin) + GPIO_PART1_MAX)
+ * GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX)
+
+#define exynos5_gpio_part1_get_nr(bank, pin) \
+ ((((((unsigned int) &(((struct exynos5_gpio_part1 *) \
+ EXYNOS5_GPIO_PART1_BASE)->bank)) \
+ - EXYNOS5_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
+ * GPIO_PER_BANK) + pin)
+
+#define EXYNOS5_GPIO_PART1_MAX ((sizeof(struct exynos5_gpio_part1) \
+ / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+
+#define exynos5_gpio_part2_get_nr(bank, pin) \
+ (((((((unsigned int) &(((struct exynos5_gpio_part2 *) \
+ EXYNOS5_GPIO_PART2_BASE)->bank)) \
+ - EXYNOS5_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
+ * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART1_MAX)
+
+#define EXYNOS5_GPIO_PART2_MAX ((sizeof(struct exynos5_gpio_part2) \
+ / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+
+#define exynos5_gpio_part3_get_nr(bank, pin) \
+ (((((((unsigned int) &(((struct exynos5_gpio_part3 *) \
+ EXYNOS5_GPIO_PART3_BASE)->bank)) \
+ - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
+ * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX)
static inline unsigned int s5p_gpio_base(int nr)
{
- if (nr < GPIO_PART1_MAX)
- return EXYNOS4_GPIO_PART1_BASE;
- else
- return EXYNOS4_GPIO_PART2_BASE;
+ if (cpu_is_exynos5()) {
+ if (nr < EXYNOS5_GPIO_PART1_MAX)
+ return EXYNOS5_GPIO_PART1_BASE;
+ else if (nr < EXYNOS5_GPIO_PART2_MAX)
+ return EXYNOS5_GPIO_PART2_BASE;
+ else
+ return EXYNOS5_GPIO_PART3_BASE;
+
+ } else if (cpu_is_exynos4()) {
+ if (nr < EXYNOS4_GPIO_PART1_MAX)
+ return EXYNOS4_GPIO_PART1_BASE;
+ else
+ return EXYNOS4_GPIO_PART2_BASE;
+ }
return 0;
}
diff --git a/arch/arm/include/asm/arch-exynos/tzpc.h b/arch/arm/include/asm/arch-exynos/tzpc.h
new file mode 100644
index 0000000..2c9a07b
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/tzpc.h
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __TZPC_H_
+#define __TZPC_H_
+
+#ifndef __ASSEMBLY__
+struct exynos5_tzpc {
+ unsigned int r0size;
+ char res1[0x7FC];
+ unsigned int decprot0stat;
+ unsigned int decprot0set;
+ unsigned int decprot0clr;
+ unsigned int decprot1stat;
+ unsigned int decprot1set;
+ unsigned int decprot1clr;
+ unsigned int decprot2stat;
+ unsigned int decprot2set;
+ unsigned int decprot2clr;
+ unsigned int decprot3stat;
+ unsigned int decprot3set;
+ unsigned int decprot3clr;
+ char res2[0x7B0];
+ unsigned int periphid0;
+ unsigned int periphid1;
+ unsigned int periphid2;
+ unsigned int periphid3;
+ unsigned int pcellid0;
+ unsigned int pcellid1;
+ unsigned int pcellid2;
+ unsigned int pcellid3;
+};
+#endif
+
+#endif
--
1.7.5.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [U-Boot] [PATCH v6 3/4] EXYNOS: Add SMDK5250 board support
2012-01-25 5:19 [U-Boot] [PATCH v6 0/4] Add SMDK5250 board support Chander Kashyap
2012-01-25 5:19 ` [U-Boot] [PATCH v6 1/4] Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macro Chander Kashyap
2012-01-25 5:19 ` [U-Boot] [PATCH v6 2/4] ARM: EXYNOS: Add support for Exynos5 based SoCs Chander Kashyap
@ 2012-01-25 5:19 ` Chander Kashyap
2012-01-25 6:56 ` Igor Grinberg
2012-01-25 5:19 ` [U-Boot] [PATCH v6 4/4] EXYNOS: SMDK5250: Add MMC SPL support Chander Kashyap
3 siblings, 1 reply; 7+ messages in thread
From: Chander Kashyap @ 2012-01-25 5:19 UTC (permalink / raw)
To: u-boot
SMDK5250 board is based on Samsungs EXYNOS5250 SoC.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
---
Changes for v2:
- This patch is bifurcated into borad support and SoC support
- Fixed typo: s/EEYNOS/EXYNOS
- Squashed patch "SMDK5250: enable device tree support" in this.
Changes for v3:
- None
Changes for v4:
- Converted assembly routines for clock, memory, uart and tzpc
- init to c functions
- Moved uart init to smdk5250.c
Changes for v5:
- Remove initof gpio1
- Fixed gpio configuration for uart
Changes for v6:
- Add gpio1 init in board_uart_init, which was removed in v5
MAINTAINERS | 1 +
board/samsung/smdk5250/Makefile | 51 ++++
board/samsung/smdk5250/clock_init.c | 202 +++++++++++++
board/samsung/smdk5250/dmc_init.c | 508 ++++++++++++++++++++++++++++++++
board/samsung/smdk5250/lowlevel_init.S | 96 ++++++
board/samsung/smdk5250/setup.h | 353 ++++++++++++++++++++++
board/samsung/smdk5250/smdk5250.c | 152 ++++++++++
board/samsung/smdk5250/tzpc_init.c | 48 +++
boards.cfg | 1 +
include/configs/smdk5250.h | 198 +++++++++++++
10 files changed, 1610 insertions(+), 0 deletions(-)
create mode 100644 board/samsung/smdk5250/Makefile
create mode 100644 board/samsung/smdk5250/clock_init.c
create mode 100644 board/samsung/smdk5250/dmc_init.c
create mode 100644 board/samsung/smdk5250/lowlevel_init.S
create mode 100644 board/samsung/smdk5250/setup.h
create mode 100644 board/samsung/smdk5250/smdk5250.c
create mode 100644 board/samsung/smdk5250/tzpc_init.c
create mode 100644 include/configs/smdk5250.h
diff --git a/MAINTAINERS b/MAINTAINERS
index acbd7f1..c03ebb4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -713,6 +713,7 @@ Chander Kashyap <k.chander@samsung.com>
origen ARM ARMV7 (EXYNOS4210 SoC)
SMDKV310 ARM ARMV7 (EXYNOS4210 SoC)
+ SMDK5250 ARM ARMV7 (EXYNOS5250 SoC)
Heungjun Kim <riverful.kim@samsung.com>
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
new file mode 100644
index 0000000..d9c2774
--- /dev/null
+++ b/board/samsung/smdk5250/Makefile
@@ -0,0 +1,51 @@
+#
+# Copyright (C) 2011 Samsung Electronics
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+SOBJS := lowlevel_init.o
+
+COBJS := clock_init.o
+COBJS += dmc_init.o
+COBJS += tzpc_init.o
+COBJS += smdk5250.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+ALL := $(obj).depend $(LIB)
+
+all: $(ALL)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c
new file mode 100644
index 0000000..2b53a47
--- /dev/null
+++ b/board/samsung/smdk5250/clock_init.c
@@ -0,0 +1,202 @@
+/*
+ * Clock setup for SMDK5250 board based on EXYNOS5
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include "setup.h"
+
+void system_clock_init()
+{
+ struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+
+ /*
+ * MUX_APLL_SEL[0]: FINPLL = 0
+ * MUX_CPU_SEL[6]: MOUTAPLL = 0
+ * MUX_HPM_SEL[20]: MOUTAPLL = 0
+ */
+ writel(0x0, &clk->src_cpu);
+
+ /* MUX_MPLL_SEL[8]: FINPLL = 0 */
+ writel(0x0, &clk->src_core1);
+
+ /*
+ * VPLLSRC_SEL[0]: FINPLL = 0
+ * MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: FINPLL = 0
+ */
+ writel(0x0, &clk->src_top2);
+
+ /* MUX_BPLL_SEL[0]: FINPLL = 0*/
+ writel(0x0, &clk->src_cdrex);
+
+ /* MUX_ACLK_* Clock Selection */
+ writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
+
+ /* MUX_ACLK_* Clock Selection */
+ writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
+
+ /* MUX_ACLK_* Clock Selection */
+ writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
+
+ /* MUX_PWI_SEL[19:16]: SCLKMPLL = 6 */
+ writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
+
+ /* MUX_ATCLK_LEX[0]: ACLK_200 = 0*/
+ writel(CLK_SRC_LEX_VAL, &clk->src_lex);
+
+ /* UART [0-5]: SCLKMPLL = 6 */
+ writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
+
+ /* Set Clock Ratios */
+ writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
+
+ /* Set COPY and HPM Ratio */
+ writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
+
+ /* CORED_RATIO, COREP_RATIO */
+ writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
+
+ /* PWI_RATIO[11:8], DVSEM_RATIO[22:16], DPM_RATIO[24:20] */
+ writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
+
+ /* ACLK_*_RATIO */
+ writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
+
+ /* ACLK_*_RATIO */
+ writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
+
+ /* CDREX Ratio */
+ writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
+
+ /* MCLK_EFPHY_RATIO[3:0] */
+ writel(CLK_DIV_CDREX2_VAL, &clk->div_cdrex2);
+
+ /* {PCLK[4:6]|ATCLK[10:8]}_RATIO */
+ writel(CLK_DIV_LEX_VAL, &clk->div_lex);
+
+ /* PCLK_R0X_RATIO[3:0] */
+ writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
+
+ /* PCLK_R1X_RATIO[3:0] */
+ writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
+
+ /* SATA[24]: SCLKMPLL=0, MMC[0-4]: SCLKMPLL = 6 */
+ writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
+
+ /* UART[0-4] */
+ writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
+
+ /* PWM_RATIO[3:0] */
+ writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
+
+ /* SATA_RATIO, USB_DRD_RATIO */
+ writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
+
+ /* MMC[0-1] */
+ writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
+
+ /* MMC[2-3] */
+ writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
+
+ /* MMC[4] */
+ writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
+
+ /* ACLK|PLCK_ACP_RATIO */
+ writel(CLK_DIV_ACP_VAL, &clk->div_acp);
+
+ /* ISPDIV0_RATIO, ISPDIV1_RATIO */
+ writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
+
+ /* MCUISPDIV0_RATIO, MCUISPDIV1_RATIO */
+ writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
+
+ /* MPWMDIV_RATIO */
+ writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
+
+ /* PLL locktime */
+ writel(APLL_LOCK_VAL, &clk->apll_lock);
+
+ writel(MPLL_LOCK_VAL, &clk->mpll_lock);
+
+ writel(BPLL_LOCK_VAL, &clk->bpll_lock);
+
+ writel(CPLL_LOCK_VAL, &clk->cpll_lock);
+
+ writel(EPLL_LOCK_VAL, &clk->epll_lock);
+
+ writel(VPLL_LOCK_VAL, &clk->vpll_lock);
+
+ sdelay(0x10000);
+
+ /* Set APLL */
+ writel(APLL_CON1_VAL, &clk->apll_con1);
+ writel(APLL_CON0_VAL, &clk->apll_con0);
+ sdelay(0x30000);
+
+ /* Set MPLL */
+ writel(MPLL_CON1_VAL, &clk->mpll_con1);
+ writel(MPLL_CON0_VAL, &clk->mpll_con0);
+ sdelay(0x30000);
+ writel(BPLL_CON1_VAL, &clk->bpll_con1);
+ writel(BPLL_CON0_VAL, &clk->bpll_con0);
+ sdelay(0x30000);
+
+ /* Set CPLL */
+ writel(CPLL_CON1_VAL, &clk->cpll_con1);
+ writel(CPLL_CON0_VAL, &clk->cpll_con0);
+ sdelay(0x30000);
+
+ /* Set EPLL */
+ writel(EPLL_CON2_VAL, &clk->epll_con2);
+ writel(EPLL_CON1_VAL, &clk->epll_con1);
+ writel(EPLL_CON0_VAL, &clk->epll_con0);
+ sdelay(0x30000);
+
+ /* Set VPLL */
+ writel(VPLL_CON2_VAL, &clk->vpll_con2);
+ writel(VPLL_CON1_VAL, &clk->vpll_con1);
+ writel(VPLL_CON0_VAL, &clk->vpll_con0);
+ sdelay(0x30000);
+
+ /* Set MPLL */
+ /* After Initiallising th PLL select the sources accordingly */
+ /* MUX_APLL_SEL[0]: MOUTAPLLFOUT = 1 */
+ writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
+
+ /* MUX_MPLL_SEL[8]: MOUTMPLLFOUT = 1 */
+ writel(CLK_SRC_CORE1_VAL, &clk->src_core1);
+
+ /* MUX_BPLL_SEL[0]: FOUTBPLL = 1*/
+ writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex);
+
+ /*
+ * VPLLSRC_SEL[0]: FINPLL = 0
+ * MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: MOUT{CPLL|EPLL|VPLL} = 1
+ * MUX_{MPLL[20]}|{BPLL[24]}_USER_SEL: FOUT{MPLL|BPLL} = 1
+ */
+ writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
+}
diff --git a/board/samsung/smdk5250/dmc_init.c b/board/samsung/smdk5250/dmc_init.c
new file mode 100644
index 0000000..6f92d8a
--- /dev/null
+++ b/board/samsung/smdk5250/dmc_init.c
@@ -0,0 +1,508 @@
+/*
+ * Memory setup for SMDK5250 board based on EXYNOS5
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/dmc.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include "setup.h"
+
+/* APLL : 1GHz */
+/* MCLK_CDREX: MCLK_CDREX_533*/
+/* LPDDR support: LPDDR2 */
+
+void mem_ctrl_asm_init()
+{
+ struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+ struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
+ struct exynos5_dmc *dmc;
+ unsigned int val;
+
+ phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
+ phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
+ dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
+
+ /* Reset PHY Controllor: PHY_RESET[0] */
+ writel(0x0, &clk->lpddr3phy_ctrl);
+
+ sdelay(0x10000);
+
+ /*set Read Latance and Burst Length for PHY0 and PHY1 */
+ val = 0x408;
+ writel(val, &phy0_ctrl->phy_con42);
+ writel(val, &phy1_ctrl->phy_con42);
+
+ /*
+ * ZQ Calibration:
+ * Select Driver Strength,
+ * long calibration for manual calibration
+ */
+ val = 0x0DA40304;
+ writel(val, &phy0_ctrl->phy_con16);
+ writel(val, &phy1_ctrl->phy_con16);
+
+ /* Enable termination */
+ val = 0x0DAC0304;
+ writel(val, &phy0_ctrl->phy_con16);
+ writel(val, &phy1_ctrl->phy_con16);
+
+ /* Start Manual Calibration */
+ val = 0x0DAC0306;
+ writel(val, &phy0_ctrl->phy_con16);
+ writel(val, &phy1_ctrl->phy_con16);
+
+ sdelay(0x10000);
+
+ /* Enable termination */
+ val = 0x0DAC0304;
+ writel(val, &phy0_ctrl->phy_con16);
+ writel(val, &phy1_ctrl->phy_con16);
+
+ /* DDR Mode: LPDDR2 */
+ val = 0x17021240;
+ writel(val, &phy0_ctrl->phy_con0);
+ writel(val, &phy1_ctrl->phy_con0);
+
+ /* DQS, DQ: Signal, for LPDDR2: Always Set */
+ val = 0x00000F0F;
+ writel(val, &phy0_ctrl->phy_con14);
+ writel(val, &phy1_ctrl->phy_con14);
+
+ /* RD_FETCH: 1 */
+ val = 0x1FFF1000;
+ writel(val, &dmc->concontrol);
+ sdelay(0x10000);
+
+ val = 0x0FFF1000;
+ writel(val, &dmc->concontrol);
+ sdelay(0x10000);
+
+ /*
+ * Update DLL Information:
+ * Force DLL Resyncronization
+ */
+ val = 0x00000008;
+ writel(val, &dmc->phycontrol0);
+
+ /* Reset Force DLL Resyncronization */
+ val = 0x00000000;
+ writel(val, &dmc->phycontrol0);
+
+ /*
+ * Dynamic Clock: Always Running
+ * Memory Burst length: 4
+ * Number of chips: 2
+ * Memory Bus width: 32 bit
+ * Memory Type: LPDDR2-S4
+ * Additional Latancy for PLL: 1 Cycle
+ */
+ val = 0x00212500;
+ writel(val, &dmc->memcontrol);
+
+ /*
+ * Memory Configuration Chip 0
+ * Address Mapping: Interleaved
+ * Number of Column address Bits: 10 bits
+ * Number of Rows Address Bits: 14
+ * Number of Banks: 8
+ */
+ val = 0x00001323;
+ writel(val, &dmc->memconfig0);
+
+ /*
+ * Memory Configuration Chip 1
+ * Address Mapping: Interleaved
+ * Number of Column address Bits: 10 bits
+ * Number of Rows Address Bits: 14
+ * Number of Banks: 8
+ */
+ val = 0x00001323;
+ writel(val, &dmc->memconfig1);
+
+ /*
+ * Chip0: AXI
+ * AXI Base Address: 0x40000000
+ * AXI Base Address Mask: 0x780
+ */
+ val = 0x00400780;
+ writel(val, &dmc->membaseconfig0);
+
+ /*
+ * Chip1: AXI
+ * AXI Base Address: 0x80000000
+ * AXI Base Address Mask: 0x780
+ */
+ val = 0x00800780;
+ writel(val, &dmc->membaseconfig1);
+
+ /* Precharge Configuration */
+ val = 0xFF000000;
+ writel(val, &dmc->prechconfig);
+
+ /* Power Down mode Configuration */
+ val = 0xFFFF00FF;
+ writel(val, &dmc->pwrdnconfig);
+
+ /* Periodic Refrese Interval */
+ val = 0x0000005D;
+ writel(val, &dmc->timingref);
+
+ /* MCLK_CDREX_533 */
+ /*
+ * TimingRow, TimingData, TimingPower Setting:
+ * Values as per Memory AC Parameters
+ */
+ val = 0x2336544C;
+ writel(val, &dmc->timingrow);
+
+ val = 0x24202408;
+ writel(val, &dmc->timingdata);
+
+ val = 0x38260235;
+ writel(val, &dmc->timingpower);
+
+ /* Memory Channel Inteleaving Size: 128 Bytes */
+ val = CONFIG_IV_SIZE;
+ writel(val, &dmc->ivcontrol);
+
+ /* Set Offsets to read DQS */
+ val = 0x7F7F7F7F;
+ writel(val, &phy0_ctrl->phy_con4);
+ writel(val, &phy1_ctrl->phy_con4);
+
+ /* Set Offsets to read DQ */
+ val = 0x7F7F7F7F;
+ writel(val, &phy0_ctrl->phy_con6);
+ writel(val, &phy1_ctrl->phy_con6);
+
+ /* Debug Offset */
+ val = 0x0000007F;
+ writel(val, &phy0_ctrl->phy_con10);
+ writel(val, &phy1_ctrl->phy_con10);
+
+ /* Start DLL Locking */
+ val = 0x10107F50;
+ writel(val, &phy0_ctrl->phy_con12);
+ writel(val, &phy1_ctrl->phy_con12);
+
+ sdelay(0x10000);
+
+ /*
+ * Update DLL Information:
+ * Force DLL Resyncronization
+ */
+ val = 0x00000008;
+ writel(val, &dmc->phycontrol0);
+
+ /* Reset DLL Resyncronization */
+ val = 0x00000000;
+ writel(val, &dmc->phycontrol0);
+
+ /*
+ * NOP CMD: Channel 0, Chip 0
+ * Exit from active/precharge power down or deep power down
+ */
+ val = 0x07000000;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ /* EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+ val = 0x00071C00;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ val = 0x00010BFC;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ /* MCLK_CDREX_533 */
+ val = 0x00000708;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ val = 0x00000818;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ /*
+ * NOP CMD: Channel 0, Chip 1
+ * Exit from active/precharge power down or deep power down
+ */
+ val = 0x07100000;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ /* EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+ val = 0x00171C00;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ val = 0x00110BFC;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ /* MCLK_CDREX_533 */
+ val = 0x00100708;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ val = 0x00100818;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ /*
+ * NOP CMD: Channel 1, Chip 0
+ * Exit from active/precharge power down or deep power down
+ */
+ val = 0x17000000;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ /* EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+ val = 0x10071C00;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ val = 0x10010BFC;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ /* MCLK_CDREX_533 */
+ val = 0x10000708;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ val = 0x10000818;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ /*
+ * NOP CMD: Channel 1, Chip 1
+ * Exit from active/precharge power down or deep power down
+ */
+ val = 0x17100000;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ /* EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
+ val = 0x10171C00;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ val = 0x10110BFC;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ /* MCLK_CDREX_533 */
+ val = 0x10100708;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ val = 0x10100818;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ /* Reset DQS Offsets */
+ val = 0x08080808;
+ writel(val, &phy0_ctrl->phy_con4);
+ writel(val, &phy1_ctrl->phy_con4);
+
+ /* Reset DQ Offsets */
+ val = 0x08080808;
+ writel(val, &phy0_ctrl->phy_con6);
+ writel(val, &phy1_ctrl->phy_con6);
+
+ /* Reset debug Offsets */
+ val = 0x00000008;
+ writel(val, &phy0_ctrl->phy_con10);
+ writel(val, &phy1_ctrl->phy_con10);
+
+ /* Set DLL Locking */
+ val = 0x10107F30;
+ writel(val, &phy0_ctrl->phy_con12);
+ writel(val, &phy1_ctrl->phy_con12);
+
+ sdelay(0x10000);
+
+ /* Start DLL Locking */
+ val = 0x10107F70;
+ writel(val, &phy0_ctrl->phy_con12);
+ writel(val, &phy1_ctrl->phy_con12);
+
+ sdelay(0x10000);
+
+ /*
+ * Update DLL Information:
+ * Force DLL Resyncronization
+ */
+ val = 0x00000008;
+ writel(val, &dmc->phycontrol0);
+
+ /* Reset DLL Resyncronization */
+ val = 0x00000000;
+ writel(val, &dmc->phycontrol0);
+
+ sdelay(0x10000);
+
+ /*
+ * Update DLL Information:
+ * Force DLL Resyncronization
+ */
+ val = 0x00000008;
+ writel(val, &dmc->phycontrol0);
+
+ /* Reset DLL Resyncronization */
+ val = 0x00000000;
+ writel(val, &dmc->phycontrol0);
+
+ sdelay(0x10000);
+#if defined(CONFIG_RD_LVL)
+ /* DLL On */
+ val = 0x10102D50;
+ writel(val, &phy0_ctrl->phy_con12);
+ writel(val, &phy1_ctrl->phy_con12);
+
+ /*
+ * Set ctrl_gateadj, ctrl_readadj
+ * ctrl_gateduradj, rdlvl_pass_adj
+ * rdlvl_rddataPadj
+ */
+ val = 0x09210001;
+ writel(val, &phy0_ctrl->phy_con1);
+ writel(val, &phy1_ctrl->phy_con1);
+
+ /* LPDDR2 Address */
+ val = 0x00000208;
+ writel(val, &phy0_ctrl->phy_con22);
+ writel(val, &phy1_ctrl->phy_con22);
+
+ /* Enable Byte Read Leleling */
+ val = 0x17023240;
+ writel(val, &phy0_ctrl->phy_con0);
+ writel(val, &phy1_ctrl->phy_con0);
+
+ /* rdlvl_en: Use levelling offset instead ctrl_shiftc */
+ val = 0x02010004;
+ writel(val, &phy0_ctrl->phy_con2);
+ writel(val, &phy1_ctrl->phy_con2);
+
+ sdelay(0x10000);
+
+ /* Enable Data Eye Trainig */
+ val = 0x00000002;
+ writel(val, &dmc->rdlvl_config);
+
+ sdelay(0x10000);
+
+ /* Disable Data Eye Trainig */
+ val = 0x00000000;
+ writel(val, &dmc->rdlvl_config);
+
+ /* RdDeSkew_clear: Clear */
+ val = 0x02012004;
+ writel(val, &phy0_ctrl->phy_con2);
+ writel(val, &phy1_ctrl->phy_con2);
+
+ /* Start DLL Locking */
+ val = 0x10107F70;
+ writel(val, &phy0_ctrl->phy_con12);
+ writel(val, &phy1_ctrl->phy_con12);
+
+ /* Force DLL Resyncronization */
+ val = 0x00000008;
+ writel(val, &dmc->phycontrol0);
+
+ /* Reset DLL Resyncronization */
+ val = 0x00000000;
+ writel(val, &dmc->phycontrol0);
+
+ sdelay(0x10000);
+
+ /* ctrl_atgate: ctrl_gate_p*, ctrl_read_p* generated by PHY*/
+ val = 0x17023200;
+ writel(val, &phy0_ctrl->phy_con0);
+ writel(val, &phy1_ctrl->phy_con0);
+
+ /* Channel:0, Chip:0, PALL (all banks precharge) CMD */
+ val = 0x01000000;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ /* Channel:0, Chip:1, PALL (all banks precharge) CMD */
+ val = 0x01100000;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ /* Channel:1, Chip:0, PALL (all banks precharge) CMD */
+ val = 0x11000000;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+
+ /* Channel:1, Chip:1, PALL (all banks precharge) CMD */
+ val = 0x11100000;
+ writel(val, &dmc->directcmd);
+
+ sdelay(0x10000);
+#endif
+ /*
+ * Dynamic Clock: Stops During Idle Period
+ * Dynamic Power Down: Enable
+ * Dynamic Self refresh: Enable
+ * Memory Burst length: 4
+ * Number of chips: 2
+ * Memory Bus width: 32 bit
+ * Memory Type: LPDDR2-S4
+ * Additional Latancy for PLL: 1 Cycle
+ */
+ val = 0x00212523;
+ writel(val, &dmc->memcontrol);
+
+ /* Start Auto refresh */
+ val = 0x0FFF10E0;
+ writel(val, &dmc->concontrol);
+}
diff --git a/board/samsung/smdk5250/lowlevel_init.S b/board/samsung/smdk5250/lowlevel_init.S
new file mode 100644
index 0000000..d7a0c2e
--- /dev/null
+++ b/board/samsung/smdk5250/lowlevel_init.S
@@ -0,0 +1,96 @@
+/*
+ * Lowlevel setup for SMDK5250 board based on S5PC520
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+
+_TEXT_BASE:
+ .word CONFIG_SYS_TEXT_BASE
+
+ .globl lowlevel_init
+lowlevel_init:
+
+ /* use iRAM stack in bl2 */
+ ldr sp, =CONFIG_IRAM_STACK
+ stmdb r13!, {ip,lr}
+
+ /* check reset status */
+ ldr r0, =(EXYNOS5_POWER_BASE + INFORM1_OFFSET)
+ ldr r1, [r0]
+
+ /* AFTR wakeup reset */
+ ldr r2, =S5P_CHECK_DIDLE
+ cmp r1, r2
+ beq exit_wakeup
+
+ /* LPA wakeup reset */
+ ldr r2, =S5P_CHECK_LPA
+ cmp r1, r2
+ beq exit_wakeup
+
+ /* Sleep wakeup reset */
+ ldr r2, =S5P_CHECK_SLEEP
+ cmp r1, r2
+ beq wakeup_reset
+
+ /*
+ * If U-boot is already running in RAM, no need to relocate U-Boot.
+ * Memory controller must be configured before relocating U-Boot
+ * in ram.
+ */
+ ldr r0, =0x0ffffff /* r0 <- Mask Bits*/
+ bic r1, pc, r0 /* pc <- current addr of code */
+ /* r1 <- unmasked bits of pc */
+ ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */
+ bic r2, r2, r0 /* r2 <- unmasked bits of r2*/
+ cmp r1, r2 /* compare r1, r2 */
+ beq 1f /* r0 == r1 then skip sdram init */
+
+ /* init system clock */
+ bl system_clock_init
+
+ /* Memory initialize */
+ bl mem_ctrl_asm_init
+
+1:
+ bl tzpc_init
+ ldmia r13!, {ip,pc}
+
+wakeup_reset:
+ bl system_clock_init
+ bl mem_ctrl_asm_init
+ bl tzpc_init
+
+exit_wakeup:
+ /* Load return address and jump to kernel */
+ ldr r0, =(EXYNOS5_POWER_BASE + INFORM0_OFFSET)
+
+ /* r1 = physical address of exynos5_cpu_resume function*/
+ ldr r1, [r0]
+
+ /* Jump to kernel */
+ mov pc, r1
+ nop
+ nop
diff --git a/board/samsung/smdk5250/setup.h b/board/samsung/smdk5250/setup.h
new file mode 100644
index 0000000..2ff7400
--- /dev/null
+++ b/board/samsung/smdk5250/setup.h
@@ -0,0 +1,353 @@
+/*
+ * Machine Specific Values for SMDK5250 board based on S5PC520
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SMDK5250_SETUP_H
+#define _SMDK5250_SETUP_H
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+
+/* GPIO Offsets for UART: GPIO Contol Register */
+#define EXYNOS5_GPIO_A0_CON_OFFSET 0x0
+#define EXYNOS5_GPIO_A1_CON_OFFSET 0x20
+
+/* TZPC : Register Offsets */
+#define TZPC0_BASE 0x10100000
+#define TZPC1_BASE 0x10110000
+#define TZPC2_BASE 0x10120000
+#define TZPC3_BASE 0x10130000
+#define TZPC4_BASE 0x10140000
+#define TZPC5_BASE 0x10150000
+#define TZPC6_BASE 0x10160000
+#define TZPC7_BASE 0x10170000
+#define TZPC8_BASE 0x10180000
+#define TZPC9_BASE 0x10190000
+
+/* CLK_SRC_CPU */
+/* 0 = MOUTAPLL, 1 = SCLKMPLL */
+#define MUX_HPM_SEL 0
+#define MUX_CPU_SEL 0
+#define MUX_APLL_SEL 1
+#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
+ | (MUX_CPU_SEL << 16) \
+ | (MUX_APLL_SEL))
+
+/* CLK_DIV_CPU0 */
+#define ARM2_RATIO 0x0
+#define APLL_RATIO 0x1
+#define PCLK_DBG_RATIO 0x1
+#define ATB_RATIO 0x4
+#define PERIPH_RATIO 0x7
+#define ACP_RATIO 0x7
+#define CPUD_RATIO 0x2
+#define ARM_RATIO 0x0
+#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \
+ | (APLL_RATIO << 24) \
+ | (PCLK_DBG_RATIO << 20) \
+ | (ATB_RATIO << 16) \
+ | (PERIPH_RATIO << 12) \
+ | (ACP_RATIO << 8) \
+ | (CPUD_RATIO << 4) \
+ | (ARM_RATIO))
+
+/* CLK_DIV_CPU1 */
+#define HPM_RATIO 0x4
+#define COPY_RATIO 0x0
+#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \
+ | (COPY_RATIO))
+
+#define APLL_MDIV 0x7D
+#define APLL_PDIV 0x3
+#define APLL_SDIV 0x0
+
+#define MPLL_MDIV 0x64
+#define MPLL_PDIV 0x3
+#define MPLL_SDIV 0x0
+
+#define CPLL_MDIV 0x96
+#define CPLL_PDIV 0x4
+#define CPLL_SDIV 0x0
+
+/* APLL_CON1 */
+#define APLL_CON1_VAL (0x00203800)
+
+/* MPLL_CON1 */
+#define MPLL_CON1_VAL (0x00203800)
+
+/* CPLL_CON1 */
+#define CPLL_CON1_VAL (0x00203800)
+
+#define EPLL_MDIV 0x60
+#define EPLL_PDIV 0x3
+#define EPLL_SDIV 0x3
+
+#define EPLL_CON1_VAL 0x00000000
+#define EPLL_CON2_VAL 0x00000080
+
+#define VPLL_MDIV 0x96
+#define VPLL_PDIV 0x3
+#define VPLL_SDIV 0x2
+
+#define VPLL_CON1_VAL 0x00000000
+#define VPLL_CON2_VAL 0x00000080
+
+#define BPLL_MDIV 0x215
+#define BPLL_PDIV 0xC
+#define BPLL_SDIV 0x1
+
+#define BPLL_CON1_VAL 0x00203800
+
+/* Set PLL */
+#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
+
+#define APLL_CON0_VAL set_pll(APLL_MDIV, APLL_PDIV, APLL_SDIV)
+#define MPLL_CON0_VAL set_pll(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
+#define CPLL_CON0_VAL set_pll(CPLL_MDIV, CPLL_PDIV, CPLL_SDIV)
+#define EPLL_CON0_VAL set_pll(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
+#define VPLL_CON0_VAL set_pll(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
+#define BPLL_CON0_VAL set_pll(BPLL_MDIV, BPLL_PDIV, BPLL_SDIV)
+
+/* CLK_SRC_CORE0 */
+#define CLK_SRC_CORE0_VAL 0x00060000
+
+/* CLK_SRC_CORE1 */
+#define CLK_SRC_CORE1_VAL 0x100
+
+/* CLK_DIV_CORE0 */
+#define CLK_DIV_CORE0_VAL 0x120000
+
+/* CLK_DIV_CORE1 */
+#define CLK_DIV_CORE1_VAL 0x07070700
+
+/* CLK_SRC_CDREX */
+#define CLK_SRC_CDREX_VAL 0x111
+
+/* CLK_DIV_CDREX */
+#define MCLK_CDREX2_RATIO 0x0
+#define ACLK_EFCON_RATIO 0x1
+#define MCLK_DPHY_RATIO 0x0
+#define MCLK_CDREX_RATIO 0x0
+#define ACLK_C2C_200_RATIO 0x1
+#define C2C_CLK_400_RATIO 0x1
+#define PCLK_CDREX_RATIO 0x3
+#define ACLK_CDREX_RATIO 0x1
+#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 20) \
+ | (MCLK_CDREX_RATIO << 16) \
+ | (ACLK_C2C_200_RATIO << 12) \
+ | (C2C_CLK_400_RATIO << 8) \
+ | (PCLK_CDREX_RATIO << 4) \
+ | (ACLK_CDREX_RATIO))
+
+#define MCLK_EFPHY_RATIO 0x4
+#define CLK_DIV_CDREX2_VAL MCLK_EFPHY_RATIO
+
+/* CLK_DIV_ACP */
+#define CLK_DIV_ACP_VAL 0x12
+
+/* CLK_SRC_TOP0 */
+#define MUX_ACLK_300_GSCL_SEL 0x1
+#define MUX_ACLK_300_GSCL_MID_SEL 0x0
+#define MUX_ACLK_400_SEL 0x0
+#define MUX_ACLK_333_SEL 0x0
+#define MUX_ACLK_300_DISP1_SEL 0x1
+#define MUX_ACLK_300_DISP1_MID_SEL 0x0
+#define MUX_ACLK_200_SEL 0x0
+#define MUX_ACLK_166_SEL 0x0
+#define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \
+ | (MUX_ACLK_300_GSCL_MID_SEL << 24) \
+ | (MUX_ACLK_400_SEL << 20) \
+ | (MUX_ACLK_333_SEL << 16) \
+ | (MUX_ACLK_300_DISP1_SEL << 15) \
+ | (MUX_ACLK_300_DISP1_MID_SEL << 14) \
+ | (MUX_ACLK_200_SEL << 12) \
+ | (MUX_ACLK_166_SEL << 8))
+
+/* CLK_SRC_TOP1 */
+#define MUX_ACLK_400_ISP_SEL 0x0
+#define MUX_ACLK_400_IOP_SEL 0x0
+#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0
+#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_ISP_SEL << 24) \
+ |(MUX_ACLK_400_IOP_SEL << 20) \
+ |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16))
+
+/* CLK_SRC_TOP2 */
+#define MUX_BPLL_USER_SEL 0x1
+#define MUX_MPLL_USER_SEL 0x1
+#define MUX_VPLL_SEL 0x0
+#define MUX_EPLL_SEL 0x0
+#define MUX_CPLL_SEL 0x0
+#define VPLLSRC_SEL 0x0
+#define CLK_SRC_TOP2_VAL ((MUX_BPLL_USER_SEL << 24) \
+ | (MUX_MPLL_USER_SEL << 20) \
+ | (MUX_VPLL_SEL << 16) \
+ | (MUX_EPLL_SEL << 12) \
+ | (MUX_CPLL_SEL << 8) \
+ | (VPLLSRC_SEL))
+/* CLK_SRC_TOP3 */
+#define MUX_ACLK_333_SUB_SEL 0x1
+#define MUX_ACLK_400_SUB_SEL 0x1
+#define MUX_ACLK_266_ISP_SUB_SEL 0x1
+#define MUX_ACLK_266_GPS_SUB_SEL 0x1
+#define MUX_ACLK_300_GSCL_SUB_SEL 0x1
+#define MUX_ACLK_266_GSCL_SUB_SEL 0x1
+#define MUX_ACLK_300_DISP1_SUB_SEL 0x1
+#define MUX_ACLK_200_DISP1_SUB_SEL 0x1
+#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \
+ | (MUX_ACLK_400_SUB_SEL << 20) \
+ | (MUX_ACLK_266_ISP_SUB_SEL << 16) \
+ | (MUX_ACLK_266_GPS_SUB_SEL << 12) \
+ | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
+ | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
+ | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
+ | (MUX_ACLK_200_DISP1_SUB_SEL << 4))
+
+/* CLK_DIV_TOP0 */
+#define ACLK_300_RATIO 0x0
+#define ACLK_400_RATIO 0x3
+#define ACLK_333_RATIO 0x2
+#define ACLK_266_RATIO 0x2
+#define ACLK_200_RATIO 0x3
+#define ACLK_166_RATIO 0x5
+#define ACLK_133_RATIO 0x1
+#define ACLK_66_RATIO 0x5
+#define CLK_DIV_TOP0_VAL ((ACLK_300_RATIO << 28) \
+ | (ACLK_400_RATIO << 24) \
+ | (ACLK_333_RATIO << 20) \
+ | (ACLK_266_RATIO << 16) \
+ | (ACLK_200_RATIO << 12) \
+ | (ACLK_166_RATIO << 8) \
+ | (ACLK_133_RATIO << 4) \
+ | (ACLK_66_RATIO))
+
+/* CLK_DIV_TOP1 */
+#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3
+#define ACLK_66_PRE_RATIO 0x1
+#define ACLK_400_ISP_RATIO 0x1
+#define ACLK_400_IOP_RATIO 0x1
+#define ACLK_300_GSCL_RATIO 0x0
+#define ACLK_266_GPS_RATIO 0x7
+
+#define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
+ | (ACLK_66_PRE_RATIO << 24) \
+ | (ACLK_400_ISP_RATIO << 20) \
+ | (ACLK_400_IOP_RATIO << 16) \
+ | (ACLK_300_GSCL_RATIO << 12) \
+ | (ACLK_266_GPS_RATIO << 8))
+
+/* APLL_LOCK */
+#define APLL_LOCK_VAL (0x3E8)
+/* MPLL_LOCK */
+#define MPLL_LOCK_VAL (0x2F1)
+/* CPLL_LOCK */
+#define CPLL_LOCK_VAL (0x3E8)
+/* EPLL_LOCK */
+#define EPLL_LOCK_VAL (0x2321)
+/* VPLL_LOCK */
+#define VPLL_LOCK_VAL (0x2321)
+/* BPLL_LOCK */
+#define BPLL_LOCK_VAL (0x3E8)
+
+/* CLK_SRC_PERIC0 */
+/* SRC_CLOCK = SCLK_MPLL */
+#define PWM_SEL 0
+#define UART4_SEL 6
+#define UART3_SEL 6
+#define UART2_SEL 6
+#define UART1_SEL 6
+#define UART0_SEL 6
+#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \
+ | (UART4_SEL << 16) \
+ | (UART3_SEL << 12) \
+ | (UART2_SEL << 8) \
+ | (UART1_SEL << 4) \
+ | (UART0_SEL << 0))
+
+#define CLK_SRC_FSYS_VAL 0x66666
+#define CLK_DIV_FSYS0_VAL 0x0BB00000
+#define CLK_DIV_FSYS1_VAL 0x000f000f
+#define CLK_DIV_FSYS2_VAL 0x020f020f
+#define CLK_DIV_FSYS3_VAL 0x000f
+
+/* CLK_DIV_PERIC0 */
+#define UART5_RATIO 8
+#define UART4_RATIO 8
+#define UART3_RATIO 8
+#define UART2_RATIO 8
+#define UART1_RATIO 8
+#define UART0_RATIO 8
+#define CLK_DIV_PERIC0_VAL ((UART4_RATIO << 16) \
+ | (UART3_RATIO << 12) \
+ | (UART2_RATIO << 8) \
+ | (UART1_RATIO << 4) \
+ | (UART0_RATIO << 0))
+
+/* CLK_DIV_PERIC3 */
+#define PWM_RATIO 8
+#define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
+
+/* CLK_SRC_LEX */
+#define CLK_SRC_LEX_VAL 0x0
+
+/* CLK_DIV_LEX */
+#define CLK_DIV_LEX_VAL 0x10
+
+/* CLK_DIV_R0X */
+#define CLK_DIV_R0X_VAL 0x10
+
+/* CLK_DIV_L0X */
+#define CLK_DIV_R1X_VAL 0x10
+
+/* SCLK_SRC_ISP */
+#define SCLK_SRC_ISP_VAL 0x600
+/* CLK_DIV_ISP0 */
+#define CLK_DIV_ISP0_VAL 0x31
+
+/* CLK_DIV_ISP1 */
+#define CLK_DIV_ISP1_VAL 0x0
+
+/* CLK_DIV_ISP2 */
+#define CLK_DIV_ISP2_VAL 0x1
+
+#define MPLL_DEC (MPLL_MDIV * MPLL_MDIV / (MPLL_PDIV * 2^(MPLL_SDIV-1)))
+
+/*
+ * TZPC Register Value :
+ * R0SIZE: 0x0 : Size of secured ram
+ */
+#define R0SIZE 0x0
+
+/*
+ * TZPC Decode Protection Register Value :
+ * DECPROTXSET: 0xFF : Set Decode region to non-secure
+ */
+#define DECPROTXSET 0xFF
+
+void sdelay(unsigned long);
+void mem_ctrl_asm_init(void);
+void system_clock_init(void);
+void uart_asm_init(void);
+void tzpc_init(void);
+
+#endif
diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c
new file mode 100644
index 0000000..66d56ab
--- /dev/null
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/sromc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+struct exynos5_gpio_part1 *gpio1;
+
+int board_init(void)
+{
+ gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+
+ gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
+ + get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \
+ PHYS_SDRAM_1_SIZE);
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \
+ PHYS_SDRAM_2_SIZE);
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+ gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \
+ PHYS_SDRAM_3_SIZE);
+ gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+ gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \
+ PHYS_SDRAM_4_SIZE);
+ gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
+ gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5, \
+ PHYS_SDRAM_5_SIZE);
+ gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
+ gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6, \
+ PHYS_SDRAM_6_SIZE);
+ gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
+ gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7, \
+ PHYS_SDRAM_7_SIZE);
+ gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
+ gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8, \
+ PHYS_SDRAM_8_SIZE);
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ printf("\nBoard: SMDK5250\n");
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ int i, err;
+
+ /*
+ * MMC2 SD card GPIO:
+ *
+ * GPC2[0] SD_2_CLK(2)
+ * GPC2[1] SD_2_CMD(2)
+ * GPC2[2] SD_2_CDn
+ * GPC2[3:6] SD_2_DATA[0:3](2)
+ */
+ for (i = 0; i < 7; i++) {
+ /* GPC2[0:6] special function 2 */
+ s5p_gpio_cfg_pin(&gpio1->c2, i, GPIO_FUNC(0x2));
+
+ /* GPK2[0:6] drv 4x */
+ s5p_gpio_set_drv(&gpio1->c2, i, GPIO_DRV_4X);
+
+ /* GPK2[0:1] pull disable */
+ if (i == 0 || i == 1) {
+ s5p_gpio_set_pull(&gpio1->c2, i, GPIO_PULL_NONE);
+ continue;
+ }
+
+ /* GPK2[2:6] pull up */
+ s5p_gpio_set_pull(&gpio1->c2, i, GPIO_PULL_UP);
+ }
+
+ err = s5p_mmc_init(2, 4);
+ return err;
+}
+#endif
+
+static void board_uart_init(void)
+{
+ struct exynos5_gpio_part1 *gpio1 =
+ (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+ int i;
+
+ /* UART0-UART1 GPIOs (part1) : 0x22222222 */
+ for (i = 0; i < 8; i++) {
+ s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE);
+ s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2));
+ }
+
+ /* UART2-UART3 GPIOs (part2) : 0x00222222 */
+ for (i = 0; i < 6; i++) {
+ s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
+ s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC(0x2));
+ }
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+ board_uart_init();
+ return 0;
+}
+#endif
diff --git a/board/samsung/smdk5250/tzpc_init.c b/board/samsung/smdk5250/tzpc_init.c
new file mode 100644
index 0000000..c2ccef3
--- /dev/null
+++ b/board/samsung/smdk5250/tzpc_init.c
@@ -0,0 +1,48 @@
+/*
+ * Lowlevel setup for SMDK5250 board based on S5PC520
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/tzpc.h>
+#include"setup.h"
+
+/* Setting TZPC[TrustZone Protection Controller] */
+void tzpc_init(void)
+{
+ struct exynos5_tzpc *tzpc;
+ unsigned int addr;
+
+ for (addr = TZPC0_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) {
+ tzpc = (struct exynos5_tzpc *)addr;
+
+ if (addr == TZPC0_BASE)
+ writel(R0SIZE, &tzpc->r0size);
+
+ writel(DECPROTXSET, &tzpc->decprot0set);
+ writel(DECPROTXSET, &tzpc->decprot1set);
+
+ if (addr != TZPC9_BASE) {
+ writel(DECPROTXSET, &tzpc->decprot2set);
+ writel(DECPROTXSET, &tzpc->decprot3set);
+ }
+ }
+}
diff --git a/boards.cfg b/boards.cfg
index 4aaa891..c0bac3c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -221,6 +221,7 @@ s5p_goni arm armv7 goni samsung
smdkc100 arm armv7 smdkc100 samsung s5pc1xx
origen arm armv7 origen samsung exynos
s5pc210_universal arm armv7 universal_c210 samsung exynos
+smdk5250 arm armv7 smdk5250 samsung exynos
smdkv310 arm armv7 smdkv310 samsung exynos
trats arm armv7 trats samsung exynos
harmony arm armv7 harmony nvidia tegra2
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
new file mode 100644
index 0000000..194130d
--- /dev/null
+++ b/include/configs/smdk5250.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG SMDK5250 (EXYNOS5250) board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
+#define CONFIG_S5P 1 /* S5P Family */
+#define CONFIG_EXYNOS5 1 /* which is in a Exynos5 Family */
+#define CONFIG_CPU_EXYNOS5250 1 /* which is in a Exynos5250 */
+#define CONFIG_SMDK5250 1 /* which is in a SMDK5250 */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_L2_OFF 1
+#define CONFIG_SYS_DCACHE_OFF 1
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CONFIG_SYS_TEXT_BASE 0x43E00000
+
+/* input clock of PLL: SMDK5250 has 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ 24000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
+#define MACH_TYPE_SMDK5250 3774
+#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250
+
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP 0x00000BAD
+#define S5P_CHECK_DIDLE 0xBAD00000
+#define S5P_CHECK_LPA 0xABAD0000
+
+/* Offset for inform registers */
+#define INFORM0_OFFSET 0x800
+#define INFORM1_OFFSET 0x804
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
+
+/* select serial console configuration */
+#define CONFIG_SERIAL_MULTI 1
+#define CONFIG_SERIAL1 1 /* use SERIAL 1 */
+#define CONFIG_BAUDRATE 115200
+#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
+
+#define TZPC_BASE_OFFSET 0x10000
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_MMC 1
+#define CONFIG_S5P_MMC 1
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* PWM */
+#define CONFIG_PWM 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition*/
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "SMDK5250 # "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define CONFIG_SYS_HZ 1000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* Stack sizes */
+#define CONFIG_STACKSIZE (256 << 10) /* 256KB */
+
+#define CONFIG_NR_DRAM_BANKS 8
+#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
+#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+
+/* (Memory Interleaving Size = 1 << IV_SIZE) */
+#define CONFIG_IV_SIZE 0x07
+#define CONFIG_RD_LVL 1
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH 1
+#undef CONFIG_CMD_IMLS
+#define CONFIG_IDENT_STRING " for SMDK5250"
+
+#define CONFIG_ENV_IS_IN_MMC 1
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_SECURE_BL1_ONLY
+
+/* Secure FW size configuration */
+#ifdef CONFIG_SECURE_BL1_ONLY
+#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
+#else
+#define CONFIG_SEC_FW_SIZE 0
+#endif
+
+/* Configuration of BL1, BL2, ENV Blocks on mmc */
+#define CONFIG_RES_BLOCK_SIZE (512)
+#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
+#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
+
+#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
+#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
+#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
+
+/* U-boot copy size from boot Media to DRAM.*/
+#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
+#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
+#define CONFIG_DOS_PARTITION 1
+
+#define CONFIG_IRAM_STACK 0x02050000
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
+#define MMC_MAX_CHANNEL 5
+
+/* Enable devicetree support */
+#define CONFIG_OF_LIBFDT
+
+#endif /* __CONFIG_H */
--
1.7.5.4
^ permalink raw reply related [flat|nested] 7+ messages in thread