* [U-Boot] [PATCH 0/3] mxc_spi refactoring (for mx6q and mx6qsabrelite)
@ 2012-01-30 19:52 Eric Nelson
2012-01-30 19:52 ` [U-Boot] [PATCH 1/3] mxc_spi: move machine specifics into CPU headers Eric Nelson
` (3 more replies)
0 siblings, 4 replies; 14+ messages in thread
From: Eric Nelson @ 2012-01-30 19:52 UTC (permalink / raw)
To: u-boot
This patch set refactors mxc_spi as described in
http://lists.denx.de/pipermail/u-boot/2010-March/068791.html
and requested in
http://lists.denx.de/pipermail/u-boot/2012-January/116023.html
in order to add support for the MX6Q in general and the mx6qsabrelite
specifically.
Patch 1 simply moves the conditional parts of mxc_spi.c into the
respective CPU-specific imx-regs.h files.
Patch 2 adds general support for SPI to the i.MX6.
Patch 3 adds support to the mx6qsabrelite board
^ permalink raw reply [flat|nested] 14+ messages in thread* [U-Boot] [PATCH 1/3] mxc_spi: move machine specifics into CPU headers 2012-01-30 19:52 [U-Boot] [PATCH 0/3] mxc_spi refactoring (for mx6q and mx6qsabrelite) Eric Nelson @ 2012-01-30 19:52 ` Eric Nelson 2012-01-31 9:15 ` Jason Hui 2012-01-30 19:52 ` [U-Boot] [PATCH 2/3] mx6q: Add support for ECSPI through mxc_spi driver Eric Nelson ` (2 subsequent siblings) 3 siblings, 1 reply; 14+ messages in thread From: Eric Nelson @ 2012-01-30 19:52 UTC (permalink / raw) To: u-boot Move (E)CSPI register declarations into the imx-regs.h files for each supported CPU Introduce two new macros to control conditional setup MXC_CSPI - Used for processors with the Configurable Serial Peripheral Interface (MX3x) MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x) Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Stefano Babic <sbabic@denx.de> --- arch/arm/include/asm/arch-mx31/imx-regs.h | 27 ++++++++ arch/arm/include/asm/arch-mx35/imx-regs.h | 25 ++++++++ arch/arm/include/asm/arch-mx5/imx-regs.h | 30 +++++++++ drivers/spi/mxc_spi.c | 93 ++--------------------------- 4 files changed, 88 insertions(+), 87 deletions(-) diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 798cc74..6454acb 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -901,4 +901,31 @@ struct esdc_regs { #define MXC_EHCI_IPPUE_DOWN (1 << 8) #define MXC_EHCI_IPPUE_UP (1 << 9) +/* + * CSPI register definitions + */ +#define MXC_CSPI +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_SMC (1 << 3) +#define MXC_CSPICTRL_POL (1 << 4) +#define MXC_CSPICTRL_PHA (1 << 5) +#define MXC_CSPICTRL_SSCTL (1 << 6) +#define MXC_CSPICTRL_SSPOL (1 << 7) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) +#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) +#define MXC_CSPICTRL_TC (1 << 8) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPICTRL_MAXBITS 0x1f + +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 4 + +#define MXC_SPI_BASE_ADDRESSES \ + 0x43fa4000, \ + 0x50010000, \ + 0x53f84000, + #endif /* __ASM_ARCH_MX31_IMX_REGS_H */ diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h index df74508..e570ad1 100644 --- a/arch/arm/include/asm/arch-mx35/imx-regs.h +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -179,6 +179,31 @@ #define IPU_CONF_IC_EN (1<<1) #define IPU_CONF_SCI_EN (1<<0) +/* + * CSPI register definitions + */ +#define MXC_CSPI +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_SMC (1 << 3) +#define MXC_CSPICTRL_POL (1 << 4) +#define MXC_CSPICTRL_PHA (1 << 5) +#define MXC_CSPICTRL_SSCTL (1 << 6) +#define MXC_CSPICTRL_SSPOL (1 << 7) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) +#define MXC_CSPICTRL_TC (1 << 7) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPICTRL_MAXBITS 0xfff +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 4 + +#define MXC_SPI_BASE_ADDRESSES \ + 0x43fa4000, \ + 0x50010000, + #define GPIO_PORT_NUM 3 #define GPIO_NUM_PIN 32 diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 0ee88d2..4fa6658 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -223,6 +223,36 @@ #define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3 /* + * CSPI register definitions + */ +#define MXC_ECSPI +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) +#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) +#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) +#define MXC_CSPICTRL_MAXBITS 0xfff +#define MXC_CSPICTRL_TC (1 << 7) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 32 + +/* Bit position inside CTRL register to be associated with SS */ +#define MXC_CSPICTRL_CHAN 18 + +/* Bit position inside CON register to be associated with SS */ +#define MXC_CSPICON_POL 4 +#define MXC_CSPICON_PHA 0 +#define MXC_CSPICON_SSPOL 12 +#define MXC_SPI_BASE_ADDRESSES \ + CSPI1_BASE_ADDR, \ + CSPI2_BASE_ADDR, \ + CSPI3_BASE_ADDR, + +/* * Number of GPIO pins per port */ #define GPIO_NUM_PIN 32 diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 2fa7486..2e15318 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -33,93 +33,12 @@ #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \ "See linux mxc_spi driver from Freescale for details." - -#elif defined(CONFIG_MX31) - -#define MXC_CSPICTRL_EN (1 << 0) -#define MXC_CSPICTRL_MODE (1 << 1) -#define MXC_CSPICTRL_XCH (1 << 2) -#define MXC_CSPICTRL_SMC (1 << 3) -#define MXC_CSPICTRL_POL (1 << 4) -#define MXC_CSPICTRL_PHA (1 << 5) -#define MXC_CSPICTRL_SSCTL (1 << 6) -#define MXC_CSPICTRL_SSPOL (1 << 7) -#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) -#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) -#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) -#define MXC_CSPICTRL_TC (1 << 8) -#define MXC_CSPICTRL_RXOVF (1 << 6) -#define MXC_CSPICTRL_MAXBITS 0x1f - -#define MXC_CSPIPERIOD_32KHZ (1 << 15) -#define MAX_SPI_BYTES 4 - -static unsigned long spi_bases[] = { - 0x43fa4000, - 0x50010000, - 0x53f84000, -}; - -#elif defined(CONFIG_MX51) - -#define MXC_CSPICTRL_EN (1 << 0) -#define MXC_CSPICTRL_MODE (1 << 1) -#define MXC_CSPICTRL_XCH (1 << 2) -#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) -#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) -#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) -#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) -#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) -#define MXC_CSPICTRL_MAXBITS 0xfff -#define MXC_CSPICTRL_TC (1 << 7) -#define MXC_CSPICTRL_RXOVF (1 << 6) - -#define MXC_CSPIPERIOD_32KHZ (1 << 15) -#define MAX_SPI_BYTES 32 - -/* Bit position inside CTRL register to be associated with SS */ -#define MXC_CSPICTRL_CHAN 18 - -/* Bit position inside CON register to be associated with SS */ -#define MXC_CSPICON_POL 4 -#define MXC_CSPICON_PHA 0 -#define MXC_CSPICON_SSPOL 12 - -static unsigned long spi_bases[] = { - CSPI1_BASE_ADDR, - CSPI2_BASE_ADDR, - CSPI3_BASE_ADDR, -}; - -#elif defined(CONFIG_MX35) - -#define MXC_CSPICTRL_EN (1 << 0) -#define MXC_CSPICTRL_MODE (1 << 1) -#define MXC_CSPICTRL_XCH (1 << 2) -#define MXC_CSPICTRL_SMC (1 << 3) -#define MXC_CSPICTRL_POL (1 << 4) -#define MXC_CSPICTRL_PHA (1 << 5) -#define MXC_CSPICTRL_SSCTL (1 << 6) -#define MXC_CSPICTRL_SSPOL (1 << 7) -#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) -#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) -#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) -#define MXC_CSPICTRL_TC (1 << 7) -#define MXC_CSPICTRL_RXOVF (1 << 6) -#define MXC_CSPICTRL_MAXBITS 0xfff - -#define MXC_CSPIPERIOD_32KHZ (1 << 15) -#define MAX_SPI_BYTES 4 +#endif static unsigned long spi_bases[] = { - 0x43fa4000, - 0x50010000, + MXC_SPI_BASE_ADDRESSES }; -#else -#error "Unsupported architecture" -#endif - #define OUT MXC_GPIO_DIRECTION_OUT #define reg_read readl @@ -129,7 +48,7 @@ struct mxc_spi_slave { struct spi_slave slave; unsigned long base; u32 ctrl_reg; -#if defined(CONFIG_MX51) +#if defined(MXC_ECSPI) u32 cfg_reg; #endif int gpio; @@ -167,7 +86,7 @@ u32 get_cspi_div(u32 div) return i; } -#if defined(CONFIG_MX31) || defined(CONFIG_MX35) +#ifdef MXC_CSPI static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, unsigned int max_hz, unsigned int mode) { @@ -204,7 +123,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, } #endif -#if defined(CONFIG_MX51) +#ifdef MXC_ECSPI static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, unsigned int max_hz, unsigned int mode) { @@ -316,7 +235,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, MXC_CSPICTRL_BITCOUNT(bitlen - 1); reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN); -#ifdef CONFIG_MX51 +#ifdef MXC_ECSPI reg_write(®s->cfg, mxcs->cfg_reg); #endif -- 1.7.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH 1/3] mxc_spi: move machine specifics into CPU headers 2012-01-30 19:52 ` [U-Boot] [PATCH 1/3] mxc_spi: move machine specifics into CPU headers Eric Nelson @ 2012-01-31 9:15 ` Jason Hui 0 siblings, 0 replies; 14+ messages in thread From: Jason Hui @ 2012-01-31 9:15 UTC (permalink / raw) To: u-boot Eric On Tue, Jan 31, 2012 at 3:52 AM, Eric Nelson <eric.nelson@boundarydevices.com> wrote: > Move (E)CSPI register declarations into the imx-regs.h files for each supported CPU > > Introduce two new macros to control conditional setup > ? ? MXC_CSPI - Used for processors with the Configurable Serial Peripheral Interface (MX3x) > ? ? MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x) > > Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> > Acked-by: Dirk Behme <dirk.behme@de.bosch.com> > Acked-by: Stefano Babic <sbabic@denx.de> > --- > ?arch/arm/include/asm/arch-mx31/imx-regs.h | ? 27 ++++++++ > ?arch/arm/include/asm/arch-mx35/imx-regs.h | ? 25 ++++++++ > ?arch/arm/include/asm/arch-mx5/imx-regs.h ?| ? 30 +++++++++ > ?drivers/spi/mxc_spi.c ? ? ? ? ? ? ? ? ? ? | ? 93 ++--------------------------- > ?4 files changed, 88 insertions(+), 87 deletions(-) Acked-by: Jason Liu <jason.hui@linaro.org> Tested OK on the i.mx51evk board with SPI-PMIC Tested-by: Jason LIu <jason.hui@linaro.org> > > diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h > index 798cc74..6454acb 100644 > --- a/arch/arm/include/asm/arch-mx31/imx-regs.h > +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h > @@ -901,4 +901,31 @@ struct esdc_regs { > ?#define MXC_EHCI_IPPUE_DOWN ? ? ? ? ? ?(1 << 8) > ?#define MXC_EHCI_IPPUE_UP ? ? ? ? ? ? ?(1 << 9) > > +/* > + * CSPI register definitions > + */ > +#define MXC_CSPI > +#define MXC_CSPICTRL_EN ? ? ? ? ? ? ? ?(1 << 0) > +#define MXC_CSPICTRL_MODE ? ? ?(1 << 1) > +#define MXC_CSPICTRL_XCH ? ? ? (1 << 2) > +#define MXC_CSPICTRL_SMC ? ? ? (1 << 3) > +#define MXC_CSPICTRL_POL ? ? ? (1 << 4) > +#define MXC_CSPICTRL_PHA ? ? ? (1 << 5) > +#define MXC_CSPICTRL_SSCTL ? ? (1 << 6) > +#define MXC_CSPICTRL_SSPOL ? ? (1 << 7) > +#define MXC_CSPICTRL_CHIPSELECT(x) ? ? (((x) & 0x3) << 24) > +#define MXC_CSPICTRL_BITCOUNT(x) ? ? ? (((x) & 0x1f) << 8) > +#define MXC_CSPICTRL_DATARATE(x) ? ? ? (((x) & 0x7) << 16) > +#define MXC_CSPICTRL_TC ? ? ? ? ? ? ? ?(1 << 8) > +#define MXC_CSPICTRL_RXOVF ? ? (1 << 6) > +#define MXC_CSPICTRL_MAXBITS ? 0x1f > + > +#define MXC_CSPIPERIOD_32KHZ ? (1 << 15) > +#define MAX_SPI_BYTES ?4 > + > +#define MXC_SPI_BASE_ADDRESSES \ > + ? ? ? 0x43fa4000, \ > + ? ? ? 0x50010000, \ > + ? ? ? 0x53f84000, > + > ?#endif /* __ASM_ARCH_MX31_IMX_REGS_H */ > diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h > index df74508..e570ad1 100644 > --- a/arch/arm/include/asm/arch-mx35/imx-regs.h > +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h > @@ -179,6 +179,31 @@ > ?#define IPU_CONF_IC_EN ? ? ? ? (1<<1) > ?#define IPU_CONF_SCI_EN ? ? ? ? ? ? ? ?(1<<0) > > +/* > + * CSPI register definitions > + */ > +#define MXC_CSPI > +#define MXC_CSPICTRL_EN ? ? ? ? ? ? ? ?(1 << 0) > +#define MXC_CSPICTRL_MODE ? ? ?(1 << 1) > +#define MXC_CSPICTRL_XCH ? ? ? (1 << 2) > +#define MXC_CSPICTRL_SMC ? ? ? (1 << 3) > +#define MXC_CSPICTRL_POL ? ? ? (1 << 4) > +#define MXC_CSPICTRL_PHA ? ? ? (1 << 5) > +#define MXC_CSPICTRL_SSCTL ? ? (1 << 6) > +#define MXC_CSPICTRL_SSPOL ? ? (1 << 7) > +#define MXC_CSPICTRL_CHIPSELECT(x) ? ? (((x) & 0x3) << 12) > +#define MXC_CSPICTRL_BITCOUNT(x) ? ? ? (((x) & 0xfff) << 20) > +#define MXC_CSPICTRL_DATARATE(x) ? ? ? (((x) & 0x7) << 16) > +#define MXC_CSPICTRL_TC ? ? ? ? ? ? ? ?(1 << 7) > +#define MXC_CSPICTRL_RXOVF ? ? (1 << 6) > +#define MXC_CSPICTRL_MAXBITS ? 0xfff > +#define MXC_CSPIPERIOD_32KHZ ? (1 << 15) > +#define MAX_SPI_BYTES ?4 > + > +#define MXC_SPI_BASE_ADDRESSES \ > + ? ? ? 0x43fa4000, \ > + ? ? ? 0x50010000, > + > ?#define GPIO_PORT_NUM ? ? ? ? ?3 > ?#define GPIO_NUM_PIN ? ? ? ? ? 32 > > diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h > index 0ee88d2..4fa6658 100644 > --- a/arch/arm/include/asm/arch-mx5/imx-regs.h > +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h > @@ -223,6 +223,36 @@ > ?#define CS0_32M_CS1_32M_CS2_32M_CS3_32M ? ? ? ? ? ? ? ?3 > > ?/* > + * CSPI register definitions > + */ > +#define MXC_ECSPI > +#define MXC_CSPICTRL_EN ? ? ? ? ? ? ? ?(1 << 0) > +#define MXC_CSPICTRL_MODE ? ? ?(1 << 1) > +#define MXC_CSPICTRL_XCH ? ? ? (1 << 2) > +#define MXC_CSPICTRL_CHIPSELECT(x) ? ? (((x) & 0x3) << 12) > +#define MXC_CSPICTRL_BITCOUNT(x) ? ? ? (((x) & 0xfff) << 20) > +#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) > +#define MXC_CSPICTRL_POSTDIV(x) ? ? ? ?(((x) & 0xF) << 8) > +#define MXC_CSPICTRL_SELCHAN(x) ? ? ? ?(((x) & 0x3) << 18) > +#define MXC_CSPICTRL_MAXBITS ? 0xfff > +#define MXC_CSPICTRL_TC ? ? ? ? ? ? ? ?(1 << 7) > +#define MXC_CSPICTRL_RXOVF ? ? (1 << 6) > +#define MXC_CSPIPERIOD_32KHZ ? (1 << 15) > +#define MAX_SPI_BYTES ?32 > + > +/* Bit position inside CTRL register to be associated with SS */ > +#define MXC_CSPICTRL_CHAN ? ? ?18 > + > +/* Bit position inside CON register to be associated with SS */ > +#define MXC_CSPICON_POL ? ? ? ? ? ? ? ?4 > +#define MXC_CSPICON_PHA ? ? ? ? ? ? ? ?0 > +#define MXC_CSPICON_SSPOL ? ? ?12 > +#define MXC_SPI_BASE_ADDRESSES \ > + ? ? ? CSPI1_BASE_ADDR, \ > + ? ? ? CSPI2_BASE_ADDR, \ > + ? ? ? CSPI3_BASE_ADDR, > + > +/* > ?* Number of GPIO pins per port > ?*/ > ?#define GPIO_NUM_PIN ? ? ? ? ? ?32 > diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c > index 2fa7486..2e15318 100644 > --- a/drivers/spi/mxc_spi.c > +++ b/drivers/spi/mxc_spi.c > @@ -33,93 +33,12 @@ > > ?#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \ > ?"See linux mxc_spi driver from Freescale for details." > - > -#elif defined(CONFIG_MX31) > - > -#define MXC_CSPICTRL_EN ? ? ? ? ? ? ? ?(1 << 0) > -#define MXC_CSPICTRL_MODE ? ? ?(1 << 1) > -#define MXC_CSPICTRL_XCH ? ? ? (1 << 2) > -#define MXC_CSPICTRL_SMC ? ? ? (1 << 3) > -#define MXC_CSPICTRL_POL ? ? ? (1 << 4) > -#define MXC_CSPICTRL_PHA ? ? ? (1 << 5) > -#define MXC_CSPICTRL_SSCTL ? ? (1 << 6) > -#define MXC_CSPICTRL_SSPOL ? ? (1 << 7) > -#define MXC_CSPICTRL_CHIPSELECT(x) ? ? (((x) & 0x3) << 24) > -#define MXC_CSPICTRL_BITCOUNT(x) ? ? ? (((x) & 0x1f) << 8) > -#define MXC_CSPICTRL_DATARATE(x) ? ? ? (((x) & 0x7) << 16) > -#define MXC_CSPICTRL_TC ? ? ? ? ? ? ? ?(1 << 8) > -#define MXC_CSPICTRL_RXOVF ? ? (1 << 6) > -#define MXC_CSPICTRL_MAXBITS ? 0x1f > - > -#define MXC_CSPIPERIOD_32KHZ ? (1 << 15) > -#define MAX_SPI_BYTES ?4 > - > -static unsigned long spi_bases[] = { > - ? ? ? 0x43fa4000, > - ? ? ? 0x50010000, > - ? ? ? 0x53f84000, > -}; > - > -#elif defined(CONFIG_MX51) > - > -#define MXC_CSPICTRL_EN ? ? ? ? ? ? ? ?(1 << 0) > -#define MXC_CSPICTRL_MODE ? ? ?(1 << 1) > -#define MXC_CSPICTRL_XCH ? ? ? (1 << 2) > -#define MXC_CSPICTRL_CHIPSELECT(x) ? ? (((x) & 0x3) << 12) > -#define MXC_CSPICTRL_BITCOUNT(x) ? ? ? (((x) & 0xfff) << 20) > -#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) > -#define MXC_CSPICTRL_POSTDIV(x) ? ? ? ?(((x) & 0xF) << 8) > -#define MXC_CSPICTRL_SELCHAN(x) ? ? ? ?(((x) & 0x3) << 18) > -#define MXC_CSPICTRL_MAXBITS ? 0xfff > -#define MXC_CSPICTRL_TC ? ? ? ? ? ? ? ?(1 << 7) > -#define MXC_CSPICTRL_RXOVF ? ? (1 << 6) > - > -#define MXC_CSPIPERIOD_32KHZ ? (1 << 15) > -#define MAX_SPI_BYTES ?32 > - > -/* Bit position inside CTRL register to be associated with SS */ > -#define MXC_CSPICTRL_CHAN ? ? ?18 > - > -/* Bit position inside CON register to be associated with SS */ > -#define MXC_CSPICON_POL ? ? ? ? ? ? ? ?4 > -#define MXC_CSPICON_PHA ? ? ? ? ? ? ? ?0 > -#define MXC_CSPICON_SSPOL ? ? ?12 > - > -static unsigned long spi_bases[] = { > - ? ? ? CSPI1_BASE_ADDR, > - ? ? ? CSPI2_BASE_ADDR, > - ? ? ? CSPI3_BASE_ADDR, > -}; > - > -#elif defined(CONFIG_MX35) > - > -#define MXC_CSPICTRL_EN ? ? ? ? ? ? ? ?(1 << 0) > -#define MXC_CSPICTRL_MODE ? ? ?(1 << 1) > -#define MXC_CSPICTRL_XCH ? ? ? (1 << 2) > -#define MXC_CSPICTRL_SMC ? ? ? (1 << 3) > -#define MXC_CSPICTRL_POL ? ? ? (1 << 4) > -#define MXC_CSPICTRL_PHA ? ? ? (1 << 5) > -#define MXC_CSPICTRL_SSCTL ? ? (1 << 6) > -#define MXC_CSPICTRL_SSPOL ? ? (1 << 7) > -#define MXC_CSPICTRL_CHIPSELECT(x) ? ? (((x) & 0x3) << 12) > -#define MXC_CSPICTRL_BITCOUNT(x) ? ? ? (((x) & 0xfff) << 20) > -#define MXC_CSPICTRL_DATARATE(x) ? ? ? (((x) & 0x7) << 16) > -#define MXC_CSPICTRL_TC ? ? ? ? ? ? ? ?(1 << 7) > -#define MXC_CSPICTRL_RXOVF ? ? (1 << 6) > -#define MXC_CSPICTRL_MAXBITS ? 0xfff > - > -#define MXC_CSPIPERIOD_32KHZ ? (1 << 15) > -#define MAX_SPI_BYTES ?4 > +#endif > > ?static unsigned long spi_bases[] = { > - ? ? ? 0x43fa4000, > - ? ? ? 0x50010000, > + ? ? ? MXC_SPI_BASE_ADDRESSES > ?}; > > -#else > -#error "Unsupported architecture" > -#endif > - > ?#define OUT ? ?MXC_GPIO_DIRECTION_OUT > > ?#define reg_read readl > @@ -129,7 +48,7 @@ struct mxc_spi_slave { > ? ? ? ?struct spi_slave slave; > ? ? ? ?unsigned long ? base; > ? ? ? ?u32 ? ? ? ? ? ? ctrl_reg; > -#if defined(CONFIG_MX51) > +#if defined(MXC_ECSPI) > ? ? ? ?u32 ? ? ? ? ? ? cfg_reg; > ?#endif > ? ? ? ?int ? ? ? ? ? ? gpio; > @@ -167,7 +86,7 @@ u32 get_cspi_div(u32 div) > ? ? ? ?return i; > ?} > > -#if defined(CONFIG_MX31) || defined(CONFIG_MX35) > +#ifdef MXC_CSPI > ?static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, > ? ? ? ? ? ? ? ?unsigned int max_hz, unsigned int mode) > ?{ > @@ -204,7 +123,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, > ?} > ?#endif > > -#if defined(CONFIG_MX51) > +#ifdef MXC_ECSPI > ?static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, > ? ? ? ? ? ? ? ?unsigned int max_hz, unsigned int mode) > ?{ > @@ -316,7 +235,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, > ? ? ? ? ? ? ? ?MXC_CSPICTRL_BITCOUNT(bitlen - 1); > > ? ? ? ?reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN); > -#ifdef CONFIG_MX51 > +#ifdef MXC_ECSPI > ? ? ? ?reg_write(®s->cfg, mxcs->cfg_reg); > ?#endif > > -- > 1.7.1 > ^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH 2/3] mx6q: Add support for ECSPI through mxc_spi driver 2012-01-30 19:52 [U-Boot] [PATCH 0/3] mxc_spi refactoring (for mx6q and mx6qsabrelite) Eric Nelson 2012-01-30 19:52 ` [U-Boot] [PATCH 1/3] mxc_spi: move machine specifics into CPU headers Eric Nelson @ 2012-01-30 19:52 ` Eric Nelson 2012-01-31 9:20 ` Jason Hui 2012-01-30 19:52 ` [U-Boot] [PATCH 3/3] mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform Eric Nelson 2012-01-31 6:51 ` [U-Boot] [PATCH 0/3] mxc_spi refactoring (for mx6q and mx6qsabrelite) Jason Liu 3 siblings, 1 reply; 14+ messages in thread From: Eric Nelson @ 2012-01-30 19:52 UTC (permalink / raw) To: u-boot Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Stefano Babic <sbabic@denx.de> --- arch/arm/include/asm/arch-mx6/imx-regs.h | 44 ++++++++++++++++++++++++++++++ 1 files changed, 44 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 5227b44..ec74ff2 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -190,6 +190,50 @@ struct src { u32 gpr10; }; +/* ECSPI registers */ +struct cspi_regs { + u32 rxdata; + u32 txdata; + u32 ctrl; + u32 cfg; + u32 intr; + u32 dma; + u32 stat; + u32 period; +}; + +/* + * CSPI register definitions + */ +#define MXC_ECSPI +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) +#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) +#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) +#define MXC_CSPICTRL_MAXBITS 0xfff +#define MXC_CSPICTRL_TC (1 << 7) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 32 + +/* Bit position inside CTRL register to be associated with SS */ +#define MXC_CSPICTRL_CHAN 18 + +/* Bit position inside CON register to be associated with SS */ +#define MXC_CSPICON_POL 4 +#define MXC_CSPICON_PHA 0 +#define MXC_CSPICON_SSPOL 12 +#define MXC_SPI_BASE_ADDRESSES \ + ECSPI1_BASE_ADDR, \ + ECSPI2_BASE_ADDR, \ + ECSPI3_BASE_ADDR, \ + ECSPI4_BASE_ADDR, \ + ECSPI5_BASE_ADDR + struct iim_regs { u32 ctrl; u32 ctrl_set; -- 1.7.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH 2/3] mx6q: Add support for ECSPI through mxc_spi driver 2012-01-30 19:52 ` [U-Boot] [PATCH 2/3] mx6q: Add support for ECSPI through mxc_spi driver Eric Nelson @ 2012-01-31 9:20 ` Jason Hui 0 siblings, 0 replies; 14+ messages in thread From: Jason Hui @ 2012-01-31 9:20 UTC (permalink / raw) To: u-boot On Tue, Jan 31, 2012 at 3:52 AM, Eric Nelson <eric.nelson@boundarydevices.com> wrote: > Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> > Acked-by: Dirk Behme <dirk.behme@de.bosch.com> > Acked-by: Stefano Babic <sbabic@denx.de> > --- > ?arch/arm/include/asm/arch-mx6/imx-regs.h | ? 44 ++++++++++++++++++++++++++++++ > ?1 files changed, 44 insertions(+), 0 deletions(-) Acked-by: Jason Liu <jason.hui@linaro.org> > > diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h > index 5227b44..ec74ff2 100644 > --- a/arch/arm/include/asm/arch-mx6/imx-regs.h > +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h > @@ -190,6 +190,50 @@ struct src { > ? ? ? ?u32 ? ? gpr10; > ?}; > > +/* ECSPI registers */ > +struct cspi_regs { > + ? ? ? u32 rxdata; > + ? ? ? u32 txdata; > + ? ? ? u32 ctrl; > + ? ? ? u32 cfg; > + ? ? ? u32 intr; > + ? ? ? u32 dma; > + ? ? ? u32 stat; > + ? ? ? u32 period; > +}; > + > +/* > + * CSPI register definitions > + */ > +#define MXC_ECSPI > +#define MXC_CSPICTRL_EN ? ? ? ? ? ? ? ?(1 << 0) > +#define MXC_CSPICTRL_MODE ? ? ?(1 << 1) > +#define MXC_CSPICTRL_XCH ? ? ? (1 << 2) > +#define MXC_CSPICTRL_CHIPSELECT(x) ? ? (((x) & 0x3) << 12) > +#define MXC_CSPICTRL_BITCOUNT(x) ? ? ? (((x) & 0xfff) << 20) > +#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) > +#define MXC_CSPICTRL_POSTDIV(x) ? ? ? ?(((x) & 0xF) << 8) > +#define MXC_CSPICTRL_SELCHAN(x) ? ? ? ?(((x) & 0x3) << 18) > +#define MXC_CSPICTRL_MAXBITS ? 0xfff > +#define MXC_CSPICTRL_TC ? ? ? ? ? ? ? ?(1 << 7) > +#define MXC_CSPICTRL_RXOVF ? ? (1 << 6) > +#define MXC_CSPIPERIOD_32KHZ ? (1 << 15) > +#define MAX_SPI_BYTES ?32 > + > +/* Bit position inside CTRL register to be associated with SS */ > +#define MXC_CSPICTRL_CHAN ? ? ?18 > + > +/* Bit position inside CON register to be associated with SS */ > +#define MXC_CSPICON_POL ? ? ? ? ? ? ? ?4 > +#define MXC_CSPICON_PHA ? ? ? ? ? ? ? ?0 > +#define MXC_CSPICON_SSPOL ? ? ?12 > +#define MXC_SPI_BASE_ADDRESSES \ > + ? ? ? ECSPI1_BASE_ADDR, \ > + ? ? ? ECSPI2_BASE_ADDR, \ > + ? ? ? ECSPI3_BASE_ADDR, \ > + ? ? ? ECSPI4_BASE_ADDR, \ > + ? ? ? ECSPI5_BASE_ADDR > + > ?struct iim_regs { > ? ? ? ?u32 ? ? ctrl; > ? ? ? ?u32 ? ? ctrl_set; > -- > 1.7.1 > ^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH 3/3] mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform 2012-01-30 19:52 [U-Boot] [PATCH 0/3] mxc_spi refactoring (for mx6q and mx6qsabrelite) Eric Nelson 2012-01-30 19:52 ` [U-Boot] [PATCH 1/3] mxc_spi: move machine specifics into CPU headers Eric Nelson 2012-01-30 19:52 ` [U-Boot] [PATCH 2/3] mx6q: Add support for ECSPI through mxc_spi driver Eric Nelson @ 2012-01-30 19:52 ` Eric Nelson 2012-01-31 9:31 ` Jason Hui 2012-01-31 6:51 ` [U-Boot] [PATCH 0/3] mxc_spi refactoring (for mx6q and mx6qsabrelite) Jason Liu 3 siblings, 1 reply; 14+ messages in thread From: Eric Nelson @ 2012-01-30 19:52 UTC (permalink / raw) To: u-boot Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Stefano Babic <sbabic@denx.de> --- board/freescale/mx6qsabrelite/imximage.cfg | 2 +- board/freescale/mx6qsabrelite/mx6qsabrelite.c | 25 +++++++++++++++++++++++++ include/configs/mx6qsabrelite.h | 9 +++++++++ 3 files changed, 35 insertions(+), 1 deletions(-) diff --git a/board/freescale/mx6qsabrelite/imximage.cfg b/board/freescale/mx6qsabrelite/imximage.cfg index 83dee6f..c389427 100644 --- a/board/freescale/mx6qsabrelite/imximage.cfg +++ b/board/freescale/mx6qsabrelite/imximage.cfg @@ -156,7 +156,7 @@ DATA 4 0x021b0404 0x00011006 # set the default clock gate to save power DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC00 +DATA 4 0x020c406c 0x0030FC03 DATA 4 0x020c4070 0x0FFFC000 DATA 4 0x020c4074 0x3FF00000 DATA 4 0x020c4078 0x00FFF300 diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index a53b01f..b4282aa 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -46,6 +46,10 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -193,6 +197,23 @@ int board_mmc_init(bd_t *bis) } #endif +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t ecspi1_pads[] = { + /* SS1 */ + MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), +}; + +void setup_spi(void) +{ + gpio_direction_output(IMX_GPIO_NR(3, 19), 1); + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, + ARRAY_SIZE(ecspi1_pads)); +} +#endif + #define MII_1000BASET_CTRL 0x9 #define MII_EXTENDED_CTRL 0xb #define MII_EXTENDED_DATAW 0xc @@ -239,6 +260,10 @@ int board_eth_init(bd_t *bis) return ret; } +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + return 0; } diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index d650ee3..bcb1a42 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -44,6 +44,15 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_CMD_SF +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SST +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_SPEED 25000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#endif + /* MMC Configs */ #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC -- 1.7.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH 3/3] mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform 2012-01-30 19:52 ` [U-Boot] [PATCH 3/3] mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform Eric Nelson @ 2012-01-31 9:31 ` Jason Hui 2012-01-31 14:16 ` Eric Nelson 0 siblings, 1 reply; 14+ messages in thread From: Jason Hui @ 2012-01-31 9:31 UTC (permalink / raw) To: u-boot Eric, On Tue, Jan 31, 2012 at 3:52 AM, Eric Nelson <eric.nelson@boundarydevices.com> wrote: > Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> > Acked-by: Dirk Behme <dirk.behme@de.bosch.com> > Acked-by: Stefano Babic <sbabic@denx.de> > --- > ?board/freescale/mx6qsabrelite/imximage.cfg ? ?| ? ?2 +- > ?board/freescale/mx6qsabrelite/mx6qsabrelite.c | ? 25 +++++++++++++++++++++++++ > ?include/configs/mx6qsabrelite.h ? ? ? ? ? ? ? | ? ?9 +++++++++ > ?3 files changed, 35 insertions(+), 1 deletions(-) After apply the patch, I have the build errors: ../mx6qsabrelite/mx6qsabrelite.c:211: undefined reference to `IMX_GPIO_NR' So, the patch should depends on others. If one patch set is depend on others, it's better to tell it in the cover letter of your patch set. Thanks. > > diff --git a/board/freescale/mx6qsabrelite/imximage.cfg b/board/freescale/mx6qsabrelite/imximage.cfg > index 83dee6f..c389427 100644 > --- a/board/freescale/mx6qsabrelite/imximage.cfg > +++ b/board/freescale/mx6qsabrelite/imximage.cfg > @@ -156,7 +156,7 @@ DATA 4 0x021b0404 0x00011006 > > ?# set the default clock gate to save power > ?DATA 4 0x020c4068 0x00C03F3F > -DATA 4 0x020c406c 0x0030FC00 > +DATA 4 0x020c406c 0x0030FC03 > ?DATA 4 0x020c4070 0x0FFFC000 > ?DATA 4 0x020c4074 0x3FF00000 > ?DATA 4 0x020c4078 0x00FFF300 > diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c > index a53b01f..b4282aa 100644 > --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c > +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c > @@ -46,6 +46,10 @@ DECLARE_GLOBAL_DATA_PTR; > ? ? ? ?PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED ? | ? ? ? ? ? ? \ > ? ? ? ?PAD_CTL_DSE_40ohm ? | PAD_CTL_HYS) > > +#define SPI_PAD_CTRL (PAD_CTL_HYS | ? ? ? ? ? ? ? ? ? ? ? ? ? ?\ > + ? ? ? PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | ? ? ? ? ? ? \ > + ? ? ? PAD_CTL_DSE_40ohm ? ? | PAD_CTL_SRE_FAST) > + > ?int dram_init(void) > ?{ > ? ? ? ?gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); > @@ -193,6 +197,23 @@ int board_mmc_init(bd_t *bis) > ?} > ?#endif > > +#ifdef CONFIG_MXC_SPI > +iomux_v3_cfg_t ecspi1_pads[] = { > + ? ? ? /* SS1 */ > + ? ? ? MX6Q_PAD_EIM_D19__GPIO_3_19 ? | MUX_PAD_CTRL(SPI_PAD_CTRL), > + ? ? ? MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), > + ? ? ? MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), > + ? ? ? MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), > +}; > + > +void setup_spi(void) > +{ > + ? ? ? gpio_direction_output(IMX_GPIO_NR(3, 19), 1); > + ? ? ? imx_iomux_v3_setup_multiple_pads(ecspi1_pads, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ARRAY_SIZE(ecspi1_pads)); > +} > +#endif > + > ?#define MII_1000BASET_CTRL ? ? ? ? ? ? 0x9 > ?#define MII_EXTENDED_CTRL ? ? ? ? ? ? ?0xb > ?#define MII_EXTENDED_DATAW ? ? ? ? ? ? 0xc > @@ -239,6 +260,10 @@ int board_eth_init(bd_t *bis) > ? ? ? ? ? ? ? ?return ret; > ? ? ? ?} > > +#ifdef CONFIG_MXC_SPI > + ? ? ? setup_spi(); > +#endif > + > ? ? ? ?return 0; > ?} > > diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h > index d650ee3..bcb1a42 100644 > --- a/include/configs/mx6qsabrelite.h > +++ b/include/configs/mx6qsabrelite.h > @@ -44,6 +44,15 @@ > ?#define CONFIG_MXC_UART > ?#define CONFIG_MXC_UART_BASE ? ? ? ? ? UART2_BASE > > +#define CONFIG_CMD_SF > +#ifdef CONFIG_CMD_SF > +#define CONFIG_SPI_FLASH > +#define CONFIG_SPI_FLASH_SST > +#define CONFIG_MXC_SPI > +#define CONFIG_SF_DEFAULT_SPEED 25000000 > +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) > +#endif > + > ?/* MMC Configs */ > ?#define CONFIG_FSL_ESDHC > ?#define CONFIG_FSL_USDHC > -- > 1.7.1 > ^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH 3/3] mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform 2012-01-31 9:31 ` Jason Hui @ 2012-01-31 14:16 ` Eric Nelson 2012-01-31 15:00 ` Stefano Babic 2012-01-31 17:50 ` [U-Boot] MX6q SPI refactoring and related patches Eric Nelson 0 siblings, 2 replies; 14+ messages in thread From: Eric Nelson @ 2012-01-31 14:16 UTC (permalink / raw) To: u-boot On 01/31/2012 02:31 AM, Jason Hui wrote: > Eric, > > On Tue, Jan 31, 2012 at 3:52 AM, Eric Nelson > <eric.nelson@boundarydevices.com> wrote: >> Signed-off-by: Eric Nelson<eric.nelson@boundarydevices.com> >> Acked-by: Dirk Behme<dirk.behme@de.bosch.com> >> Acked-by: Stefano Babic<sbabic@denx.de> >> --- >> board/freescale/mx6qsabrelite/imximage.cfg | 2 +- >> board/freescale/mx6qsabrelite/mx6qsabrelite.c | 25 +++++++++++++++++++++++++ >> include/configs/mx6qsabrelite.h | 9 +++++++++ >> 3 files changed, 35 insertions(+), 1 deletions(-) > > After apply the patch, I have the build errors: > ../mx6qsabrelite/mx6qsabrelite.c:211: undefined reference to `IMX_GPIO_NR' > > So, the patch should depends on others. If one patch set is depend on > others, it's better to tell it > in the cover letter of your patch set. Thanks. > Ouch! It's all about the GPIO numbers... This occurred when I re-based to Stefano's tree and will require another patch to keep the BANK:OFFSET numbering scheme. There's a patch lingering in Dirk's tree that defines IMX_GPIO_NR() in gpio.h. See http://lists.denx.de/pipermail/u-boot/2012-January/116866.html for details. I was hoping to get some feedback before generating a patch and revising this patch (and removing GPIO_3_19 macro): http://lists.denx.de/pipermail/u-boot/2012-January/116874.html That said, I'll revise and re-send along with a patch adding support for: GPIO_NUMBER(port,index) GPIO_PORT(number) GPIO_INDEX(number) ^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH 3/3] mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform 2012-01-31 14:16 ` Eric Nelson @ 2012-01-31 15:00 ` Stefano Babic 2012-01-31 17:50 ` [U-Boot] MX6q SPI refactoring and related patches Eric Nelson 1 sibling, 0 replies; 14+ messages in thread From: Stefano Babic @ 2012-01-31 15:00 UTC (permalink / raw) To: u-boot On 31/01/2012 15:16, Eric Nelson wrote: > On 01/31/2012 02:31 AM, Jason Hui wrote: >> Eric, >> Hi Eric, > Ouch! It's all about the GPIO numbers... > > This occurred when I re-based to Stefano's tree and will require > another patch to keep the BANK:OFFSET numbering scheme. There's a > patch lingering in Dirk's tree that defines IMX_GPIO_NR() in gpio.h. > > See http://lists.denx.de/pipermail/u-boot/2012-January/116866.html > for details. Extending the thread you report: the only macro defined in MX I can find is for MX27: #define MXC_GPIO_PORT_TO_NUM(port, bit) (((port - 1) << 5) + (bit & 0x1f)) but we do not need to stick with it ;-). Using a more general GPIO_ as you proposed is better because we could extend the same macros to other family. > > I was hoping to get some feedback before generating a patch and > revising this patch (and removing GPIO_3_19 macro): > > http://lists.denx.de/pipermail/u-boot/2012-January/116874.html > > That said, I'll revise and re-send along with a patch adding > support for: > GPIO_NUMBER(port,index) > GPIO_PORT(number) > GPIO_INDEX(number) Agree with your proposal, good idea ! Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] MX6q SPI refactoring and related patches 2012-01-31 14:16 ` Eric Nelson 2012-01-31 15:00 ` Stefano Babic @ 2012-01-31 17:50 ` Eric Nelson 1 sibling, 0 replies; 14+ messages in thread From: Eric Nelson @ 2012-01-31 17:50 UTC (permalink / raw) To: u-boot I'm about to send an updated set of patches for mxc_spi re-factoring and the related cleanup stemming from the discussions in http://lists.denx.de/pipermail/u-boot/2012-January/116816.html These are split into multiple patch sets as suggested by Dirk: http://lists.denx.de/pipermail/u-boot/2012-January/116865.html Because these are all re-sends, I'm tagging them as "V6" as requested by Jason: http://lists.denx.de/pipermail/u-boot/2012-January/116894.html I'm also including a "PART #" to make it clear which patches are grouped together. -- Part 1 will contain basic support for translating between ordinal GPIO numbers and port:index forms. It is required for parts 2, 4, and 5 -- Part 2 (3 patches) re-factors mxc_spi by moving register declarations into their arch-specific headers. This changed from the previous submission by using GPIO_NUMBER() instead of the undefined IMX_GPIO_NR(). http://lists.denx.de/pipermail/u-boot/2012-January/116901.html -- Part 3 (2 patches) allows a board to define default values for SPI ROM bus and chip-selects and add some documentation for the same. I believe these have already been approved by Mike Frysinger. -- Part 4 defines defaults for the mx6qsabrelite board. Note that this is slightly different from previous submission by also changing a reference to GPIO_NUMBER(3,19) to use the new default value (CONFIG_SF_DEFAULT_CS). -- Part 5 conditionally defines a configuration for use in booting and saving environment to SPI flash instead of SD card to make it easier to switch between them. ^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH 0/3] mxc_spi refactoring (for mx6q and mx6qsabrelite) 2012-01-30 19:52 [U-Boot] [PATCH 0/3] mxc_spi refactoring (for mx6q and mx6qsabrelite) Eric Nelson ` (2 preceding siblings ...) 2012-01-30 19:52 ` [U-Boot] [PATCH 3/3] mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform Eric Nelson @ 2012-01-31 6:51 ` Jason Liu 2012-01-31 6:59 ` Jason Hui 2012-01-31 13:39 ` Eric Nelson 3 siblings, 2 replies; 14+ messages in thread From: Jason Liu @ 2012-01-31 6:51 UTC (permalink / raw) To: u-boot Eric, 2012/1/31 Eric Nelson <eric.nelson@boundarydevices.com>: > This patch set refactors mxc_spi as described in > ? ?http://lists.denx.de/pipermail/u-boot/2010-March/068791.html > and requested in > ? ?http://lists.denx.de/pipermail/u-boot/2012-January/116023.html > in order to add support for the MX6Q in general and the mx6qsabrelite > specifically. If this patch-set is re-send, please specify version Vx and change-log. Thanks, > > Patch 1 simply moves the conditional parts of mxc_spi.c into the > respective CPU-specific imx-regs.h files. > > Patch 2 adds general support for SPI to the i.MX6. I can't find the patch 2/3 in my email system, miss it? > > Patch 3 adds support to the mx6qsabrelite board > > _______________________________________________ > U-Boot mailing list > U-Boot at lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot ^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH 0/3] mxc_spi refactoring (for mx6q and mx6qsabrelite) 2012-01-31 6:51 ` [U-Boot] [PATCH 0/3] mxc_spi refactoring (for mx6q and mx6qsabrelite) Jason Liu @ 2012-01-31 6:59 ` Jason Hui 2012-01-31 13:39 ` Eric Nelson 1 sibling, 0 replies; 14+ messages in thread From: Jason Hui @ 2012-01-31 6:59 UTC (permalink / raw) To: u-boot On Tue, Jan 31, 2012 at 2:51 PM, Jason Liu <liu.h.jason@gmail.com> wrote: > Eric, > > 2012/1/31 Eric Nelson <eric.nelson@boundarydevices.com>: >> This patch set refactors mxc_spi as described in >> ? ?http://lists.denx.de/pipermail/u-boot/2010-March/068791.html >> and requested in >> ? ?http://lists.denx.de/pipermail/u-boot/2012-January/116023.html >> in order to add support for the MX6Q in general and the mx6qsabrelite >> specifically. > > If this patch-set is re-send, please specify version Vx and change-log. Thanks, > >> >> Patch 1 simply moves the conditional parts of mxc_spi.c into the >> respective CPU-specific imx-regs.h files. >> >> Patch 2 adds general support for SPI to the i.MX6. > > I can't find the patch 2/3 in my email system, miss it? sorry, Ignore it. The email system get messed. > >> >> Patch 3 adds support to the mx6qsabrelite board >> >> _______________________________________________ >> U-Boot mailing list >> U-Boot at lists.denx.de >> http://lists.denx.de/mailman/listinfo/u-boot ^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH 0/3] mxc_spi refactoring (for mx6q and mx6qsabrelite) 2012-01-31 6:51 ` [U-Boot] [PATCH 0/3] mxc_spi refactoring (for mx6q and mx6qsabrelite) Jason Liu 2012-01-31 6:59 ` Jason Hui @ 2012-01-31 13:39 ` Eric Nelson 2012-02-01 4:49 ` Jason Hui 1 sibling, 1 reply; 14+ messages in thread From: Eric Nelson @ 2012-01-31 13:39 UTC (permalink / raw) To: u-boot On 01/30/2012 11:51 PM, Jason Liu wrote: > Eric, > > 2012/1/31 Eric Nelson<eric.nelson@boundarydevices.com>: >> This patch set refactors mxc_spi as described in >> http://lists.denx.de/pipermail/u-boot/2010-March/068791.html >> and requested in >> http://lists.denx.de/pipermail/u-boot/2012-January/116023.html >> in order to add support for the MX6Q in general and the mx6qsabrelite >> specifically. > > If this patch-set is re-send, please specify version Vx and change-log. Thanks, > Hi Jason, I wasn't quite sure how to handle that, since I split up a 7-patch series into independent parts. Any guidance? ^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH 0/3] mxc_spi refactoring (for mx6q and mx6qsabrelite) 2012-01-31 13:39 ` Eric Nelson @ 2012-02-01 4:49 ` Jason Hui 0 siblings, 0 replies; 14+ messages in thread From: Jason Hui @ 2012-02-01 4:49 UTC (permalink / raw) To: u-boot Eric, On Tue, Jan 31, 2012 at 9:39 PM, Eric Nelson <eric.nelson@boundarydevices.com> wrote: > On 01/30/2012 11:51 PM, Jason Liu wrote: >> >> Eric, >> >> 2012/1/31 Eric Nelson<eric.nelson@boundarydevices.com>: >>> >>> This patch set refactors mxc_spi as described in >>> ? ?http://lists.denx.de/pipermail/u-boot/2010-March/068791.html >>> and requested in >>> ? ?http://lists.denx.de/pipermail/u-boot/2012-January/116023.html >>> in order to add support for the MX6Q in general and the mx6qsabrelite >>> specifically. >> >> >> If this patch-set is re-send, please specify version Vx and change-log. >> Thanks, >> > Hi Jason, > > I wasn't quite sure how to handle that, since I split up a 7-patch > series into independent parts. > > Any guidance? IMHO, if the patches is resent with changes you need specify Vx and change-log. if the patches is resent with no changes you need have the keywords resend and add some comments blow --- to tell the reader why resend. Jason ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2012-02-01 4:49 UTC | newest] Thread overview: 14+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2012-01-30 19:52 [U-Boot] [PATCH 0/3] mxc_spi refactoring (for mx6q and mx6qsabrelite) Eric Nelson 2012-01-30 19:52 ` [U-Boot] [PATCH 1/3] mxc_spi: move machine specifics into CPU headers Eric Nelson 2012-01-31 9:15 ` Jason Hui 2012-01-30 19:52 ` [U-Boot] [PATCH 2/3] mx6q: Add support for ECSPI through mxc_spi driver Eric Nelson 2012-01-31 9:20 ` Jason Hui 2012-01-30 19:52 ` [U-Boot] [PATCH 3/3] mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform Eric Nelson 2012-01-31 9:31 ` Jason Hui 2012-01-31 14:16 ` Eric Nelson 2012-01-31 15:00 ` Stefano Babic 2012-01-31 17:50 ` [U-Boot] MX6q SPI refactoring and related patches Eric Nelson 2012-01-31 6:51 ` [U-Boot] [PATCH 0/3] mxc_spi refactoring (for mx6q and mx6qsabrelite) Jason Liu 2012-01-31 6:59 ` Jason Hui 2012-01-31 13:39 ` Eric Nelson 2012-02-01 4:49 ` Jason Hui
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