From mboxrd@z Thu Jan 1 00:00:00 1970 From: Heiko Schocher Date: Thu, 02 Feb 2012 10:34:19 +0100 Subject: [U-Boot] [PATCH v5 4/7] arm, arm926ejs: Do not clear the V bit on DA850 SoCs In-Reply-To: References: <1328018214-6461-1-git-send-email-christian.riesch@omicron.at> <1328018214-6461-5-git-send-email-christian.riesch@omicron.at> <4F28EADB.50301@denx.de> Message-ID: <4F2A589B.8060507@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hello Christian, Christian Riesch wrote: > Hello Heiko and Sughosh, > > On Wed, Feb 1, 2012 at 8:33 AM, Heiko Schocher wrote: >> Sughosh Ganu wrote: >>> On Tue, Jan 31, 2012 at 7:26 PM, Christian Riesch < >>> christian.riesch at omicron.at> wrote: >>> >>>> The V bit of the c1 register of CP15 should not be cleared >>>> since the SoC has no valid memory at 0x00000000. >>>> >>>> Signed-off-by: Christian Riesch >>>> Reported-by: Sughosh Ganu >>>> Cc: Albert Aribaud >>>> Cc: Tom Rini >>>> --- >>>> arch/arm/cpu/arm926ejs/start.S | 5 ++++- >>>> 1 files changed, 4 insertions(+), 1 deletions(-) >>>> >>>> diff --git a/arch/arm/cpu/arm926ejs/start.S >>>> b/arch/arm/cpu/arm926ejs/start.S >>>> index b39ed8a..b350480 100644 >>>> --- a/arch/arm/cpu/arm926ejs/start.S >>>> +++ b/arch/arm/cpu/arm926ejs/start.S >>>> @@ -372,7 +372,10 @@ flush_dcache: >>>> * disable MMU and D cache, and enable I cache >>>> */ >>>> mrc p15, 0, r0, c1, c0, 0 >>>> - bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) >>>> */ >>>> + bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ >>>> +#ifndef CONFIG_SOC_DA850 >>>> + bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ >>>> +#endif >>>> >>> Instead of checking for a particular SOC, can we introduce a generic >>> config, something like CONFIG_EXCEPTION_VECTORS_LOW. This way, if other >>> SOC's have a similar requirement, it won't be needed to keep adding checks >>> here. It would also help in case this needs to be implemented for other arm >>> cores, so that we can have a common config option for bypassing this V-bit >>> clear. Just my suggestion. Maybe Tom and Albert can comment. >> Yep, I vote for this too, also this config option should be documented >> in the README. > > Ok, I'll change this to > > #ifdef CONFIG_EXCEPTION_VECTORS_HIGH > orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ > #else > bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ > #endif > > Or should it be CONFIG_SYS_EXCEPTION_VECTORS_HIGH? I think I don't > understand the explanation in README whether it should be _SYS_ or > not. It should be CONFIG_SYS as this is a hardware dependend config option. bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany