From mboxrd@z Thu Jan 1 00:00:00 1970 From: Troy Kisky Date: Fri, 10 Feb 2012 14:02:01 -0700 Subject: [U-Boot] [PATCH v5 5/5] i.mx6q: mx6qsabrelite: Update the network configuration In-Reply-To: <1328659730-7109-5-git-send-email-troy.kisky@boundarydevices.com> References: <1328659730-7109-1-git-send-email-troy.kisky@boundarydevices.com> <1328659730-7109-5-git-send-email-troy.kisky@boundarydevices.com> Message-ID: <4F3585C9.6040001@boundarydevices.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 2/7/2012 5:08 PM, Troy Kisky wrote: > Define CONFIG_PHY_MICREL, and > minimize the tx clock delay. > > There is an issue with 1000 baseTx mode on early revs > of the SabreLite boards. The center tap pin 9 of the mag RJ45 > USB combo was connected to the 3.3 filtered supply. Letting > this pin float solved the problem. Symptoms of the problem > were packets with many extra zeroes tacked on the end, and random > bit flips causing a high rate of CRC errors. 10/100 baseTx worked > fine on all revs. To disable 1000 baseTx for these boards, simply > define the environment variable disable_giga. ie. > > setenv disable_giga 1 > > Signed-off-by: Troy Kisky > Acked-by: Dirk Behme > --- > board/freescale/mx6qsabrelite/mx6qsabrelite.c | 51 +++++++------------------ > include/configs/mx6qsabrelite.h | 2 + > 2 files changed, 16 insertions(+), 37 deletions(-) > > diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c > index a53b01f..2847539 100644 > --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c > +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c > This has a minor conflict with the recently applied 56c8eaf6cf44f8ec674fb863005e73250ad3d31c mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform Would you like me to resend 5/5, 1-5/5, or let you handle. Thanks Troy