From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Mon, 13 Feb 2012 08:08:04 +0100 Subject: [U-Boot] [PATCH v5 5/5] i.mx6q: mx6qsabrelite: Update the network configuration In-Reply-To: <4F3585C9.6040001@boundarydevices.com> References: <1328659730-7109-1-git-send-email-troy.kisky@boundarydevices.com> <1328659730-7109-5-git-send-email-troy.kisky@boundarydevices.com> <4F3585C9.6040001@boundarydevices.com> Message-ID: <4F38B6D4.1070402@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 10/02/2012 22:02, Troy Kisky wrote: > On 2/7/2012 5:08 PM, Troy Kisky wrote: >> Define CONFIG_PHY_MICREL, and >> minimize the tx clock delay. >> >> There is an issue with 1000 baseTx mode on early revs >> of the SabreLite boards. The center tap pin 9 of the mag RJ45 >> USB combo was connected to the 3.3 filtered supply. Letting >> this pin float solved the problem. Symptoms of the problem >> were packets with many extra zeroes tacked on the end, and random >> bit flips causing a high rate of CRC errors. 10/100 baseTx worked >> fine on all revs. To disable 1000 baseTx for these boards, simply >> define the environment variable disable_giga. ie. >> >> setenv disable_giga 1 >> >> Signed-off-by: Troy Kisky >> Acked-by: Dirk Behme >> --- >> board/freescale/mx6qsabrelite/mx6qsabrelite.c | 51 >> +++++++------------------ >> include/configs/mx6qsabrelite.h | 2 + >> 2 files changed, 16 insertions(+), 37 deletions(-) >> >> diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c >> b/board/freescale/mx6qsabrelite/mx6qsabrelite.c >> index a53b01f..2847539 100644 >> --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c >> +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c >> > This has a minor conflict with the recently applied > 56c8eaf6cf44f8ec674fb863005e73250ad3d31c > mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform > > Would you like me to resend 5/5, 1-5/5, or let you handle. Do not worry, I solved the conflict myself. As I can understand, there is not open issues with the patchset, and I will apply the patches after Albert will merge my last pull request. Stefano -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de =====================================================================