From mboxrd@z Thu Jan 1 00:00:00 1970 From: Albert ARIBAUD Date: Mon, 20 Feb 2012 09:01:26 +0100 Subject: [U-Boot] [PATCH 1/2] at91: modified NAND flash timing on meesc board In-Reply-To: <1327497590790-git-send-email-Daniel.Gorsulowski@esd.eu> References: <1327497590790-git-send-email-Daniel.Gorsulowski@esd.eu> Message-ID: <4F41FDD6.5090204@aribaud.net> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Daniel, Le 25/01/2012 14:19, Daniel Gorsulowski a ?crit : > Signed-off-by: Daniel Gorsulowski > --- > board/esd/meesc/meesc.c | 8 ++++---- > 1 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c > index 4882ffc..9dd4375 100644 > --- a/board/esd/meesc/meesc.c > +++ b/board/esd/meesc/meesc.c > @@ -73,20 +73,20 @@ static void meesc_nand_hw_init(void) > writel(csa,&matrix->csa[0]); > > /* Configure SMC CS3 for NAND/SmartMedia */ > - writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | > - AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), > + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | > + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2), > &smc->cs[3].setup); > > writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | > AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), > &smc->cs[3].pulse); > > - writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), > + writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6), > &smc->cs[3].cycle); > writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | > AT91_SMC_MODE_EXNW_DISABLE | > AT91_SMC_MODE_DBW_8 | > - AT91_SMC_MODE_TDF_CYCLE(3), > + AT91_SMC_MODE_TDF_CYCLE(12), > &smc->cs[3].mode); > > /* Configure RDY/BSY */ Considered as a bug fix, and Applied to u-boot-arm/master, thanks. Amicalement, -- Albert.