From mboxrd@z Thu Jan 1 00:00:00 1970 From: Troy Kisky Date: Thu, 22 Mar 2012 20:25:11 -0700 Subject: [U-Boot] [PATCH 1/1] MX53: DDR: Fix ZQHWCTRL field TZQ_CS In-Reply-To: <4F6BD63F.2090300@boundarydevices.com> References: <1332453631-18653-1-git-send-email-troy.kisky@boundarydevices.com> <4F6BD63F.2090300@boundarydevices.com> Message-ID: <4F6BED17.2060002@boundarydevices.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 3/22/2012 6:47 PM, Troy Kisky wrote: > On 3/22/2012 3:00 PM, Troy Kisky wrote: >> Currently, board files are setting this field to 0x01 >> which the manual says is a reserved value. Change to >> use the default of 0x04 - 128 cycles. > Typo, should say default of 0x02 - 128 cycles > Possibly the manual is wrong, and the value of 0x01 corresponds to 64 cycles? My testing was on a DDR2 device where this field is not relevant. >> >> Signed-off-by: Troy Kisky >> --- >> board/freescale/mx53ard/imximage_dd3.cfg | 2 +- >> board/freescale/mx53evk/imximage.cfg | 2 +- >> board/freescale/mx53loco/imximage.cfg | 2 +- >> board/freescale/mx53smd/imximage.cfg | 2 +- >> 4 files changed, 4 insertions(+), 4 deletions(-) >> >> >> >> >> I've tested on an mx53, but this needs much more >> testing before being applied. >> >> >