From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Fri, 23 Mar 2012 10:34:18 +0100 Subject: [U-Boot] [PATCH 1/1] MX53: DDR: Fix ZQHWCTRL field TZQ_CS In-Reply-To: <4F6BED17.2060002@boundarydevices.com> References: <1332453631-18653-1-git-send-email-troy.kisky@boundarydevices.com> <4F6BD63F.2090300@boundarydevices.com> <4F6BED17.2060002@boundarydevices.com> Message-ID: <4F6C439A.7080300@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 23/03/2012 04:25, Troy Kisky wrote: > On 3/22/2012 6:47 PM, Troy Kisky wrote: >> On 3/22/2012 3:00 PM, Troy Kisky wrote: >>> Currently, board files are setting this field to 0x01 >>> which the manual says is a reserved value. Change to >>> use the default of 0x04 - 128 cycles. >> Typo, should say default of 0x02 - 128 cycles >> > Possibly the manual is wrong, and the value of 0x01 corresponds > to 64 cycles? My testing was on a DDR2 device where this field > is not relevant. Is there someone who can answer to this question ? This patch fixes the value according to the manual, without doubts. But if the manual is wrong... Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================