[U-Boot] T4 U-boot: ctrl_regs.c: wr used uninitialized

[U-Boot] T4 U-boot: ctrl_regs.c: wr used uninitialized

[Scott Wood]

I get this in the T4 branch of U-Boot:

> Configuring for T4240QDS_EMU - Board: T4240QDS, Options: EMU
> ctrl_regs.c: In function 'compute_fsl_memctl_config_regs':
> ctrl_regs.c:852:15: warning: 'wr' may be used uninitialized in this function

It does not appear to be a false positive (though it is an error path),
and in any case such warnings should be squashed so that real warnings
stick out.

It was introduced by this patch:

> commit 18496c6d6cf46177e7faeb364cfe5baddb8cf71e
> Author: York Sun <yorksun@freescale.com>
> Date:   Tue Dec 13 14:16:55 2011 -0800
> 
>     powerpc/mpc8xxx: Add support for cas latency 12 and above
>     
>     Required by JEDEC 79-3E for high speed DDR3.
>     Also change "CSn disabled" message to debug.
>     
>     Signed-off-by: York Sun <yorksun@freescale.com>

I also don't see the T4 patches being posted to the mailing list -- why?

And why is there any notion of a 32-bit physical address map for T4, and
a README that suggests the 32-bit address map is used?

-Scott

[U-Boot] T4 U-boot: ctrl_regs.c: wr used uninitialized

[Scott Wood]

On 03/26/2012 02:04 PM, Scott Wood wrote:
> I get this in the T4 branch of U-Boot:
> 
>> Configuring for T4240QDS_EMU - Board: T4240QDS, Options: EMU
>> ctrl_regs.c: In function 'compute_fsl_memctl_config_regs':
>> ctrl_regs.c:852:15: warning: 'wr' may be used uninitialized in this function
> 
> It does not appear to be a false positive (though it is an error path),
> and in any case such warnings should be squashed so that real warnings
> stick out.
> 
> It was introduced by this patch:
> 
>> commit 18496c6d6cf46177e7faeb364cfe5baddb8cf71e
>> Author: York Sun <yorksun@freescale.com>
>> Date:   Tue Dec 13 14:16:55 2011 -0800
>>
>>     powerpc/mpc8xxx: Add support for cas latency 12 and above
>>     
>>     Required by JEDEC 79-3E for high speed DDR3.
>>     Also change "CSn disabled" message to debug.
>>     
>>     Signed-off-by: York Sun <yorksun@freescale.com>
> 
> I also don't see the T4 patches being posted to the mailing list -- why?
> 
> And why is there any notion of a 32-bit physical address map for T4, and
> a README that suggests the 32-bit address map is used?

Please ignore this, I sent it to the wrong mailing list by mistake.

-Scott