From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Mon, 09 Apr 2012 13:21:13 +0200 Subject: [U-Boot] [PATCH 1/2] ARM926EJS: Make asm routines volatile in cache ops In-Reply-To: <1333718707-6443-1-git-send-email-marex@denx.de> References: <1333718707-6443-1-git-send-email-marex@denx.de> Message-ID: <4F82C629.8090803@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 06/04/2012 15:25, Marek Vasut wrote: > We certainly don't want the compiler to reorganise the code for dcache flushing. > > Signed-off-by: Marek Vasut > Cc: Stefano Babic > Cc: Albert ARIBAUD > --- > arch/arm/cpu/arm926ejs/cache.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c > index 5b23e3a..0b36294 100644 > --- a/arch/arm/cpu/arm926ejs/cache.c > +++ b/arch/arm/cpu/arm926ejs/cache.c > @@ -82,7 +82,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop) > start += CONFIG_SYS_CACHELINE_SIZE; > } > > - asm("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0)); > + asm volatile("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0)); > } > > void flush_cache(unsigned long start, unsigned long size) Acked-by: Stefano Babic Thanks to point this issue - the same happens on MX3x. I will send a patch (ptch for cache in ARM1136 is already merged). Stefano -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================