From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Date: Fri, 13 Apr 2012 15:05:01 -0600 Subject: [U-Boot] [PATCH v2 4/7] tegra: fdt: Add NAND controller binding and definitions In-Reply-To: <1334341777-2681-5-git-send-email-sjg@chromium.org> References: <1334341777-2681-1-git-send-email-sjg@chromium.org> <1334341777-2681-5-git-send-email-sjg@chromium.org> Message-ID: <4F8894FD.70307@wwwdotorg.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 04/13/2012 12:29 PM, Simon Glass wrote: > Add a NAND controller along with a bindings file for review. > > Signed-off-by: Simon Glass > +++ b/doc/device-tree-bindings/nand/nvidia-nand.txt I'd prefer this be called nvidia,tegra20-nand.txt so filenames are named according to compatible value. This makes it easier to look things up. > +The device node for a NAND flash device is as described in the document > +"Open Firmware Recommended Practice : Universal Serial Bus" with the This is really based on USB? > +Required properties : > + - compatible : Should be "manufacture,device", "nand-flash" > + - nvidia,page-data-bytes : Number of bytes in the data area > + - nvidia,page-spare-bytes : * Number of bytes in spare area Not sure what that "*" is? > +Nvidia NAND Controller > +---------------------- > + > +The device node for a NAND flash controller is as described in the document > +"Open Firmware Recommended Practice : Universal Serial Bus" with the USB again? > +nand-controller at 0x70008000 { > + compatible = "nvidia,tegra20-nand"; > + wp-gpios = <&gpio 59 0>; /* PH3 */ > + nvidia,width = <8>; > + nvidia,timing = <26 100 20 80 20 10 12 10 70>; > + nand at 0 { > + compatible = "hynix,hy27uf4g2b", "nand-flash"; The TRM says there can be up to 8 chip selects. Don't the NAND device sub-nodes need a reg property to indicate which chip-select they're on? Also, the TRM mentions async vs. ONFI devices. Don't we need properties somewhere to configure that kind of thing? > + nvidia,page-data-bytes = <2048>; > + nvidia,tag-ecc-bytes = <4>; > + nvidia,tag-bytes = <20>; > + nvidia,data-ecc-bytes = <36>; > + nvidia,skipped-spare-bytes = <4>; > + nvidia,page-spare-bytes = <64>; > + }; > +};