From mboxrd@z Thu Jan  1 00:00:00 1970
From: Scott Wood <scottwood@freescale.com>
Date: Tue, 17 Apr 2012 13:38:33 -0500
Subject: [U-Boot] [PATCH v2 4/7] tegra: fdt: Add NAND controller binding
	and definitions
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	<4F8894FD.70307@wwwdotorg.org>
	<CAPnjgZ1uXbLUtMTXd5siZsKSF5m3BZGRtkGiEYhK+PQO1PbpNQ@mail.gmail.com>
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On 04/17/2012 01:33 PM, Simon Glass wrote:
> Hi Stephen,
> 
> On Fri, Apr 13, 2012 at 2:05 PM, Stephen Warren <swarren@wwwdotorg.org> wrote:
>> On 04/13/2012 12:29 PM, Simon Glass wrote:
>>> +nand-controller at 0x70008000 {
>>> +     compatible = "nvidia,tegra20-nand";
>>> +     wp-gpios = <&gpio 59 0>;                /* PH3 */
>>> +     nvidia,width = <8>;
>>> +     nvidia,timing = <26 100 20 80 20 10 12 10 70>;
>>> +     nand at 0 {
>>> +             compatible = "hynix,hy27uf4g2b", "nand-flash";
>>
>> The TRM says there can be up to 8 chip selects. Don't the NAND device
>> sub-nodes need a reg property to indicate which chip-select they're on?
> 
> We don't have driver support for this at present.

That shouldn't matter.  The device tree is about describing the
hardware.  Ideally the device tree shouldn't have to change if in the
future you do get driver support for it.

Also, unit addresses should only be present if reg is present, and they
should match.

-Scott