From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bo Shen Date: Tue, 15 May 2012 10:18:12 +0800 Subject: [U-Boot] [PATCH] ATMEL/PIO: Enable new feature of PIO on Atmel device In-Reply-To: <4FB12695.906@gmail.com> References: <1336986016-30973-1-git-send-email-voice.shen@atmel.com> <4FB12695.906@gmail.com> Message-ID: <4FB1BCE4.8050804@atmel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 5/14/2012 23:36, Andreas Bie?mann wrote: > Dear Bo Shen, > > On 14.05.2012 11:00, Bo Shen wrote: >> Enable new PIO feature supported by Atmel SoC. >> Using CPU_HAS_PIO3 micro to enable PIO new feature. >> >> Signed-off-by: Bo Shen >> --- >> arch/arm/include/asm/arch-at91/at91_pio.h | 71 ++++++++++++++++- >> drivers/gpio/at91_gpio.c | 123 ++++++++++++++++++++++++++++- >> 2 files changed, 191 insertions(+), 3 deletions(-) >> >> diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/include/asm/arch-at91/at91_pio.h >> index 416cabf..4ceedee 100644 >> --- a/arch/arm/include/asm/arch-at91/at91_pio.h >> +++ b/arch/arm/include/asm/arch-at91/at91_pio.h > > >> @@ -137,11 +180,37 @@ int at91_get_pio_value(unsigned port, unsigned pin); >> #define PIO_PUER 0x64 /* Pull-up Enable Register */ >> #define PIO_PUSR 0x68 /* Pull-up Status Register */ >> #define PIO_ASR 0x70 /* Peripheral A Select Register */ >> +#define PIO_ABCDSR1 0x70 /* Peripheral ABCD Select Register 1 */ >> #define PIO_BSR 0x74 /* Peripheral B Select Register */ >> +#define PIO_ABCDSR2 0x74 /* Peripheral ABCD Select Register 2 */ >> #define PIO_ABSR 0x78 /* AB Status Register */ >> +#define PIO_IFSCDR 0x80 /* Input Filter Slow Clock Disable Register */ >> +#define PIO_IFSCER 0x84 /* Input Filter Slow Clock Enable Register */ >> +#define PIO_IFSCSR 0x88 /* Input Filter Slow Clock Status Register */ >> +#define PIO_SCDR 0x8c /* Slow Clock Divider Debouncing Register */ >> +#define PIO_SCDR_DIV (0x3fff<< 0) /* Slow Clock Divider Mask */ >> +#define PIO_PPDDR 0x90 /* Pad Pull-down Disable Register */ >> +#define PIO_PPDER 0x94 /* Pad Pull-down Enable Register */ >> +#define PIO_PPDSR 0x98 /* Pad Pull-down Status Register */ >> #define PIO_OWER 0xa0 /* Output Write Enable Register */ >> #define PIO_OWDR 0xa4 /* Output Write Disable Register */ >> #define PIO_OWSR 0xa8 /* Output Write Status Register */ >> +#define PIO_AIMER 0xb0 /* Additional INT Modes Enable Register */ >> +#define PIO_AIMDR 0xb4 /* Additional INT Modes Disable Register */ >> +#define PIO_AIMMR 0xb8 /* Additional INT Modes Mask Register */ >> +#define PIO_ESR 0xc0 /* Edge Select Register */ >> +#define PIO_LSR 0xc4 /* Level Select Register */ >> +#define PIO_ELSR 0xc8 /* Edge/Level Status Register */ >> +#define PIO_FELLSR 0xd0 /* Falling Edge/Low Level Select Register */ >> +#define PIO_REHLSR 0xd4 /* Rising Edge/ High Level Select Register */ >> +#define PIO_FRLHSR 0xd8 /* Fall/Rise - Low/High Status Register */ >> +#define PIO_SCHMITT 0x100 /* Schmitt Trigger Register */ >> + >> +#define ABCDSR_PERIPH_A 0x0 >> +#define ABCDSR_PERIPH_B 0x1 >> +#define ABCDSR_PERIPH_C 0x2 >> +#define ABCDSR_PERIPH_D 0x3 >> + >> #endif >> >> #endif > shouldn't we drop the legacy interface completely instead of adding new > definitions? OK. I will deal with this. Thanks. > > > > best regards > > Andreas Bie?mann >