From mboxrd@z Thu Jan 1 00:00:00 1970 From: Scott Wood Date: Fri, 18 May 2012 12:21:37 -0500 Subject: [U-Boot] [PATCH 5/6] cmd_nvedit.c: allow board-specific code before/after saving the environment In-Reply-To: <4FB68209.7050404@freescale.com> References: <1336170092-22538-1-git-send-email-timur@freescale.com> <1336170092-22538-5-git-send-email-timur@freescale.com> <201205140120.45712.vapier@gentoo.org> <4FB12E88.1050906@freescale.com> <20120517221808.2AEAE206271@gemini.denx.de> <4FB58038.8060004@freescale.com> <4FB58187.2040506@freescale.com> <4FB5B078.4050000@freescale.com> <4FB5B222.6000008@freescale.com> <4FB5B455.1010106@freescale.com> <4FB6720B.2050401@freescale.com> <4FB6752A.5080309@freescale.com> <4FB67622.3030803@freescale.com> <4FB678CF.4030501@freescale.com> <4FB68209.7050404@freescale.com> Message-ID: <4FB68521.7010801@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 05/18/2012 12:08 PM, Timur Tabi wrote: > Scott Wood wrote: >> It was over a year ago that I made that request internally. And still >> the answer is "I need this now now now!". > > Who's going to do that work, if not you? Matthew had something working a while ago, I thought. >> NACK any non-SPD NAND boot for a board that otherwise uses SPD, >> particularly if it has socketed RAM. It's not as if we don't know how >> to make this work. > > Well, *I* don't know how to do that. Use a three stage boot where the middle stage runs out of L2 SRAM. -Scott