From: Scott Wood <scottwood@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/9] CACHE: Add cache_aligned() macro
Date: Mon, 25 Jun 2012 16:12:13 -0500 [thread overview]
Message-ID: <4FE8D42D.1000400@freescale.com> (raw)
In-Reply-To: <1340583477-14018-3-git-send-email-marex@denx.de>
On 06/24/2012 07:17 PM, Marek Vasut wrote:
> This macro returns 1 if the argument (address) is aligned, returns
> zero otherwise. This will be used to test user-supplied address to
> various commands to prevent user from loading data to/from unaligned
> address when using caches.
>
> This is made as a macro, because macros are expanded where they are
> used. Therefore it can be easily instrumented to report position of
> the fault.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Wolfgang Denk <wd@denx.de>
> ---
> include/common.h | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/include/common.h b/include/common.h
> index 322569e..17c64b0 100644
> --- a/include/common.h
> +++ b/include/common.h
> @@ -730,6 +730,24 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop);
> void invalidate_dcache_all(void);
> void invalidate_icache_all(void);
>
> +/* Test if address is cache-aligned. Returns 0 if it is, 1 otherwise. */
> +#define cacheline_aligned(addr) \
> + ({ \
> + int __ret; \
> + if (!dcache_status()) { \
> + __ret = 1; \
> + } else if ((addr) & (ARCH_DMA_MINALIGN - 1)) { \
> + puts("Align load address to " \
> + __stringify(ARCH_DMA_MINALIGN) \
> + " bytes when using caches!\n"); \
> + __ret = 0; \
> + } else { \
> + __ret = 1; \
> + } \
> + __ret; \
> + })
What if it's a store rather than a load? If this is only supposed to be
used for loads (because on a store you can flush the cache rather than
invalidate), it's not labelled that way, the changelog says "to/from
unaligned address", and the caller might be common code that doesn't
know which direction the transfer is in. Besides, it would be awkward
user interface to allow an address to be used in one direction but not
the other.
What if the caller wants to try a different strategy if this returns 0,
rather than print an error?
Why should the success of a command depend on whether caches are
enabled? If we're going to forbid unaligned addresses in certain
contexts, shouldn't it always be forbidden to ensure consistent user
experience? Or if we're going to be picky about when we reject it, why
don't we care whether the device in question does DMA, and whether that
DMA is coherent?
-Scott
next prev parent reply other threads:[~2012-06-25 21:12 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-25 0:17 [U-Boot] [PATCH 0/9] CACHE: Finishing touches Marek Vasut
2012-06-25 0:17 ` [U-Boot] [PATCH 1/9] COMMON: Add __stringify() function Marek Vasut
2012-06-25 0:17 ` [U-Boot] [PATCH 2/9] CACHE: Add cache_aligned() macro Marek Vasut
2012-06-25 21:12 ` Scott Wood [this message]
2012-06-25 23:30 ` Marek Vasut
2012-07-07 3:00 ` Aneesh V
2012-06-25 0:17 ` [U-Boot] [PATCH 3/9] CACHE: ext2load: Test if start address is aligned Marek Vasut
2012-06-25 0:17 ` [U-Boot] [PATCH 4/9] CACHE: fatload: " Marek Vasut
2012-06-25 0:17 ` [U-Boot] [PATCH 5/9] CACHE: mmc read/write: " Marek Vasut
2012-06-25 0:17 ` [U-Boot] [PATCH 6/9] CACHE: nand " Marek Vasut
2012-06-25 16:58 ` Scott Wood
2012-06-25 18:43 ` Tom Rini
2012-06-25 20:08 ` Scott Wood
2012-06-25 20:48 ` Tom Rini
2012-06-25 21:17 ` Scott Wood
2012-06-25 21:22 ` Tom Rini
2012-06-25 23:42 ` Marek Vasut
2012-06-26 0:37 ` Scott Wood
2012-06-26 1:16 ` Marek Vasut
2012-06-26 19:38 ` Scott Wood
2012-06-25 23:38 ` Marek Vasut
2012-06-25 23:37 ` Marek Vasut
2012-06-25 23:57 ` Scott Wood
2012-06-26 1:33 ` Marek Vasut
2012-06-26 19:25 ` Scott Wood
2012-06-26 20:39 ` Marek Vasut
2012-07-07 3:05 ` Aneesh V
2012-06-25 0:17 ` [U-Boot] [PATCH 7/9] CACHE: net: " Marek Vasut
2012-06-25 18:05 ` Joe Hershberger
2012-06-25 23:16 ` Marek Vasut
2012-06-25 0:17 ` [U-Boot] [PATCH 8/9] CACHE: net: asix: Fix asix driver to work with data cache on Marek Vasut
2012-06-25 18:07 ` Joe Hershberger
2012-06-25 23:16 ` Marek Vasut
2012-07-06 23:09 ` Marek Vasut
2012-07-06 23:16 ` Marek Vasut
2012-06-25 0:17 ` [U-Boot] [PATCH 9/9] M28EVK: Enable instruction and data cache Marek Vasut
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