From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rini Date: Mon, 9 Jul 2012 01:46:04 -0700 Subject: [U-Boot] [PATCH 1/1] igep0020: set OMAP MUX mcspi1_cs2 pin to GPIO 176 mode In-Reply-To: References: <1341337621-19242-1-git-send-email-javier@dowhile0.org> Message-ID: <4FFA9A4C.9060208@ti.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 07/09/2012 12:32 AM, Enric Balletb? i Serra wrote: > Hi Javier, > > 2012/7/3 Javier Martinez Canillas > > > According to the IGEPv2 Rev.C data-sheet the LAN9221i pin 14 (IRQ) > is connected to the OMAP3730 mcspi1_cs2 pin. Since this omap mux > pin acts as an IRQ line, it has to be configured as an input GPIO. > > IGEPv2 platform code sets the smsc911x_cfg->gpio_irq to GPIO 176 > but since the mux pin default mode is MODE7 (safe_mode) the driver > fails when trying to register the IRQ: > > [ 1.994598] smsc911x: Driver version 2008-10-21 [ 3.704162] > irq 272: nobody cared (try booting with the "irqpoll" option) [ > 3.711364] [] (unwind_backtrace+0x0/0xf0) from > [] (__report_bad_irq+0x20/0xbc) [ 3.720916] > [] (__report_bad_irq+0x20/0xbc) from [] > (note_interrupt+0x1d8/0x238) [ 3.730560] [] > (note_interrupt+0x1d8/0x238) from [] > (handle_irq_event_percpu+0xc0/0x260) [ 3.740936] [] > (handle_irq_event_percpu+0xc0/0x260) from [] > (handle_irq_event+0x3c/0x5c) [ 3.751312] [] > (handle_irq_event+0x3c/0x5c) from [] > (handle_level_irq+0xac/0x10c) [ 3.761047] [] > (handle_level_irq+0xac/0x10c) from [] > (generic_handle_irq+0x30/0x48) [ 3.770935] [] > (generic_handle_irq+0x30/0x48) from [] > (gpio_irq_handler+0x180/0x1d4) [ 3.780944] [] > (gpio_irq_handler+0x180/0x1d4) from [] > (generic_handle_irq+0x30/0x48) [ 3.790954] [] > (generic_handle_irq+0x30/0x48) from [] > (handle_IRQ+0x4c/0xac) [ 3.800231] [] > (handle_IRQ+0x4c/0xac) from [] > (omap3_intc_handle_irq+0x60/0x74) [ 3.809783] [] > (omap3_intc_handle_irq+0x60/0x74) from [] > (__irq_svc+0x44/0x60) [ 3.819213] Exception stack(0xee42fde0 to > 0xee42fe28) [ 3.824554] fde0: 00000001 00000001 00000000 > 00000000 60000013 c06cce14 c06cce14 00000110 [ 3.833190] fe00: > 00000000 c06ccdf4 60000013 ee41d000 fb058064 ee42fe28 c0089e08 > c04976b4 [ 3.841796] fe20: 20000013 ffffffff [ 3.845489] > [] (__irq_svc+0x44/0x60) from [] > (_raw_spin_unlock_irqrestore+0x34/0x44) [ 3.855499] [] > (_raw_spin_unlock_irqrestore+0x34/0x44) from [] > (__setup_irq+0x1b8/0x3f0) [ 3.865875] [] > (__setup_irq+0x1b8/0x3f0) from [] > (request_threaded_irq+0xb8/0x140) [ 3.875701] [] > (request_threaded_irq+0xb8/0x140) from [] > (smsc911x_drv_probe+0x75c/0x11a4) [ 3.886260] [] > (smsc911x_drv_probe+0x75c/0x11a4) from [] > (platform_drv_probe+0x18/0x1c) [ 3.896545] [] > (platform_drv_probe+0x18/0x1c) from [] > (driver_probe_device+0x90/0x210) [ 3.906707] [] > (driver_probe_device+0x90/0x210) from [] > (__driver_attach+0x94/0x98) [ 3.916625] [] > (__driver_attach+0x94/0x98) from [] > (bus_for_each_dev+0x50/0x7c) [ 3.926177] [] > (bus_for_each_dev+0x50/0x7c) from [] > (bus_add_driver+0x184/0x248) [ 3.935821] [] > (bus_add_driver+0x184/0x248) from [] > (driver_register+0x78/0x12c) [ 3.945465] [] > (driver_register+0x78/0x12c) from [] > (do_one_initcall+0x34/0x178) [ 3.955108] [] > (do_one_initcall+0x34/0x178) from [] > (kernel_init+0xfc/0x1c0) [ 3.964385] [] > (kernel_init+0xfc/0x1c0) from [] > (kernel_thread_exit+0x0/0x8) [ 3.973632] handlers: [ > 3.976043] [] smsc911x_irqhandler [ 3.980560] Disabling > IRQ #272 > > Signed-off-by: Javier Martinez Canillas > --- board/isee/igep0020/igep0020.h | > 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) > > diff --git a/board/isee/igep0020/igep0020.h > b/board/isee/igep0020/igep0020.h index 3d6e15f..eb1aa30 100644 --- > a/board/isee/igep0020/igep0020.h +++ > b/board/isee/igep0020/igep0020.h @@ -143,5 +143,6 @@ static void > setup_net_chip(void); MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS > | M4)) /* GPIO_7 */\ MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS > | M4)) /* GPIO_8 */\ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN > | M0)) /* SDRC_CKE0 */\ - MUX_VAL(CP(SDRC_CKE1), (IDIS | > PTU | EN | M0)) /* SDRC_CKE1 */ + MUX_VAL(CP(SDRC_CKE1), > (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */\ + > MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | DIS | M4)) /* > GPIO_176-ETH IRQ */ #endif -- 1.7.7.6 > > > I'm not sure if this is the correct place to do this. > > This was discussed for a long, the main question is who must set > the pin muxer ? > > In my opinion u-boot only should set mux for the pins that it is > using and I think u-boot is not using this IRQ pin for ethernet > driver (not sure, I need to check). At kernel level of course the > driver uses this pin. In my opinion the kernel should guarantees > that this pin is muxed correctly, not u-boot. > > Any other opinion ? How this is solved in others boards ? The kernel must be ensuring the correct muxing. If we don't need something configured U-Boot should not configure it in general. In practice there is a lot of mux setup that has been done in U-Boot in the past. A quick read says we don't need the IRQ pin in U-Boot currently so we shouldn't set it, so barring a correction on that, NAK and correct the kernel. Thanks! - -- Tom -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQIcBAEBAgAGBQJP+ppMAAoJENk4IS6UOR1WH6wP/ivX5WmULKCHDVgsc1jkIeGs vvp+9DTBEpBGVimSSPe8UFQ2bL29W6E50iyudVDnRqQanEAeoGkw8g7hbrKHF5EH Vr4n611EwuU6sBrans53tCgo0LP4Hi8pNnyQvBGyZjSWcy1AF5c9DN1zZwtt+UWk nu+0NKcDH/czLGAo9UaOsdIgcaZPFplxKg7rPjM8yEIyKXA6GhH5wPP/5ObfNkzm RK5ZF25sNWbGSxqZHlcNOVoqX6BZZlFBdEtXv+xwMUBYaxhqwAJOjqgH2x4xXp2H Dt7a/LzXGaOIRm/2Ctept7cdFcInWEVNHFCbIEgAu3TRC69QJNOJV/hsK8DP/ubD Sw9q+4un9Y4VGMwfrCbhtrI38cbOHih3PBdo0TBDIHxe/vYrnIffKfTOsvTZ/uqj FF6ECzhpN3LI/HihgS2Fd/391Llh6iz8WOpXLRfMTwdzlB5kWX9uZcZ4Z3g6raKY 6t8RsbnkhTXFqJdpO3jemnjXBrmNhl9AtHPFX/Bs5OJJ4QNRSE1xnHyhblT8n62c SQAX2z1ctaZ343rQ4EIB6J6wCN/b29oBoD2+KHrd2+6bwurPACVUYuZljXJ0IvQ9 NYrH4TnCeYR0YADm6Th0m8zf2W+KIIny8hTsHKTsj2BoaKB/kWKhMrSJqJP2yc+7 Fg3dAWUDWWzNRZX0/U8v =eY7X -----END PGP SIGNATURE-----