* [U-Boot] S3c64xx: Switch all I/O to use readl/writel function
@ 2012-07-07 9:56 Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 01/13] smdk6400: Move smdk6400 board from Makefile to boards.cfg Zhong Hongbo
` (13 more replies)
0 siblings, 14 replies; 20+ messages in thread
From: Zhong Hongbo @ 2012-07-07 9:56 UTC (permalink / raw)
To: u-boot
This serial patch intent to:
1. Switch all I/O to use readl/writel function
2. Change nand_spl to use SPL framework
3. S3C64XX serial includes s3c6400 and s3c6410,
Here seprate cpu and board file to support to board's of s3c6410.
I test this patch on my s3c6410 development board. the log as following:
U-Boot 2012.04.01-10905-g9fa0c77 (Jul 07 2012 - 15:50:57) for SMDK6400
CPU: S3C64XX at 532MHz
Fclk = 532MHz, Hclk = 133MHz, Pclk = 66MHz (ASYNC Mode)
Board: DMATEK6410
DRAM: 128 MiB
WARNING: Caches not enabled
NAND: 128 MiB
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: dm9000
Hit any key to stop autoboot: 0
DMATEK6410 #
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 01/13] smdk6400: Move smdk6400 board from Makefile to boards.cfg
2012-07-07 9:56 [U-Boot] S3c64xx: Switch all I/O to use readl/writel function Zhong Hongbo
@ 2012-07-07 9:57 ` Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 02/13] S3C64XX: Switch to use readl/writel to operate nand flash Zhong Hongbo
` (12 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Zhong Hongbo @ 2012-07-07 9:57 UTC (permalink / raw)
To: u-boot
From: Zhong Hongbo <bocui107@gmail.com>
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
---
Makefile | 20 --------------------
board/samsung/smdk6400/config.mk | 4 +---
boards.cfg | 2 ++
include/configs/smdk6400.h | 2 +-
4 files changed, 4 insertions(+), 24 deletions(-)
diff --git a/Makefile b/Makefile
index 0197239..e3af33f 100644
--- a/Makefile
+++ b/Makefile
@@ -695,26 +695,6 @@ SX1_config: unconfig
fi;
@$(MKCONFIG) -n $@ SX1 arm arm925t sx1
-#########################################################################
-## ARM1176 Systems
-#########################################################################
-smdk6400_noUSB_config \
-smdk6400_config : unconfig
- @mkdir -p $(obj)include $(obj)board/samsung/smdk6400
- @mkdir -p $(obj)nand_spl/board/samsung/smdk6400
- @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
- @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
- @if [ -z "$(findstring smdk6400_noUSB_config,$@)" ]; then \
- echo "RAM_TEXT = 0x57e00000" >> $(obj)board/samsung/smdk6400/config.tmp;\
- else \
- echo "RAM_TEXT = 0xc7e00000" >> $(obj)board/samsung/smdk6400/config.tmp;\
- fi
- @$(MKCONFIG) smdk6400 arm arm1176 smdk6400 samsung s3c64xx
- @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
-
-#########################################################################
-#########################################################################
-
clean:
@rm -f $(obj)examples/standalone/82559_eeprom \
$(obj)examples/standalone/atmel_df_pow2 \
diff --git a/board/samsung/smdk6400/config.mk b/board/samsung/smdk6400/config.mk
index 6f04c2f..93a1a0d 100644
--- a/board/samsung/smdk6400/config.mk
+++ b/board/samsung/smdk6400/config.mk
@@ -21,10 +21,8 @@
#
# download area is 0x5000c000
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
ifndef CONFIG_NAND_SPL
-CONFIG_SYS_TEXT_BASE = $(RAM_TEXT)
+CONFIG_SYS_TEXT_BASE = $(CONFIG_RAM_TEXT)
else
CONFIG_SYS_TEXT_BASE = 0
endif
diff --git a/boards.cfg b/boards.cfg
index 9205070..a6ca01f 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -47,6 +47,8 @@ flea3 arm arm1136 - CarMedi
mx35pdk arm arm1136 - freescale mx35
apollon arm arm1136 apollon - omap24xx
omap2420h4 arm arm1136 - ti omap24xx
+smdk6400 arm arm1176 smdk6400 samsung s3c64xx smdk6400:NAND_U_BOOT,RAM_TEXT=0xc7e00000
+smdk6400_nousb arm arm1176 smdk6400 samsung s3c64xx smdk6400:NAND_U_BOOT,RAM_TEXT=0x57e00000
tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
integratorap_cm720t arm arm720t integrator armltd - integratorap:CM720T
integratorap_cm920t arm arm920t integrator armltd - integratorap:CM920T
diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
index 04caeef..47326d6 100644
--- a/include/configs/smdk6400.h
+++ b/include/configs/smdk6400.h
@@ -54,7 +54,7 @@
/* input clock of PLL: SMDK6400 has 12MHz input clock */
#define CONFIG_SYS_CLK_FREQ 12000000
-#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000)
+#if !defined(CONFIG_NAND_U_BOOT) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000)
#define CONFIG_ENABLE_MMU
#endif
--
1.7.5.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 02/13] S3C64XX: Switch to use readl/writel to operate nand flash
2012-07-07 9:56 [U-Boot] S3c64xx: Switch all I/O to use readl/writel function Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 01/13] smdk6400: Move smdk6400 board from Makefile to boards.cfg Zhong Hongbo
@ 2012-07-07 9:57 ` Zhong Hongbo
2012-07-09 22:19 ` Scott Wood
2012-07-07 9:57 ` [U-Boot] [PATCH 03/13] S3C64XX: Use readl/writel to operate uart Zhong Hongbo
` (11 subsequent siblings)
13 siblings, 1 reply; 20+ messages in thread
From: Zhong Hongbo @ 2012-07-07 9:57 UTC (permalink / raw)
To: u-boot
From: Zhong Hongbo <bocui107@gmail.com>
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
---
arch/arm/include/asm/arch-s3c64xx/nand.h | 69 +++++++++++++++++++++++
arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 79 ++-------------------------
board/samsung/smdk6400/lowlevel_init.S | 8 ++--
drivers/mtd/nand/s3c64xx.c | 58 +++++++++++++-------
4 files changed, 116 insertions(+), 98 deletions(-)
create mode 100644 arch/arm/include/asm/arch-s3c64xx/nand.h
diff --git a/arch/arm/include/asm/arch-s3c64xx/nand.h b/arch/arm/include/asm/arch-s3c64xx/nand.h
new file mode 100644
index 0000000..51e4d34
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c64xx/nand.h
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2012
+ * Zhong Hongbo <bocui107@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_NAND_H__
+#define __ASM_ARCH_NAND_H__
+
+#define NFCONF_ECC_4BIT (1<<24)
+
+#define NFCONT_ECC_ENC (1<<18)
+#define NFCONT_WP (1<<16)
+#define NFCONT_MECCLOCK (1<<7)
+#define NFCONT_SECCLOCK (1<<6)
+#define NFCONT_INITMECC (1<<5)
+#define NFCONT_INITSECC (1<<4)
+#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC)
+#define NFCONT_CS_ALT (1<<2)
+#define NFCONT_CS (1<<1)
+#define NFCONT_ENABLE (1<<0)
+
+#define NFSTAT_ECCENCDONE (1<<7)
+#define NFSTAT_ECCDECDONE (1<<6)
+#define NFSTAT_RnB (1<<0)
+
+#define NFESTAT0_ECCBUSY (1<<31)
+
+#ifndef __ASSEMBLY__
+/* NAND FLASH */
+struct s3c64xx_nand {
+ u32 nfconf;
+ u32 nfcont;
+ u32 nfcmmd;
+ u32 nfaddr;
+ u32 nfdata;
+ u32 nfmeccdata0;
+ u32 nfmeccdata1;
+ u32 nfseccdata0;
+ u32 nfsblk;
+ u32 nfeblk;
+ u32 nfstat;
+ u32 nfestat0;
+ u32 nfestat1;
+ u32 nfmecc0;
+ u32 nfmecc1;
+ u32 nfsecc;
+ u32 nfmlcbitpt;
+};
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index 10b3324..5cb8976 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -556,80 +556,6 @@
*/
#define ELFIN_NAND_BASE 0x70200000
-#define NFCONF_OFFSET 0x00
-#define NFCONT_OFFSET 0x04
-#define NFCMMD_OFFSET 0x08
-#define NFADDR_OFFSET 0x0c
-#define NFDATA_OFFSET 0x10
-#define NFMECCDATA0_OFFSET 0x14
-#define NFMECCDATA1_OFFSET 0x18
-#define NFSECCDATA0_OFFSET 0x1c
-#define NFSBLK_OFFSET 0x20
-#define NFEBLK_OFFSET 0x24
-#define NFSTAT_OFFSET 0x28
-#define NFESTAT0_OFFSET 0x2c
-#define NFESTAT1_OFFSET 0x30
-#define NFMECC0_OFFSET 0x34
-#define NFMECC1_OFFSET 0x38
-#define NFSECC_OFFSET 0x3c
-#define NFMLCBITPT_OFFSET 0x40
-
-#define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET)
-#define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET)
-#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET)
-#define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET)
-#define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET)
-#define NFMECCDATA0 (ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
-#define NFMECCDATA1 (ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
-#define NFSECCDATA0 (ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
-#define NFSBLK (ELFIN_NAND_BASE + NFSBLK_OFFSET)
-#define NFEBLK (ELFIN_NAND_BASE + NFEBLK_OFFSET)
-#define NFSTAT (ELFIN_NAND_BASE + NFSTAT_OFFSET)
-#define NFESTAT0 (ELFIN_NAND_BASE + NFESTAT0_OFFSET)
-#define NFESTAT1 (ELFIN_NAND_BASE + NFESTAT1_OFFSET)
-#define NFMECC0 (ELFIN_NAND_BASE + NFMECC0_OFFSET)
-#define NFMECC1 (ELFIN_NAND_BASE + NFMECC1_OFFSET)
-#define NFSECC (ELFIN_NAND_BASE + NFSECC_OFFSET)
-#define NFMLCBITPT (ELFIN_NAND_BASE + NFMLCBITPT_OFFSET)
-
-#define NFCONF_REG __REG(ELFIN_NAND_BASE + NFCONF_OFFSET)
-#define NFCONT_REG __REG(ELFIN_NAND_BASE + NFCONT_OFFSET)
-#define NFCMD_REG __REG(ELFIN_NAND_BASE + NFCMMD_OFFSET)
-#define NFADDR_REG __REG(ELFIN_NAND_BASE + NFADDR_OFFSET)
-#define NFDATA_REG __REG(ELFIN_NAND_BASE + NFDATA_OFFSET)
-#define NFDATA8_REG __REGb(ELFIN_NAND_BASE + NFDATA_OFFSET)
-#define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
-#define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
-#define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
-#define NFSBLK_REG __REG(ELFIN_NAND_BASE + NFSBLK_OFFSET)
-#define NFEBLK_REG __REG(ELFIN_NAND_BASE + NFEBLK_OFFSET)
-#define NFSTAT_REG __REG(ELFIN_NAND_BASE + NFSTAT_OFFSET)
-#define NFESTAT0_REG __REG(ELFIN_NAND_BASE + NFESTAT0_OFFSET)
-#define NFESTAT1_REG __REG(ELFIN_NAND_BASE + NFESTAT1_OFFSET)
-#define NFMECC0_REG __REG(ELFIN_NAND_BASE + NFMECC0_OFFSET)
-#define NFMECC1_REG __REG(ELFIN_NAND_BASE + NFMECC1_OFFSET)
-#define NFSECC_REG __REG(ELFIN_NAND_BASE + NFSECC_OFFSET)
-#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET)
-
-#define NFCONF_ECC_4BIT (1<<24)
-
-#define NFCONT_ECC_ENC (1<<18)
-#define NFCONT_WP (1<<16)
-#define NFCONT_MECCLOCK (1<<7)
-#define NFCONT_SECCLOCK (1<<6)
-#define NFCONT_INITMECC (1<<5)
-#define NFCONT_INITSECC (1<<4)
-#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC)
-#define NFCONT_CS_ALT (1<<2)
-#define NFCONT_CS (1<<1)
-#define NFCONT_ENABLE (1<<0)
-
-#define NFSTAT_ECCENCDONE (1<<7)
-#define NFSTAT_ECCDECDONE (1<<6)
-#define NFSTAT_RnB (1<<0)
-
-#define NFESTAT0_ECCBUSY (1<<31)
-
/*
* Interrupt
*/
@@ -890,6 +816,11 @@ static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr)
{
return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400));
}
+
+static inline unsigned int s3c64xx_get_base_nand(void)
+{
+ return ELFIN_NAND_BASE;
+}
#endif
#endif /*__S3C6400_H__*/
diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S
index f7ce176..4a82e4d 100644
--- a/board/samsung/smdk6400/lowlevel_init.S
+++ b/board/samsung/smdk6400/lowlevel_init.S
@@ -269,14 +269,14 @@ uart_asm_init:
*/
nand_asm_init:
ldr r0, =ELFIN_NAND_BASE
- ldr r1, [r0, #NFCONF_OFFSET]
+ ldr r1, [r0, #0x0] @NFCONF_OFFSET
orr r1, r1, #0x70
orr r1, r1, #0x7700
- str r1, [r0, #NFCONF_OFFSET]
+ str r1, [r0, #0x0]
- ldr r1, [r0, #NFCONT_OFFSET]
+ ldr r1, [r0, #0x04] @NFCONT_OFFSET
orr r1, r1, #0x07
- str r1, [r0, #NFCONT_OFFSET]
+ str r1, [r0, #0x04]
mov pc, lr
#endif
diff --git a/drivers/mtd/nand/s3c64xx.c b/drivers/mtd/nand/s3c64xx.c
index 87f0341..1d6bd67 100644
--- a/drivers/mtd/nand/s3c64xx.c
+++ b/drivers/mtd/nand/s3c64xx.c
@@ -31,6 +31,7 @@
#include <linux/mtd/nand.h>
#include <asm/arch/s3c6400.h>
+#include <asm/arch/nand.h>
#include <asm/io.h>
#include <asm/errno.h>
@@ -42,6 +43,11 @@ static int nand_cs[MAX_CHIPS] = {0, 1};
#define printf(arg...) do {} while (0)
#endif
+static inline struct s3c64xx_nand *s3c_get_base_nand(void)
+{
+ return (struct s3c64xx_nand *)s3c64xx_get_base_nand();
+}
+
/* Nand flash definition values by jsgood */
#ifdef S3C_NAND_DEBUG
/*
@@ -64,7 +70,8 @@ static void print_oob(const char *header, struct mtd_info *mtd)
static void s3c_nand_select_chip(struct mtd_info *mtd, int chip)
{
- int ctrl = readl(NFCONT);
+ struct s3c64xx_nand *const nand = s3c_get_base_nand();
+ int ctrl = readl(&nand->nfcont);
switch (chip) {
case -1:
@@ -80,7 +87,7 @@ static void s3c_nand_select_chip(struct mtd_info *mtd, int chip)
return;
}
- writel(ctrl, NFCONT);
+ writel(ctrl, &nand->nfcont);
}
/*
@@ -89,15 +96,16 @@ static void s3c_nand_select_chip(struct mtd_info *mtd, int chip)
*/
static void s3c_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
+ struct s3c64xx_nand *const nand = s3c_get_base_nand();
struct nand_chip *this = mtd->priv;
if (ctrl & NAND_CTRL_CHANGE) {
if (ctrl & NAND_CLE)
- this->IO_ADDR_W = (void __iomem *)NFCMMD;
+ this->IO_ADDR_W = (void *)&nand->nfcmmd;
else if (ctrl & NAND_ALE)
- this->IO_ADDR_W = (void __iomem *)NFADDR;
+ this->IO_ADDR_W = (void *)&nand->nfaddr;
else
- this->IO_ADDR_W = (void __iomem *)NFDATA;
+ this->IO_ADDR_W = (void *)&nand->nfdata;
if (ctrl & NAND_NCE)
s3c_nand_select_chip(mtd, *(int *)this->priv);
else
@@ -114,7 +122,9 @@ static void s3c_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
*/
static int s3c_nand_device_ready(struct mtd_info *mtdinfo)
{
- return !!(readl(NFSTAT) & NFSTAT_RnB);
+ struct s3c64xx_nand *const nand = s3c_get_base_nand();
+
+ return !!(readl(&nand->nfstat) & NFSTAT_RnB);
}
#ifdef CONFIG_SYS_S3C_NAND_HWECC
@@ -124,6 +134,7 @@ static int s3c_nand_device_ready(struct mtd_info *mtdinfo)
*/
static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode)
{
+ struct s3c64xx_nand *const nand = s3c_get_base_nand();
u_long nfcont, nfconf;
/*
@@ -131,12 +142,12 @@ static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode)
* those with non-zero ID[3][3:2], which anyway only holds for ST
* (Numonyx) chips
*/
- nfconf = readl(NFCONF) & ~NFCONF_ECC_4BIT;
+ nfconf = readl(&nand->nfconf) & ~NFCONF_ECC_4BIT;
- writel(nfconf, NFCONF);
+ writel(nfconf, &nand->nfconf);
/* Initialize & unlock */
- nfcont = readl(NFCONT);
+ nfcont = readl(&nand->nfcont);
nfcont |= NFCONT_INITECC;
nfcont &= ~NFCONT_MECCLOCK;
@@ -145,7 +156,7 @@ static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode)
else if (mode == NAND_ECC_READ)
nfcont &= ~NFCONT_ECC_ENC;
- writel(nfcont, NFCONT);
+ writel(nfcont, &nand->nfcont);
}
/*
@@ -156,14 +167,15 @@ static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode)
static int s3c_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
u_char *ecc_code)
{
+ struct s3c64xx_nand *const nand = s3c_get_base_nand();
u_long nfcont, nfmecc0;
/* Lock */
- nfcont = readl(NFCONT);
+ nfcont = readl(&nand->nfcont);
nfcont |= NFCONT_MECCLOCK;
- writel(nfcont, NFCONT);
+ writel(nfcont, &nand->nfcont);
- nfmecc0 = readl(NFMECC0);
+ nfmecc0 = readl(&nand->nfmecc0);
ecc_code[0] = nfmecc0 & 0xff;
ecc_code[1] = (nfmecc0 >> 8) & 0xff;
@@ -185,18 +197,19 @@ static int s3c_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
static int s3c_nand_correct_data(struct mtd_info *mtd, u_char *dat,
u_char *read_ecc, u_char *calc_ecc)
{
- int ret = -1;
+ struct s3c64xx_nand *const nand = s3c_get_base_nand();
u_long nfestat0, nfmeccdata0, nfmeccdata1, err_byte_addr;
u_char err_type, repaired;
+ int ret = -1;
/* SLC: Write ecc to compare */
nfmeccdata0 = (calc_ecc[1] << 16) | calc_ecc[0];
nfmeccdata1 = (calc_ecc[3] << 16) | calc_ecc[2];
- writel(nfmeccdata0, NFMECCDATA0);
- writel(nfmeccdata1, NFMECCDATA1);
+ writel(nfmeccdata0, &nand->nfmeccdata0);
+ writel(nfmeccdata1, &nand->nfmeccdata1);
/* Read ecc status */
- nfestat0 = readl(NFESTAT0);
+ nfestat0 = readl(&nand->nfestat0);
err_type = nfestat0 & 0x3;
switch (err_type) {
@@ -254,15 +267,20 @@ static int s3c_nand_correct_data(struct mtd_info *mtd, u_char *dat,
*/
int board_nand_init(struct nand_chip *nand)
{
+ struct s3c64xx_nand *const nand_reg = s3c_get_base_nand();
static int chip_n;
+ unsigned int nfcont;
if (chip_n >= MAX_CHIPS)
return -ENODEV;
- NFCONT_REG = (NFCONT_REG & ~NFCONT_WP) | NFCONT_ENABLE | 0x6;
+ nfcont = readl(&nand_reg->nfcont);
+ nfcont &= ~NFCONT_WP;
+ nfcont |= NFCONT_ENABLE | 0x6;
+ writel(nfcont, &nand_reg->nfcont);
- nand->IO_ADDR_R = (void __iomem *)NFDATA;
- nand->IO_ADDR_W = (void __iomem *)NFDATA;
+ nand->IO_ADDR_R = (void *)&nand_reg->nfdata;
+ nand->IO_ADDR_W = (void *)&nand_reg->nfdata;
nand->cmd_ctrl = s3c_nand_hwcontrol;
nand->dev_ready = s3c_nand_device_ready;
nand->select_chip = s3c_nand_select_chip;
--
1.7.5.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 03/13] S3C64XX: Use readl/writel to operate uart
2012-07-07 9:56 [U-Boot] S3c64xx: Switch all I/O to use readl/writel function Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 01/13] smdk6400: Move smdk6400 board from Makefile to boards.cfg Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 02/13] S3C64XX: Switch to use readl/writel to operate nand flash Zhong Hongbo
@ 2012-07-07 9:57 ` Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 04/13] S3C64XX: add pwm for s3c64xx support Zhong Hongbo
` (10 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Zhong Hongbo @ 2012-07-07 9:57 UTC (permalink / raw)
To: u-boot
From: Zhong Hongbo <bocui107@gmail.com>
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
---
arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 65 +--------------------------
arch/arm/include/asm/arch-s3c64xx/s3c64x0.h | 31 -------------
arch/arm/include/asm/arch-s3c64xx/uart.h | 54 ++++++++++++++++++++++
board/samsung/smdk6400/lowlevel_init.S | 8 ---
drivers/serial/s3c64xx.c | 50 +++++++++++++--------
5 files changed, 87 insertions(+), 121 deletions(-)
create mode 100644 arch/arm/include/asm/arch-s3c64xx/uart.h
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index 5cb8976..c6b41e8 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -582,62 +582,6 @@
*/
#define ELFIN_UART_BASE 0x7F005000
-#define ELFIN_UART0_OFFSET 0x0000
-#define ELFIN_UART1_OFFSET 0x0400
-#define ELFIN_UART2_OFFSET 0x0800
-
-#define ULCON_OFFSET 0x00
-#define UCON_OFFSET 0x04
-#define UFCON_OFFSET 0x08
-#define UMCON_OFFSET 0x0C
-#define UTRSTAT_OFFSET 0x10
-#define UERSTAT_OFFSET 0x14
-#define UFSTAT_OFFSET 0x18
-#define UMSTAT_OFFSET 0x1C
-#define UTXH_OFFSET 0x20
-#define URXH_OFFSET 0x24
-#define UBRDIV_OFFSET 0x28
-#define UDIVSLOT_OFFSET 0x2C
-#define UINTP_OFFSET 0x30
-#define UINTSP_OFFSET 0x34
-#define UINTM_OFFSET 0x38
-
-#define ULCON0_REG __REG(0x7F005000)
-#define UCON0_REG __REG(0x7F005004)
-#define UFCON0_REG __REG(0x7F005008)
-#define UMCON0_REG __REG(0x7F00500C)
-#define UTRSTAT0_REG __REG(0x7F005010)
-#define UERSTAT0_REG __REG(0x7F005014)
-#define UFSTAT0_REG __REG(0x7F005018)
-#define UMSTAT0_REG __REG(0x7F00501c)
-#define UTXH0_REG __REG(0x7F005020)
-#define URXH0_REG __REG(0x7F005024)
-#define UBRDIV0_REG __REG(0x7F005028)
-#define UDIVSLOT0_REG __REG(0x7F00502c)
-#define UINTP0_REG __REG(0x7F005030)
-#define UINTSP0_REG __REG(0x7F005034)
-#define UINTM0_REG __REG(0x7F005038)
-
-#define ULCON1_REG __REG(0x7F005400)
-#define UCON1_REG __REG(0x7F005404)
-#define UFCON1_REG __REG(0x7F005408)
-#define UMCON1_REG __REG(0x7F00540C)
-#define UTRSTAT1_REG __REG(0x7F005410)
-#define UERSTAT1_REG __REG(0x7F005414)
-#define UFSTAT1_REG __REG(0x7F005418)
-#define UMSTAT1_REG __REG(0x7F00541c)
-#define UTXH1_REG __REG(0x7F005420)
-#define URXH1_REG __REG(0x7F005424)
-#define UBRDIV1_REG __REG(0x7F005428)
-#define UDIVSLOT1_REG __REG(0x7F00542c)
-#define UINTP1_REG __REG(0x7F005430)
-#define UINTSP1_REG __REG(0x7F005434)
-#define UINTM1_REG __REG(0x7F005438)
-
-#define UTRSTAT_TX_EMPTY (1 << 2)
-#define UTRSTAT_RX_READY (1 << 0)
-#define UART_ERR_MASK 0xF
-
/*
* PWM timer
*/
@@ -804,17 +748,12 @@
#define DMC_DDR_USER_CONFIG 1
#ifndef __ASSEMBLY__
-enum s3c64xx_uarts_nr {
- S3C64XX_UART0,
- S3C64XX_UART1,
- S3C64XX_UART2,
-};
#include "s3c64x0.h"
-static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr)
+static inline unsigned int s3c64xx_get_base_uart(void)
{
- return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400));
+ return ELFIN_UART_BASE;
}
static inline unsigned int s3c64xx_get_base_nand(void)
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h b/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
index 0bbf1d0..7add68c 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
@@ -40,37 +40,6 @@
#include <asm/types.h>
-/* UART (see manual chapter 11) */
-typedef struct {
- volatile u32 ULCON;
- volatile u32 UCON;
- volatile u32 UFCON;
- volatile u32 UMCON;
- volatile u32 UTRSTAT;
- volatile u32 UERSTAT;
- volatile u32 UFSTAT;
- volatile u32 UMSTAT;
-#ifdef __BIG_ENDIAN
- volatile u8 res1[3];
- volatile u8 UTXH;
- volatile u8 res2[3];
- volatile u8 URXH;
-#else /* Little Endian */
- volatile u8 UTXH;
- volatile u8 res1[3];
- volatile u8 URXH;
- volatile u8 res2[3];
-#endif
- volatile u32 UBRDIV;
-#ifdef __BIG_ENDIAN
- volatile u8 res3[2];
- volatile u16 UDIVSLOT;
-#else
- volatile u16 UDIVSLOT;
- volatile u8 res3[2];
-#endif
-} s3c64xx_uart;
-
/* PWM TIMER (see manual chapter 10) */
typedef struct {
volatile u32 TCNTB;
diff --git a/arch/arm/include/asm/arch-s3c64xx/uart.h b/arch/arm/include/asm/arch-s3c64xx/uart.h
new file mode 100644
index 0000000..f3f37aa
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c64xx/uart.h
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2012
+ * Zhong Hongbo <bocui107@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_UART__
+#define __ASM_ARCH_UART__
+
+#ifndef __ASSEMBLY__
+
+enum s3c64xx_uarts_nr {
+ S3C64XX_UART0,
+ S3C64XX_UART1,
+ S3C64XX_UART2,
+};
+
+/* UART (see manual chapter 11) */
+struct s3c64xx_uart {
+ unsigned int ulcon;
+ unsigned int ucon;
+ unsigned int ufcon;
+ unsigned int umcon;
+ unsigned int utrstat;
+ unsigned int uerstat;
+ unsigned int ufstat;
+ unsigned int umstat;
+ unsigned int utxh;
+ unsigned int urxh;
+ unsigned int ubrdiv;
+ unsigned int udivslot;
+ unsigned int uintp;
+ unsigned int uintsp;
+ unsigned int uintm;
+} s3c64xx_uart;
+#endif
+#endif
diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S
index 4a82e4d..1142be1 100644
--- a/board/samsung/smdk6400/lowlevel_init.S
+++ b/board/samsung/smdk6400/lowlevel_init.S
@@ -36,14 +36,6 @@
#include <asm/arch/s3c6400.h>
-#ifdef CONFIG_SERIAL1
-#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET)
-#elif defined(CONFIG_SERIAL2)
-#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART1_OFFSET)
-#else
-#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART2_OFFSET)
-#endif
-
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
diff --git a/drivers/serial/s3c64xx.c b/drivers/serial/s3c64xx.c
index a88e930..2959669 100644
--- a/drivers/serial/s3c64xx.c
+++ b/drivers/serial/s3c64xx.c
@@ -22,8 +22,9 @@
*/
#include <common.h>
-
+#include <asm/io.h>
#include <asm/arch/s3c6400.h>
+#include <asm/arch/uart.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -42,6 +43,11 @@ DECLARE_GLOBAL_DATA_PTR;
#define barrier() asm volatile("" ::: "memory")
+static inline struct s3c64xx_uart *s3c_get_base_uart(void)
+{
+ u32 offset = UART_NR * 0x4000;
+ return (struct s3c64xx_uart *)(s3c64xx_get_base_uart() + offset);
+}
/*
* The coefficient, used to calculate the baudrate on S3C6400 UARTs is
* calculated as
@@ -70,15 +76,16 @@ static const int udivslot[] = {
void serial_setbrg(void)
{
- s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
+ struct s3c64xx_uart *const uart = s3c_get_base_uart();
u32 pclk = get_PCLK();
u32 baudrate = gd->baudrate;
+ unsigned int val;
int i;
- i = (pclk / baudrate) % 16;
+ val = pclk / baudrate;
- uart->UBRDIV = pclk / baudrate / 16 - 1;
- uart->UDIVSLOT = udivslot[i];
+ writel(val / 16 - 1, &uart->ubrdiv);
+ writew(udivslot[val % 16], &uart->udivslot);
for (i = 0; i < 100; i++)
barrier();
@@ -90,16 +97,19 @@ void serial_setbrg(void)
*/
int serial_init(void)
{
- s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
+ struct s3c64xx_uart *const uart = s3c_get_base_uart();
/* reset and enable FIFOs, set triggers to the maximum */
- uart->UFCON = 0xff;
- uart->UMCON = 0;
+ writel(0, &uart->ufcon);
+ writel(0, &uart->umcon);
/* 8N1 */
- uart->ULCON = 3;
+ writel(0x3, &uart->ulcon);
/* No interrupts, no DMA, pure polling */
- uart->UCON = 5;
-
+#if defined(CONFIG_S3C6400)
+ writel(0x5, &uart->ucon);
+#else
+ writel(0xe45, &uart->ucon);
+#endif
serial_setbrg();
return 0;
@@ -112,12 +122,13 @@ int serial_init(void)
*/
int serial_getc(void)
{
- s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
+ struct s3c64xx_uart *const uart = s3c_get_base_uart();
/* wait for character to arrive */
- while (!(uart->UTRSTAT & 0x1));
+ while (!(readl(&uart->utrstat) & 0x1))
+ ;
- return uart->URXH & 0xff;
+ return (int)(readb(&uart->urxh) & 0xff);
}
#ifdef CONFIG_MODEM_SUPPORT
@@ -139,7 +150,7 @@ void enable_putc(void)
*/
void serial_putc(const char c)
{
- s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
+ struct s3c64xx_uart *const uart = s3c_get_base_uart();
#ifdef CONFIG_MODEM_SUPPORT
if (be_quiet)
@@ -147,9 +158,10 @@ void serial_putc(const char c)
#endif
/* wait for room in the tx FIFO */
- while (!(uart->UTRSTAT & 0x2));
+ while (!(readl(&uart->utrstat) & 0x2))
+ ;
- uart->UTXH = c;
+ writeb(c, &uart->utxh);
/* If \n, also do \r */
if (c == '\n')
@@ -161,9 +173,9 @@ void serial_putc(const char c)
*/
int serial_tstc(void)
{
- s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
+ struct s3c64xx_uart *const uart = s3c_get_base_uart();
- return uart->UTRSTAT & 0x1;
+ return readl(&uart->utrstat) & 0x1;
}
void serial_puts(const char *s)
--
1.7.5.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 04/13] S3C64XX: add pwm for s3c64xx support
2012-07-07 9:56 [U-Boot] S3c64xx: Switch all I/O to use readl/writel function Zhong Hongbo
` (2 preceding siblings ...)
2012-07-07 9:57 ` [U-Boot] [PATCH 03/13] S3C64XX: Use readl/writel to operate uart Zhong Hongbo
@ 2012-07-07 9:57 ` Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 05/13] S3C64XX: reference s5p cpu time system for s3c64xx timer Zhong Hongbo
` (9 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Zhong Hongbo @ 2012-07-07 9:57 UTC (permalink / raw)
To: u-boot
From: Zhong Hongbo <bocui107@gmail.com>
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
---
arch/arm/cpu/arm1176/s3c64xx/Makefile | 1 +
arch/arm/cpu/arm1176/s3c64xx/pwm.c | 189 +++++++++++++++++++++++++++
arch/arm/include/asm/arch-s3c64xx/pwm.h | 70 ++++++++++
arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 57 ++-------
arch/arm/include/asm/arch-s3c64xx/s3c64x0.h | 59 ---------
include/configs/smdk6400.h | 3 +
6 files changed, 272 insertions(+), 107 deletions(-)
create mode 100644 arch/arm/cpu/arm1176/s3c64xx/pwm.c
create mode 100644 arch/arm/include/asm/arch-s3c64xx/pwm.h
delete mode 100644 arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
diff --git a/arch/arm/cpu/arm1176/s3c64xx/Makefile b/arch/arm/cpu/arm1176/s3c64xx/Makefile
index 0785b19..966663f 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/Makefile
+++ b/arch/arm/cpu/arm1176/s3c64xx/Makefile
@@ -32,6 +32,7 @@ SOBJS = reset.o
COBJS-$(CONFIG_S3C6400) += cpu_init.o speed.o
COBJS-y += timer.o
+COBJS-$(CONFIG_PWM) += pwm.o
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
diff --git a/arch/arm/cpu/arm1176/s3c64xx/pwm.c b/arch/arm/cpu/arm1176/s3c64xx/pwm.c
new file mode 100644
index 0000000..d1d70ff
--- /dev/null
+++ b/arch/arm/cpu/arm1176/s3c64xx/pwm.c
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2012
+ *
+ * Zhong Hongbo <bocui107@gmail.com>
+ *
+ * based on arch/arm/cpu/armv7/s5p-common/sromc.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <pwm.h>
+#include <asm/io.h>
+#include <asm/arch/s3c6400.h>
+#include <asm/arch/pwm.h>
+
+int pwm_enable(int pwm_id)
+{
+ const struct s3c_timer *pwm =
+ (struct s3c_timer *)s3c64xx_get_base_timer();
+ unsigned long tcon;
+
+ tcon = readl(&pwm->tcon);
+ tcon |= TCON_START(pwm_id);
+
+ writel(tcon, &pwm->tcon);
+
+ return 0;
+}
+
+void pwm_disable(int pwm_id)
+{
+ const struct s3c_timer *pwm =
+ (struct s3c_timer *)s3c64xx_get_base_timer();
+ unsigned long tcon;
+
+ tcon = readl(&pwm->tcon);
+ tcon &= ~TCON_START(pwm_id);
+
+ writel(tcon, &pwm->tcon);
+}
+
+static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq)
+{
+ unsigned long tin_parent_rate;
+ unsigned int div;
+
+ tin_parent_rate = get_PCLK();
+
+ for (div = 2; div <= 16; div *= 2) {
+ if ((tin_parent_rate / (div << 16)) < freq)
+ return tin_parent_rate / div;
+ }
+
+ return tin_parent_rate / 16;
+}
+
+#define NS_IN_HZ (1000000000UL)
+
+int pwm_config(int pwm_id, int duty_ns, int period_ns)
+{
+ const struct s3c_timer *pwm =
+ (struct s3c_timer *)s3c64xx_get_base_timer();
+ unsigned int offset;
+ unsigned long tin_rate;
+ unsigned long tin_ns;
+ unsigned long period;
+ unsigned long tcon;
+ unsigned long tcnt;
+ unsigned long tcmp;
+
+ /*
+ * We currently avoid using 64bit arithmetic by using the
+ * fact that anything faster than 1GHz is easily representable
+ * by 32bits.
+ */
+ if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ)
+ return -ERANGE;
+
+ if (duty_ns > period_ns)
+ return -EINVAL;
+
+ period = NS_IN_HZ / period_ns;
+
+ /* Check to see if we are changing the clock rate of the PWM */
+ tin_rate = pwm_calc_tin(pwm_id, period);
+
+ tin_ns = NS_IN_HZ / tin_rate;
+ tcnt = period_ns / tin_ns;
+
+ /* Note, counters count down */
+ tcmp = duty_ns / tin_ns;
+ tcmp = tcnt - tcmp;
+
+ /*
+ * the pwm hw only checks the compare register after a decrement,
+ * so the pin never toggles if tcmp = tcnt
+ */
+ if (tcmp == tcnt)
+ tcmp--;
+
+ if (tcmp < 0)
+ tcmp = 0;
+
+ /* Update the PWM register block. */
+ offset = pwm_id * 3;
+ if (pwm_id < 4) {
+ writel(tcnt, &pwm->tcntb0 + offset);
+ writel(tcmp, &pwm->tcmpb0 + offset);
+ }
+
+ tcon = readl(&pwm->tcon);
+ tcon |= TCON_UPDATE(pwm_id);
+ if (pwm_id < 4)
+ tcon |= TCON_AUTO_RELOAD(pwm_id);
+ else
+ tcon |= TCON4_AUTO_RELOAD;
+ writel(tcon, &pwm->tcon);
+
+ tcon &= ~TCON_UPDATE(pwm_id);
+ writel(tcon, &pwm->tcon);
+
+ return 0;
+}
+
+int pwm_init(int pwm_id, int div, int invert)
+{
+ u32 val;
+ const struct s3c_timer *pwm =
+ (struct s3c_timer *)s3c64xx_get_base_timer();
+ unsigned long timer_rate_hz;
+ unsigned int offset, prescaler;
+
+ /*
+ * Timer Freq(HZ) =
+ * PWM_CLK / { (prescaler_value + 1) * (divider_value) }
+ */
+
+ val = readl(&pwm->tcfg0);
+ if (pwm_id < 2) {
+ prescaler = PRESCALER_0;
+ val &= ~0xff;
+ val |= (prescaler & 0xff);
+ } else {
+ prescaler = PRESCALER_1;
+ val &= ~(0xff << 8);
+ val |= (prescaler & 0xff) << 8;
+ }
+ writel(val, &pwm->tcfg0);
+ val = readl(&pwm->tcfg1);
+ val &= ~(0xf << MUX_DIV_SHIFT(pwm_id));
+ val |= (div & 0xf) << MUX_DIV_SHIFT(pwm_id);
+ writel(val, &pwm->tcfg1);
+
+ timer_rate_hz = get_PCLK() / ((prescaler + 1) *
+ (div + 1));
+
+ timer_rate_hz = timer_rate_hz / CONFIG_SYS_HZ;
+
+ /* set count value */
+ offset = pwm_id * 3;
+ writel(timer_rate_hz, &pwm->tcntb0 + offset);
+
+ val = readl(&pwm->tcon) & ~(0xf << TCON_OFFSET(pwm_id));
+ if (invert && (pwm_id < 4))
+ val |= TCON_INVERTER(pwm_id);
+ writel(val, &pwm->tcon);
+
+ pwm_enable(pwm_id);
+
+ return 0;
+}
diff --git a/arch/arm/include/asm/arch-s3c64xx/pwm.h b/arch/arm/include/asm/arch-s3c64xx/pwm.h
new file mode 100644
index 0000000..1e18f8c
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c64xx/pwm.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2012
+ * Zhong Hongbo <bocui107@gmail.com>
+ *
+ * based on arch/arm/include/asm/arch-s5pc1xx/pwm.h
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_PWM_H_
+#define __ASM_ARM_ARCH_PWM_H_
+
+#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */
+#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */
+
+/* Divider MUX */
+#define MUX_DIV_1 0 /* 1/1 period */
+#define MUX_DIV_2 1 /* 1/2 period */
+#define MUX_DIV_4 2 /* 1/4 period */
+#define MUX_DIV_8 3 /* 1/8 period */
+#define MUX_DIV_16 4 /* 1/16 period */
+
+#define MUX_DIV_SHIFT(x) (x * 4)
+
+#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2)
+
+#define TCON_START(x) (1 << TCON_OFFSET(x))
+#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1))
+#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2))
+#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3))
+#define TCON4_AUTO_RELOAD (1 << 22)
+
+#define TCFG1_DMA(x) (x << 20)
+
+#ifndef __ASSEMBLY__
+struct s3c_timer {
+ unsigned int tcfg0;
+ unsigned int tcfg1;
+ unsigned int tcon;
+ unsigned int tcntb0;
+ unsigned int tcmpb0;
+ unsigned int tcnto0;
+ unsigned int tcntb1;
+ unsigned int tcmpb1;
+ unsigned int tcnto1;
+ unsigned int tcntb2;
+ unsigned int res1;
+ unsigned int tcnto2;
+ unsigned int tcntb3;
+ unsigned int res2;
+ unsigned int tcnto3;
+ unsigned int tcntb4;
+ unsigned int tcnto4;
+ unsigned int tint_cstat;
+};
+#endif
+#endif
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index c6b41e8..1d7d2b6 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -31,6 +31,10 @@
#ifndef __S3C6400_H__
#define __S3C6400_H__
+#if defined(CONFIG_SYNC_MODE) && defined(CONFIG_S3C6400)
+#error CONFIG_SYNC_MODE unavailable on S3C6400, please, fix your configuration!
+#endif
+
#define S3C64XX_UART_CHANNELS 3
#define S3C64XX_SPI_CHANNELS 2
@@ -587,51 +591,6 @@
*/
#define ELFIN_TIMER_BASE 0x7F006000
-#define TCFG0_REG __REG(0x7F006000)
-#define TCFG1_REG __REG(0x7F006004)
-#define TCON_REG __REG(0x7F006008)
-#define TCNTB0_REG __REG(0x7F00600c)
-#define TCMPB0_REG __REG(0x7F006010)
-#define TCNTO0_REG __REG(0x7F006014)
-#define TCNTB1_REG __REG(0x7F006018)
-#define TCMPB1_REG __REG(0x7F00601c)
-#define TCNTO1_REG __REG(0x7F006020)
-#define TCNTB2_REG __REG(0x7F006024)
-#define TCMPB2_REG __REG(0x7F006028)
-#define TCNTO2_REG __REG(0x7F00602c)
-#define TCNTB3_REG __REG(0x7F006030)
-#define TCMPB3_REG __REG(0x7F006034)
-#define TCNTO3_REG __REG(0x7F006038)
-#define TCNTB4_REG __REG(0x7F00603c)
-#define TCNTO4_REG __REG(0x7F006040)
-
-/* Fields */
-#define fTCFG0_DZONE Fld(8, 16) /* the dead zone length (=timer 0) */
-#define fTCFG0_PRE1 Fld(8, 8) /* prescaler value for time 2,3,4 */
-#define fTCFG0_PRE0 Fld(8, 0) /* prescaler value for time 0,1 */
-#define fTCFG1_MUX4 Fld(4, 16)
-/* bits */
-#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE)
-#define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1)
-#define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0)
-#define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */
-#define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */
-#define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */
-#define COUNT_4_ON (TCON_4_ONOFF * 1)
-#define COUNT_4_OFF (TCON_4_ONOFF * 0)
-#define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */
-#define TIMER3_ATLOAD_ON (TCON_3_AUTO * 1)
-#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO)
-#define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */
-#define TIMER3_IVT_ON (TCON_3_INVERT * 1)
-#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT))
-#define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */
-#define TIMER3_MANUP (TCON_3_MAN*1)
-#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN))
-#define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */
-#define TIMER3_ON (TCON_3_ONOFF * 1)
-#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF))
-
#if defined(CONFIG_CLK_400_100_50)
#define STARTUP_AMDIV 400
#define STARTUP_MDIV 400
@@ -748,9 +707,6 @@
#define DMC_DDR_USER_CONFIG 1
#ifndef __ASSEMBLY__
-
-#include "s3c64x0.h"
-
static inline unsigned int s3c64xx_get_base_uart(void)
{
return ELFIN_UART_BASE;
@@ -760,6 +716,11 @@ static inline unsigned int s3c64xx_get_base_nand(void)
{
return ELFIN_NAND_BASE;
}
+
+static inline unsigned int s3c64xx_get_base_timer(void)
+{
+ return ELFIN_TIMER_BASE;
+}
#endif
#endif /*__S3C6400_H__*/
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h b/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
deleted file mode 100644
index 7add68c..0000000
--- a/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * (C) Copyright 2003
- * David M??ller ELSOFT AG Switzerland. d.mueller at elsoft.ch
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************
- * NAME : S3C64XX.h
- * Version : 31.3.2003
- *
- * common stuff for SAMSUNG S3C64XX SoC
- ************************************************/
-
-#ifndef __S3C64XX_H__
-#define __S3C64XX_H__
-
-#if defined(CONFIG_SYNC_MODE) && defined(CONFIG_S3C6400)
-#error CONFIG_SYNC_MODE unavailable on S3C6400, please, fix your configuration!
-#endif
-
-#include <asm/types.h>
-
-/* PWM TIMER (see manual chapter 10) */
-typedef struct {
- volatile u32 TCNTB;
- volatile u32 TCMPB;
- volatile u32 TCNTO;
-} s3c64xx_timer;
-
-typedef struct {
- volatile u32 TCFG0;
- volatile u32 TCFG1;
- volatile u32 TCON;
- s3c64xx_timer ch[4];
- volatile u32 TCNTB4;
- volatile u32 TCNTO4;
-} s3c64xx_timers;
-
-#endif /*__S3C64XX_H__*/
diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
index 47326d6..3642a5c 100644
--- a/include/configs/smdk6400.h
+++ b/include/configs/smdk6400.h
@@ -141,6 +141,9 @@
#define CONFIG_SYS_HZ 1000
+/* PWM */
+#define CONFIG_PWM 1
+
/*-----------------------------------------------------------------------
* Stack sizes
*
--
1.7.5.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 05/13] S3C64XX: reference s5p cpu time system for s3c64xx timer
2012-07-07 9:56 [U-Boot] S3c64xx: Switch all I/O to use readl/writel function Zhong Hongbo
` (3 preceding siblings ...)
2012-07-07 9:57 ` [U-Boot] [PATCH 04/13] S3C64XX: add pwm for s3c64xx support Zhong Hongbo
@ 2012-07-07 9:57 ` Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 06/13] S3C64xx: mov cpu_init.S to the board directory Zhong Hongbo
` (8 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Zhong Hongbo @ 2012-07-07 9:57 UTC (permalink / raw)
To: u-boot
From: Zhong Hongbo <bocui107@gmail.com>
The old s3c64xx timer is not work normal, Adopt s5p time design,
It work perfect.
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
---
arch/arm/cpu/arm1176/s3c64xx/timer.c | 195 ++++++++++++++++------------------
1 files changed, 94 insertions(+), 101 deletions(-)
diff --git a/arch/arm/cpu/arm1176/s3c64xx/timer.c b/arch/arm/cpu/arm1176/s3c64xx/timer.c
index f16a37b..7904d09 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/timer.c
+++ b/arch/arm/cpu/arm1176/s3c64xx/timer.c
@@ -1,23 +1,8 @@
/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ * Copyright (C) 2009 Samsung Electronics
+ * Heungjun Kim <riverful.kim@samsung.com>
+ * Inki Dae <inki.dae@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -39,64 +24,29 @@
*/
#include <common.h>
-#include <asm/proc-armv/ptrace.h>
+#include <asm/io.h>
#include <asm/arch/s3c6400.h>
-#include <div64.h>
-
-static ulong timer_load_val;
+#include <asm/arch/pwm.h>
+#include <pwm.h>
-#define PRESCALER 167
+DECLARE_GLOBAL_DATA_PTR;
-static s3c64xx_timers *s3c64xx_get_base_timers(void)
-{
- return (s3c64xx_timers *)ELFIN_TIMER_BASE;
-}
+static unsigned long get_current_tick(void);
/* macro to read the 16 bit timer */
-static inline ulong read_timer(void)
+static inline struct s3c_timer *s3c_get_base_timer(void)
{
- s3c64xx_timers *const timers = s3c64xx_get_base_timers();
-
- return timers->TCNTO4;
+ return (struct s3c_timer *)s3c64xx_get_base_timer();
}
-/* Internal tick units */
-/* Last decremneter snapshot */
-static unsigned long lastdec;
-/* Monotonic incrementing timer */
-static unsigned long long timestamp;
-
int timer_init(void)
{
- s3c64xx_timers *const timers = s3c64xx_get_base_timers();
-
- /* use PWM Timer 4 because it has no output */
- /*
- * We use the following scheme for the timer:
- * Prescaler is hard fixed at 167, divider at 1/4.
- * This gives at PCLK frequency 66MHz approx. 10us ticks
- * The timer is set to wrap after 100s, at 66MHz this obviously
- * happens after 10,000,000 ticks. A long variable can thus
- * keep values up to 40,000s, i.e., 11 hours. This should be
- * enough for most uses:-) Possible optimizations: select a
- * binary-friendly frequency, e.g., 1ms / 128. Also calculate
- * the prescaler automatically for other PCLK frequencies.
- */
- timers->TCFG0 = PRESCALER << 8;
- if (timer_load_val == 0) {
- timer_load_val = get_PCLK() / PRESCALER * (100 / 4); /* 100s */
- timers->TCFG1 = (timers->TCFG1 & ~0xf0000) | 0x20000;
- }
-
- /* load value for 10 ms timeout */
- lastdec = timers->TCNTB4 = timer_load_val;
- /* auto load, manual update of Timer 4 */
- timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO |
- TCON_4_UPDATE;
+ /* PWM Timer 4 */
+ pwm_init(4, MUX_DIV_2, 0);
+ pwm_config(4, 0, 0);
+ pwm_enable(4);
- /* auto load, start Timer 4 */
- timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | COUNT_4_ON;
- timestamp = 0;
+ reset_timer_masked();
return 0;
}
@@ -104,57 +54,100 @@ int timer_init(void)
/*
* timer without interrupts
*/
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
+unsigned long get_timer(unsigned long base)
{
- ulong now = read_timer();
+ return get_timer_masked() - base;
+}
- if (lastdec >= now) {
- /* normal mode */
- timestamp += lastdec - now;
+/* delay x useconds */
+void __udelay(unsigned long usec)
+{
+ struct s3c_timer *const timer = s3c_get_base_timer();
+ unsigned long tmo, tmp, count_value;
+
+ count_value = readl(&timer->tcntb4);
+
+ if (usec >= 1000) {
+ /*
+ * if "big" number, spread normalization
+ * to seconds
+ * 1. start to normalize for usec to ticks per sec
+ * 2. find number of "ticks" to wait to achieve target
+ * 3. finish normalize.
+ */
+ tmo = usec / 1000;
+ tmo *= (CONFIG_SYS_HZ * count_value);
+ tmo /= 1000;
} else {
- /* we have an overflow ... */
- timestamp += lastdec + timer_load_val - now;
+ /* else small number, don't kill it prior to HZ multiply */
+ tmo = usec * CONFIG_SYS_HZ * count_value;
+ tmo /= (1000 * 1000);
}
- lastdec = now;
- return timestamp;
+ /* get current timestamp */
+ tmp = get_current_tick();
+
+ /* if setting this fordward will roll time stamp */
+ /* reset "advancing" timestamp to 0, set lastinc value */
+ /* else, set advancing stamp wake up time */
+ if ((tmo + tmp + 1) < tmp)
+ reset_timer_masked();
+ else
+ tmo += tmp;
+
+ /* loop till event */
+ while (get_current_tick() < tmo)
+
+ ; /* nop */
}
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
+void reset_timer_masked(void)
{
- /* We overrun in 100s */
- return (ulong)(timer_load_val / 100);
+ struct s3c_timer *const timer = s3c_get_base_timer();
+
+ /* reset time */
+ gd->lastinc = readl(&timer->tcnto4);
+ gd->tbl = 0;
}
-ulong get_timer_masked(void)
+unsigned long get_timer_masked(void)
{
- unsigned long long res = get_ticks();
- do_div (res, (timer_load_val / (100 * CONFIG_SYS_HZ)));
- return res;
+ struct s3c_timer *const timer = s3c_get_base_timer();
+ unsigned long count_value = readl(&timer->tcntb4);
+
+ return get_current_tick() / count_value;
}
-ulong get_timer(ulong base)
+static unsigned long get_current_tick(void)
{
- return get_timer_masked() - base;
+ struct s3c_timer *const timer = s3c_get_base_timer();
+ unsigned long now = readl(&timer->tcnto4);
+ unsigned long count_value = readl(&timer->tcntb4);
+
+ if (gd->lastinc >= now)
+ gd->tbl += gd->lastinc - now;
+ else
+ gd->tbl += gd->lastinc + count_value - now;
+
+ gd->lastinc = now;
+
+ return gd->tbl;
}
-void __udelay(unsigned long usec)
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
{
- unsigned long long tmp;
- ulong tmo;
-
- tmo = (usec + 9) / 10;
- tmp = get_ticks() + tmo; /* get current timestamp */
+ return get_timer(0);
+}
- while (get_ticks() < tmp)/* loop till event */
- /*NOP*/;
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+unsigned long get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
}
--
1.7.5.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 06/13] S3C64xx: mov cpu_init.S to the board directory
2012-07-07 9:56 [U-Boot] S3c64xx: Switch all I/O to use readl/writel function Zhong Hongbo
` (4 preceding siblings ...)
2012-07-07 9:57 ` [U-Boot] [PATCH 05/13] S3C64XX: reference s5p cpu time system for s3c64xx timer Zhong Hongbo
@ 2012-07-07 9:57 ` Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 07/13] S3C6400: Delete nand_spl for S3C6400 Zhong Hongbo
` (7 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Zhong Hongbo @ 2012-07-07 9:57 UTC (permalink / raw)
To: u-boot
From: Zhong Hongbo <bocui107@gmail.com>
It just only do the memory init. The memory depend on the
design of board.
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
---
arch/arm/cpu/arm1176/s3c64xx/Makefile | 2 +-
arch/arm/cpu/arm1176/s3c64xx/cpu_init.S | 135 -------------------------------
board/samsung/smdk6400/Makefile | 2 +-
board/samsung/smdk6400/mem_init.S | 135 +++++++++++++++++++++++++++++++
4 files changed, 137 insertions(+), 137 deletions(-)
delete mode 100644 arch/arm/cpu/arm1176/s3c64xx/cpu_init.S
create mode 100644 board/samsung/smdk6400/mem_init.S
diff --git a/arch/arm/cpu/arm1176/s3c64xx/Makefile b/arch/arm/cpu/arm1176/s3c64xx/Makefile
index 966663f..2f37431 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/Makefile
+++ b/arch/arm/cpu/arm1176/s3c64xx/Makefile
@@ -30,7 +30,7 @@ LIB = $(obj)lib$(SOC).o
SOBJS = reset.o
-COBJS-$(CONFIG_S3C6400) += cpu_init.o speed.o
+COBJS-$(CONFIG_S3C64XX) += speed.o
COBJS-y += timer.o
COBJS-$(CONFIG_PWM) += pwm.o
diff --git a/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S b/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S
deleted file mode 100644
index df88cba..0000000
--- a/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400
- *
- * Copyright (C) 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/s3c6400.h>
-
- .globl mem_ctrl_asm_init
-mem_ctrl_asm_init:
- /* DMC1 base address 0x7e001000 */
- ldr r0, =ELFIN_DMC1_BASE
-
- ldr r1, =0x4
- str r1, [r0, #INDEX_DMC_MEMC_CMD]
-
- ldr r1, =DMC_DDR_REFRESH_PRD
- str r1, [r0, #INDEX_DMC_REFRESH_PRD]
-
- ldr r1, =DMC_DDR_CAS_LATENCY
- str r1, [r0, #INDEX_DMC_CAS_LATENCY]
-
- ldr r1, =DMC_DDR_t_DQSS
- str r1, [r0, #INDEX_DMC_T_DQSS]
-
- ldr r1, =DMC_DDR_t_MRD
- str r1, [r0, #INDEX_DMC_T_MRD]
-
- ldr r1, =DMC_DDR_t_RAS
- str r1, [r0, #INDEX_DMC_T_RAS]
-
- ldr r1, =DMC_DDR_t_RC
- str r1, [r0, #INDEX_DMC_T_RC]
-
- ldr r1, =DMC_DDR_t_RCD
- ldr r2, =DMC_DDR_schedule_RCD
- orr r1, r1, r2
- str r1, [r0, #INDEX_DMC_T_RCD]
-
- ldr r1, =DMC_DDR_t_RFC
- ldr r2, =DMC_DDR_schedule_RFC
- orr r1, r1, r2
- str r1, [r0, #INDEX_DMC_T_RFC]
-
- ldr r1, =DMC_DDR_t_RP
- ldr r2, =DMC_DDR_schedule_RP
- orr r1, r1, r2
- str r1, [r0, #INDEX_DMC_T_RP]
-
- ldr r1, =DMC_DDR_t_RRD
- str r1, [r0, #INDEX_DMC_T_RRD]
-
- ldr r1, =DMC_DDR_t_WR
- str r1, [r0, #INDEX_DMC_T_WR]
-
- ldr r1, =DMC_DDR_t_WTR
- str r1, [r0, #INDEX_DMC_T_WTR]
-
- ldr r1, =DMC_DDR_t_XP
- str r1, [r0, #INDEX_DMC_T_XP]
-
- ldr r1, =DMC_DDR_t_XSR
- str r1, [r0, #INDEX_DMC_T_XSR]
-
- ldr r1, =DMC_DDR_t_ESR
- str r1, [r0, #INDEX_DMC_T_ESR]
-
- ldr r1, =DMC1_MEM_CFG
- str r1, [r0, #INDEX_DMC_MEMORY_CFG]
-
- ldr r1, =DMC1_MEM_CFG2
- str r1, [r0, #INDEX_DMC_MEMORY_CFG2]
-
- ldr r1, =DMC1_CHIP0_CFG
- str r1, [r0, #INDEX_DMC_CHIP_0_CFG]
-
- ldr r1, =DMC_DDR_32_CFG
- str r1, [r0, #INDEX_DMC_USER_CONFIG]
-
- /* DMC0 DDR Chip 0 configuration direct command reg */
- ldr r1, =DMC_NOP0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
- /* Precharge All */
- ldr r1, =DMC_PA0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
- /* Auto Refresh 2 time */
- ldr r1, =DMC_AR0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
- /* MRS */
- ldr r1, =DMC_mDDR_EMR0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
- /* Mode Reg */
- ldr r1, =DMC_mDDR_MR0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
- /* Enable DMC1 */
- mov r1, #0x0
- str r1, [r0, #INDEX_DMC_MEMC_CMD]
-
-check_dmc1_ready:
- ldr r1, [r0, #INDEX_DMC_MEMC_STATUS]
- mov r2, #0x3
- and r1, r1, r2
- cmp r1, #0x1
- bne check_dmc1_ready
- nop
-
- mov pc, lr
-
- .ltorg
diff --git a/board/samsung/smdk6400/Makefile b/board/samsung/smdk6400/Makefile
index 0d3e63b..645c8e2 100644
--- a/board/samsung/smdk6400/Makefile
+++ b/board/samsung/smdk6400/Makefile
@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y := smdk6400.o
-SOBJS := lowlevel_init.o
+SOBJS := lowlevel_init.o mem_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/samsung/smdk6400/mem_init.S b/board/samsung/smdk6400/mem_init.S
new file mode 100644
index 0000000..df88cba
--- /dev/null
+++ b/board/samsung/smdk6400/mem_init.S
@@ -0,0 +1,135 @@
+/*
+ * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400
+ *
+ * Copyright (C) 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/s3c6400.h>
+
+ .globl mem_ctrl_asm_init
+mem_ctrl_asm_init:
+ /* DMC1 base address 0x7e001000 */
+ ldr r0, =ELFIN_DMC1_BASE
+
+ ldr r1, =0x4
+ str r1, [r0, #INDEX_DMC_MEMC_CMD]
+
+ ldr r1, =DMC_DDR_REFRESH_PRD
+ str r1, [r0, #INDEX_DMC_REFRESH_PRD]
+
+ ldr r1, =DMC_DDR_CAS_LATENCY
+ str r1, [r0, #INDEX_DMC_CAS_LATENCY]
+
+ ldr r1, =DMC_DDR_t_DQSS
+ str r1, [r0, #INDEX_DMC_T_DQSS]
+
+ ldr r1, =DMC_DDR_t_MRD
+ str r1, [r0, #INDEX_DMC_T_MRD]
+
+ ldr r1, =DMC_DDR_t_RAS
+ str r1, [r0, #INDEX_DMC_T_RAS]
+
+ ldr r1, =DMC_DDR_t_RC
+ str r1, [r0, #INDEX_DMC_T_RC]
+
+ ldr r1, =DMC_DDR_t_RCD
+ ldr r2, =DMC_DDR_schedule_RCD
+ orr r1, r1, r2
+ str r1, [r0, #INDEX_DMC_T_RCD]
+
+ ldr r1, =DMC_DDR_t_RFC
+ ldr r2, =DMC_DDR_schedule_RFC
+ orr r1, r1, r2
+ str r1, [r0, #INDEX_DMC_T_RFC]
+
+ ldr r1, =DMC_DDR_t_RP
+ ldr r2, =DMC_DDR_schedule_RP
+ orr r1, r1, r2
+ str r1, [r0, #INDEX_DMC_T_RP]
+
+ ldr r1, =DMC_DDR_t_RRD
+ str r1, [r0, #INDEX_DMC_T_RRD]
+
+ ldr r1, =DMC_DDR_t_WR
+ str r1, [r0, #INDEX_DMC_T_WR]
+
+ ldr r1, =DMC_DDR_t_WTR
+ str r1, [r0, #INDEX_DMC_T_WTR]
+
+ ldr r1, =DMC_DDR_t_XP
+ str r1, [r0, #INDEX_DMC_T_XP]
+
+ ldr r1, =DMC_DDR_t_XSR
+ str r1, [r0, #INDEX_DMC_T_XSR]
+
+ ldr r1, =DMC_DDR_t_ESR
+ str r1, [r0, #INDEX_DMC_T_ESR]
+
+ ldr r1, =DMC1_MEM_CFG
+ str r1, [r0, #INDEX_DMC_MEMORY_CFG]
+
+ ldr r1, =DMC1_MEM_CFG2
+ str r1, [r0, #INDEX_DMC_MEMORY_CFG2]
+
+ ldr r1, =DMC1_CHIP0_CFG
+ str r1, [r0, #INDEX_DMC_CHIP_0_CFG]
+
+ ldr r1, =DMC_DDR_32_CFG
+ str r1, [r0, #INDEX_DMC_USER_CONFIG]
+
+ /* DMC0 DDR Chip 0 configuration direct command reg */
+ ldr r1, =DMC_NOP0
+ str r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+ /* Precharge All */
+ ldr r1, =DMC_PA0
+ str r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+ /* Auto Refresh 2 time */
+ ldr r1, =DMC_AR0
+ str r1, [r0, #INDEX_DMC_DIRECT_CMD]
+ str r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+ /* MRS */
+ ldr r1, =DMC_mDDR_EMR0
+ str r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+ /* Mode Reg */
+ ldr r1, =DMC_mDDR_MR0
+ str r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+ /* Enable DMC1 */
+ mov r1, #0x0
+ str r1, [r0, #INDEX_DMC_MEMC_CMD]
+
+check_dmc1_ready:
+ ldr r1, [r0, #INDEX_DMC_MEMC_STATUS]
+ mov r2, #0x3
+ and r1, r1, r2
+ cmp r1, #0x1
+ bne check_dmc1_ready
+ nop
+
+ mov pc, lr
+
+ .ltorg
--
1.7.5.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 07/13] S3C6400: Delete nand_spl for S3C6400
2012-07-07 9:56 [U-Boot] S3c64xx: Switch all I/O to use readl/writel function Zhong Hongbo
` (5 preceding siblings ...)
2012-07-07 9:57 ` [U-Boot] [PATCH 06/13] S3C64xx: mov cpu_init.S to the board directory Zhong Hongbo
@ 2012-07-07 9:57 ` Zhong Hongbo
2012-07-09 22:21 ` Scott Wood
2012-07-07 9:57 ` [U-Boot] [PATCH 08/13] S3C6400: Adopt SPL framwork to support spl for nand flash Zhong Hongbo
` (6 subsequent siblings)
13 siblings, 1 reply; 20+ messages in thread
From: Zhong Hongbo @ 2012-07-07 9:57 UTC (permalink / raw)
To: u-boot
From: Zhong Hongbo <bocui107@gmail.com>
The old spl use nand_spl directory file to support
nand flash boot. We will adopt the new SPL framework
to implement it.
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
---
board/samsung/smdk6400/config.mk | 28 -------
boards.cfg | 4 +-
include/configs/smdk6400.h | 4 +-
nand_spl/board/samsung/smdk6400/Makefile | 117 ----------------------------
nand_spl/board/samsung/smdk6400/config.mk | 40 ----------
nand_spl/board/samsung/smdk6400/u-boot.lds | 78 ------------------
6 files changed, 4 insertions(+), 267 deletions(-)
delete mode 100644 board/samsung/smdk6400/config.mk
delete mode 100644 nand_spl/board/samsung/smdk6400/Makefile
delete mode 100644 nand_spl/board/samsung/smdk6400/config.mk
delete mode 100644 nand_spl/board/samsung/smdk6400/u-boot.lds
diff --git a/board/samsung/smdk6400/config.mk b/board/samsung/smdk6400/config.mk
deleted file mode 100644
index 93a1a0d..0000000
--- a/board/samsung/smdk6400/config.mk
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
-#
-# SAMSUNG SMDK6400 board with mDirac3 (ARM1176) cpu
-#
-# see http://www.samsung.com/ for more information on SAMSUNG
-
-# On SMDK6400 we use the 64 MB SDRAM bank at
-#
-# 0x50000000 to 0x58000000
-#
-# Linux-Kernel is expected to be at 0x50008000, entry 0x50008000
-#
-# we load ourselves to 0x57e00000 without MMU
-# with MMU, load address is changed to 0xc7e00000
-#
-# download area is 0x5000c000
-
-ifndef CONFIG_NAND_SPL
-CONFIG_SYS_TEXT_BASE = $(CONFIG_RAM_TEXT)
-else
-CONFIG_SYS_TEXT_BASE = 0
-endif
diff --git a/boards.cfg b/boards.cfg
index a6ca01f..cc18700 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -47,8 +47,8 @@ flea3 arm arm1136 - CarMedi
mx35pdk arm arm1136 - freescale mx35
apollon arm arm1136 apollon - omap24xx
omap2420h4 arm arm1136 - ti omap24xx
-smdk6400 arm arm1176 smdk6400 samsung s3c64xx smdk6400:NAND_U_BOOT,RAM_TEXT=0xc7e00000
-smdk6400_nousb arm arm1176 smdk6400 samsung s3c64xx smdk6400:NAND_U_BOOT,RAM_TEXT=0x57e00000
+smdk6400 arm arm1176 smdk6400 samsung s3c64xx smdk6400:SYS_TEXT_BASE=0x57e00000
+smdk6400_nousb arm arm1176 smdk6400 samsung s3c64xx smdk6400:SYS_TEXT_BASE=0xc7e00000
tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
integratorap_cm720t arm arm720t integrator armltd - integratorap:CM720T
integratorap_cm920t arm arm920t integrator armltd - integratorap:CM920T
diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
index 3642a5c..b38d015 100644
--- a/include/configs/smdk6400.h
+++ b/include/configs/smdk6400.h
@@ -54,7 +54,7 @@
/* input clock of PLL: SMDK6400 has 12MHz input clock */
#define CONFIG_SYS_CLK_FREQ 12000000
-#if !defined(CONFIG_NAND_U_BOOT) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000)
+#if !defined(CONFIG_SPL_BUILD) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000)
#define CONFIG_ENABLE_MMU
#endif
@@ -113,7 +113,6 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
#define CONFIG_BOOTDELAY 3
@@ -288,6 +287,7 @@
#if !defined(CONFIG_ENABLE_MMU)
#define CONFIG_CMD_USB 1
+#define CONFIG_CMD_EXT2
#define CONFIG_USB_S3C64XX
#define CONFIG_USB_OHCI_NEW 1
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x74300000
diff --git a/nand_spl/board/samsung/smdk6400/Makefile b/nand_spl/board/samsung/smdk6400/Makefile
deleted file mode 100644
index c9e75ba..0000000
--- a/nand_spl/board/samsung/smdk6400/Makefile
+++ /dev/null
@@ -1,117 +0,0 @@
-#
-# (C) Copyright 2006-2007
-# Stefan Roese, DENX Software Engineering, sr at denx.de.
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-CONFIG_NAND_SPL = y
-
-include $(TOPDIR)/config.mk
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
- $(LDFLAGS_FINAL) -gc-sections
-AFLAGS += -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_NAND_SPL -ffunction-sections
-
-SOBJS = start.o cpu_init.o lowlevel_init.o
-COBJS = nand_boot.o nand_ecc.o s3c64xx.o smdk6400_nand_spl.o nand_base.o
-
-SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $(nandobj)u-boot-spl
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-# from cpu directory
-$(obj)start.S:
- @rm -f $@
- @ln -s $(TOPDIR)/arch/arm/cpu/arm1176/start.S $@
-
-# from SoC directory
-$(obj)cpu_init.S:
- @rm -f $@
- @ln -s $(TOPDIR)/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S $@
-
-# from board directory
-$(obj)lowlevel_init.S:
- @rm -f $@
- @ln -s $(TOPDIR)/board/samsung/smdk6400/lowlevel_init.S $@
-
-# from nand_spl directory
-$(obj)nand_boot.c:
- @rm -f $@
- @ln -s $(TOPDIR)/nand_spl/nand_boot.c $@
-
-# from drivers/mtd/nand directory
-$(obj)nand_ecc.c:
- @rm -f $@
- @ln -s $(TOPDIR)/drivers/mtd/nand/nand_ecc.c $@
-
-$(obj)s3c64xx.c:
- @rm -f $@
- @ln -s $(TOPDIR)/drivers/mtd/nand/s3c64xx.c $@
-
-$(obj)smdk6400_nand_spl.c:
- @rm -f $@
- @ln -s $(TOPDIR)/board/samsung/smdk6400/smdk6400_nand_spl.c $@
-
-$(obj)nand_base.c:
- @rm -f $@
- @ln -s $(TOPDIR)/drivers/mtd/nand/nand_base.c $@
-#########################################################################
-
-$(obj)%.o: $(obj)%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(obj)%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/nand_spl/board/samsung/smdk6400/config.mk b/nand_spl/board/samsung/smdk6400/config.mk
deleted file mode 100644
index 8bea498..0000000
--- a/nand_spl/board/samsung/smdk6400/config.mk
+++ /dev/null
@@ -1,40 +0,0 @@
-#
-# (C) Copyright 2006
-# Stefan Roese, DENX Software Engineering, sr at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-#
-# Samsung S3C64xx Reference Platform (smdk6400) board
-
-# CONFIG_SYS_TEXT_BASE for SPL:
-#
-# On S3C64xx platforms the SPL is located in SRAM@0.
-#
-# CONFIG_SYS_TEXT_BASE = 0
-
-include $(TOPDIR)/board/$(BOARDDIR)/config.mk
-
-# PAD_TO used to generate a 4kByte binary needed for the combined image
-# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 4096
-PAD_TO := $(shell expr $$[$(CONFIG_SYS_TEXT_BASE) + 4096])
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
diff --git a/nand_spl/board/samsung/smdk6400/u-boot.lds b/nand_spl/board/samsung/smdk6400/u-boot.lds
deleted file mode 100644
index 567f635..0000000
--- a/nand_spl/board/samsung/smdk6400/u-boot.lds
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- start.o (.text)
- cpu_init.o (.text)
- nand_boot.o (.text)
-
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end__ = .;
- }
-}
--
1.7.5.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 08/13] S3C6400: Adopt SPL framwork to support spl for nand flash
2012-07-07 9:56 [U-Boot] S3c64xx: Switch all I/O to use readl/writel function Zhong Hongbo
` (6 preceding siblings ...)
2012-07-07 9:57 ` [U-Boot] [PATCH 07/13] S3C6400: Delete nand_spl for S3C6400 Zhong Hongbo
@ 2012-07-07 9:57 ` Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 09/13] S3C64XX: Change SROM init to use read/write operation Zhong Hongbo
` (5 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Zhong Hongbo @ 2012-07-07 9:57 UTC (permalink / raw)
To: u-boot
From: Zhong Hongbo <bocui107@gmail.com>
Adopt the new SPL framework to implement the SPL booting of
the nand flash for S3C6400.
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
---
arch/arm/cpu/arm1176/start.S | 17 +---
board/samsung/smdk6400/Makefile | 29 +++++-
board/samsung/smdk6400/lowlevel_init.S | 4 +-
board/samsung/smdk6400/smdk6400_nand_spl.c | 61 ++++++++++--
board/samsung/smdk6400/tools/mksmdk6400_image.c | 117 +++++++++++++++++++++++
drivers/mtd/nand/s3c64xx.c | 4 +-
include/configs/smdk6400.h | 34 ++-----
7 files changed, 211 insertions(+), 55 deletions(-)
create mode 100644 board/samsung/smdk6400/tools/mksmdk6400_image.c
diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
index 848144a..de2cb39 100644
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -51,7 +51,7 @@
.globl _start
_start: b reset
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
@@ -164,7 +164,7 @@ cpu_init_crit:
* When booting from NAND - it has definitely been a reset, so, no need
* to flush caches and disable the MMU
*/
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
/*
* flush v4 I/D caches
*/
@@ -252,6 +252,7 @@ stack_setup:
adr r0, _start
cmp r0, r6
+ mov r9, #0
beq clear_bss /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _bss_start_ofs
@@ -356,21 +357,14 @@ clbss_l:str r2, [r0] /* clear loop... */
cmp r0, r1
bne clbss_l
-#ifndef CONFIG_NAND_SPL
bl coloured_LED_init
bl red_led_on
#endif
-#endif
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
-#ifdef CONFIG_NAND_SPL
- ldr pc, _nand_boot
-
-_nand_boot: .word nand_boot
-#else
ldr r0, _board_init_r_ofs
adr r1, _start
add lr, r0, r1
@@ -383,7 +377,6 @@ _nand_boot: .word nand_boot
_board_init_r_ofs:
.word board_init_r - _start
-#endif
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
@@ -397,7 +390,7 @@ _mmu_table_base:
.word mmu_table
#endif
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
/*
* we assume that cache operation is done before. (eg. cleanup_before_linux())
* actually, we don't need to do anything about cache if not use d-cache in
@@ -575,4 +568,4 @@ fiq:
get_bad_stack
bad_save_user_regs
bl do_fiq
-#endif /* CONFIG_NAND_SPL */
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/samsung/smdk6400/Makefile b/board/samsung/smdk6400/Makefile
index 645c8e2..f7fa667 100644
--- a/board/samsung/smdk6400/Makefile
+++ b/board/samsung/smdk6400/Makefile
@@ -28,15 +28,34 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
+ifndef CONFIG_SPL_BUILD
COBJS-y := smdk6400.o
+endif
+
SOBJS := lowlevel_init.o mem_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS-y))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+ifdef CONFIG_SPL_BUILD
+COBJS-y += smdk6400_nand_spl.o
+endif
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
+
+ALL := $(obj).depend $(LIB)
+
+ifdef CONFIG_SPL_BUILD
+ALL += $(OBJTREE)/tools/mk$(BOARD)spl
+endif
+
+all: $(ALL)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
-$(LIB): $(obj).depend $(SOBJS) $(OBJS)
- $(call cmd_link_o_target, $(SOBJS) $(OBJS))
+ifdef CONFIG_SPL_BUILD
+$(OBJTREE)/tools/mk$(BOARD)spl: tools/mksmdk6400_image.c
+ $(HOSTCC) tools/mksmdk6400_image.c -o $(OBJTREE)/tools/mk$(BOARD)spl
+endif
#########################################################################
diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S
index 1142be1..81e5c6a 100644
--- a/board/samsung/smdk6400/lowlevel_init.S
+++ b/board/samsung/smdk6400/lowlevel_init.S
@@ -86,7 +86,7 @@ lowlevel_init:
/* init system clock */
bl system_clock_init
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
/* for UART */
bl uart_asm_init
#endif
@@ -243,7 +243,7 @@ wait_for_async:
mov pc, lr
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
/*
* uart_asm_init: Initialize UART's pins
*/
diff --git a/board/samsung/smdk6400/smdk6400_nand_spl.c b/board/samsung/smdk6400/smdk6400_nand_spl.c
index a023284..34649a2 100644
--- a/board/samsung/smdk6400/smdk6400_nand_spl.c
+++ b/board/samsung/smdk6400/smdk6400_nand_spl.c
@@ -1,13 +1,6 @@
/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ * Copyright (C) 2012
+ * Zhong Hongbo <bocui107@gmail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -29,9 +22,55 @@
*/
#include <common.h>
+#include <config.h>
+#include <nand.h>
void board_init_f(unsigned long bootflag)
{
- relocate_code(CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL,
- CONFIG_SYS_TEXT_BASE);
+ /*
+ * We call relocate_code() with relocation target same as the
+ * CONFIG_SYS_SPL_TEXT_BASE. This will result in relocation getting
+ * skipped. Instead, only .bss initialization will happen. That's
+ * all we need
+ */
+ relocate_code(CONFIG_SPL_STACK, NULL, CONFIG_SPL_TEXT_BASE);
+}
+
+void board_init_r(gd_t *id, ulong dest_addr)
+{
+ __attribute__((noreturn)) void (*uboot)(void);
+
+ spl_nand_copy();
+ /*
+ * Jump to U-Boot image
+ */
+ uboot = (void *)CONFIG_SYS_UBOOT_BASE;
+ (*uboot)();
+ /* Never returns Here */
+}
+
+void spl_nand_copy(void)
+{
+ /*
+ * Init board specific nand support
+ */
+ nand_init();
+ /*
+ * Load U-Boot image from NAND into RAM
+ */
+ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+ CONFIG_SYS_NAND_U_BOOT_SIZE,
+ (void *)CONFIG_SYS_UBOOT_BASE);
+
+#ifdef CONFIG_NAND_ENV_DST
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (void *)CONFIG_NAND_ENV_DST);
+
+#ifdef CONFIG_ENV_OFFSET_REDUND
+ nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
+ (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
+#endif
+#endif
+
+ nand_deselect();
}
diff --git a/board/samsung/smdk6400/tools/mksmdk6400_image.c b/board/samsung/smdk6400/tools/mksmdk6400_image.c
new file mode 100644
index 0000000..1a51913
--- /dev/null
+++ b/board/samsung/smdk6400/tools/mksmdk6400_image.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <errno.h>
+#include <string.h>
+#include <sys/stat.h>
+
+#define CHECKSUM_OFFSET (14*1024-4)
+#define BUFSIZE (16*1024)
+#define FILE_PERM (S_IRUSR | S_IWUSR | S_IRGRP \
+ | S_IWGRP | S_IROTH | S_IWOTH)
+/*
+* Requirement:
+* IROM code reads first 14K bytes from boot device.
+* It then calculates the checksum of 14K-4 bytes and compare with data at
+* 14K-4 offset.
+*
+* This function takes two filenames:
+* IN "u-boot-spl.bin" and
+* OUT "u-boot-mmc-spl.bin" as filenames.
+* It reads the "u-boot-spl.bin" in 16K buffer.
+* It calculates checksum of 14K-4 Bytes and stores at 14K-4 offset in buffer.
+* It writes the buffer to "u-boot-mmc-spl.bin" file.
+*/
+
+int main(int argc, char **argv)
+{
+ int i, len;
+ unsigned char buffer[BUFSIZE] = {0};
+ int ifd, ofd;
+ unsigned int checksum = 0, count;
+
+ if (argc != 3) {
+ printf(" %d Wrong number of arguments\n", argc);
+ exit(EXIT_FAILURE);
+ }
+
+ ifd = open(argv[1], O_RDONLY);
+ if (ifd < 0) {
+ fprintf(stderr, "%s: Can't open %s: %s\n",
+ argv[0], argv[1], strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+
+ ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM);
+ if (ifd < 0) {
+ fprintf(stderr, "%s: Can't open %s: %s\n",
+ argv[0], argv[2], strerror(errno));
+ if (ifd)
+ close(ifd);
+ exit(EXIT_FAILURE);
+ }
+
+ len = lseek(ifd, 0, SEEK_END);
+ lseek(ifd, 0, SEEK_SET);
+
+ count = (len < CHECKSUM_OFFSET) ? len : CHECKSUM_OFFSET;
+
+ if (read(ifd, buffer, count) != count) {
+ fprintf(stderr, "%s: Can't read %s: %s\n",
+ argv[0], argv[1], strerror(errno));
+
+ if (ifd)
+ close(ifd);
+ if (ofd)
+ close(ofd);
+
+ exit(EXIT_FAILURE);
+ }
+
+ for (i = 0, checksum = 0; i < CHECKSUM_OFFSET; i++)
+ checksum += buffer[i];
+
+ memcpy(&buffer[CHECKSUM_OFFSET], &checksum, sizeof(checksum));
+
+ if (write(ofd, buffer, BUFSIZE) != BUFSIZE) {
+ fprintf(stderr, "%s: Can't write %s: %s\n",
+ argv[0], argv[2], strerror(errno));
+
+ if (ifd)
+ close(ifd);
+ if (ofd)
+ close(ofd);
+
+ exit(EXIT_FAILURE);
+ }
+
+ if (ifd)
+ close(ifd);
+ if (ofd)
+ close(ofd);
+
+ return EXIT_SUCCESS;
+}
diff --git a/drivers/mtd/nand/s3c64xx.c b/drivers/mtd/nand/s3c64xx.c
index 1d6bd67..58de00a 100644
--- a/drivers/mtd/nand/s3c64xx.c
+++ b/drivers/mtd/nand/s3c64xx.c
@@ -39,7 +39,7 @@
#define MAX_CHIPS 2
static int nand_cs[MAX_CHIPS] = {0, 1};
-#ifdef CONFIG_NAND_SPL
+#ifdef CONFIG_SPL_BUILD
#define printf(arg...) do {} while (0)
#endif
@@ -285,7 +285,7 @@ int board_nand_init(struct nand_chip *nand)
nand->dev_ready = s3c_nand_device_ready;
nand->select_chip = s3c_nand_select_chip;
nand->options = 0;
-#ifdef CONFIG_NAND_SPL
+#ifdef CONFIG_SPL_BUILD
nand->read_byte = nand_read_byte;
nand->write_buf = nand_write_buf;
nand->read_buf = nand_read_buf;
diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
index b38d015..2816f93 100644
--- a/include/configs/smdk6400.h
+++ b/include/configs/smdk6400.h
@@ -107,9 +107,6 @@
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_NAND
-#if defined(CONFIG_BOOT_ONENAND)
-#define CONFIG_CMD_ONENAND
-#endif
#define CONFIG_CMD_PING
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
@@ -237,11 +234,10 @@
#define CONFIG_SYS_NAND_YAFFS_WRITE 1 /* support yaffs write */
#define CONFIG_SYS_NAND_BBT_2NDPAGE 1 /* bad-block markers in 1st and 2nd pages */
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_PHY_UBOOT_BASE /* NUB load-addr */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* NUB start-addr */
-
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (4 * 1024) /* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (252 * 1024) /* Size of RAM U-Boot image */
+/* Offset to RAM U-Boot image */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 * 1024)
+/* Size of RAM U-Boot image */
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (252 * 1024)
/* NAND chip page size */
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
@@ -265,26 +261,18 @@
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63}
-/* Boot configuration (define only one of next 3) */
-#define CONFIG_BOOT_NAND
-/* None of these are currently implemented. Left from the original Samsung
- * version for reference
-#define CONFIG_BOOT_NOR
-#define CONFIG_BOOT_MOVINAND
-#define CONFIG_BOOT_ONENAND
-*/
+#define CONFIG_SPL
+#define CONFIG_SPL_NAND
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_NAND
+#define CONFIG_SPL_TEXT_BASE 0xd0020000
+#define CONFIG_SPL_STACK CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_MALLOC_LEN
#define CONFIG_NAND_S3C64XX
-/* Unimplemented or unsupported. See comment above.
-#define CONFIG_ONENAND
-#define CONFIG_MOVINAND
-*/
-
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
/* Settings as above boot configuration */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_BOOTARGS "console=ttySAC,115200"
-
#if !defined(CONFIG_ENABLE_MMU)
#define CONFIG_CMD_USB 1
#define CONFIG_CMD_EXT2
--
1.7.5.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 09/13] S3C64XX: Change SROM init to use read/write operation
2012-07-07 9:56 [U-Boot] S3c64xx: Switch all I/O to use readl/writel function Zhong Hongbo
` (7 preceding siblings ...)
2012-07-07 9:57 ` [U-Boot] [PATCH 08/13] S3C6400: Adopt SPL framwork to support spl for nand flash Zhong Hongbo
@ 2012-07-07 9:57 ` Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 10/13] S3C64XX: Switch to use read/writel to operation clock system Zhong Hongbo
` (4 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Zhong Hongbo @ 2012-07-07 9:57 UTC (permalink / raw)
To: u-boot
From: Zhong Hongbo <bocui107@gmail.com>
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
---
arch/arm/cpu/arm1176/s3c64xx/Makefile | 2 +-
arch/arm/cpu/arm1176/s3c64xx/srom.c | 52 +++++++++++++++++++++++++++
arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 13 +++----
arch/arm/include/asm/arch-s3c64xx/sromc.h | 49 +++++++++++++++++++++++++
board/samsung/smdk6400/smdk6400.c | 38 ++++++++++++++------
include/configs/smdk6400.h | 1 +
6 files changed, 135 insertions(+), 20 deletions(-)
create mode 100644 arch/arm/cpu/arm1176/s3c64xx/srom.c
create mode 100644 arch/arm/include/asm/arch-s3c64xx/sromc.h
diff --git a/arch/arm/cpu/arm1176/s3c64xx/Makefile b/arch/arm/cpu/arm1176/s3c64xx/Makefile
index 2f37431..28786bf 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/Makefile
+++ b/arch/arm/cpu/arm1176/s3c64xx/Makefile
@@ -30,7 +30,7 @@ LIB = $(obj)lib$(SOC).o
SOBJS = reset.o
-COBJS-$(CONFIG_S3C64XX) += speed.o
+COBJS-$(CONFIG_S3C64XX) += speed.o srom.o
COBJS-y += timer.o
COBJS-$(CONFIG_PWM) += pwm.o
diff --git a/arch/arm/cpu/arm1176/s3c64xx/srom.c b/arch/arm/cpu/arm1176/s3c64xx/srom.c
new file mode 100644
index 0000000..297bc2d
--- /dev/null
+++ b/arch/arm/cpu/arm1176/s3c64xx/srom.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2012
+ * Zhong Hongbo <bocui107n@gmail.com>
+ * base on arch/arm/cpu/armv7/s5p-common/sromc.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sromc.h>
+#include <asm/arch/s3c6400.h>
+/*
+ * s3c64xx_config_sromc() - select the proper SROMC Bank and configure the
+ * band width control and bank control registers
+ * srom_bank - SROM
+ * srom_bw_conf - SMC Band witdh reg configuration value
+ * srom_bc_conf - SMC Bank Control reg configuration value
+ */
+void s3c64xx_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf)
+{
+ u32 tmp;
+ struct s3c64xx_sromc *srom =
+ (struct s3c64xx_sromc *)s3c64xx_get_base_sromc();
+
+ /* Configure SMC_BW register to handle proper SROMC bank */
+ tmp = srom->bw;
+ tmp &= ~(0xF << (srom_bank * 4));
+ tmp |= srom_bw_conf;
+
+ writel(tmp, &srom->bw);
+
+ /* Configure SMC_BC register */
+ writel(srom_bc_conf, &srom->bc[srom_bank]);
+}
+
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index 1d7d2b6..4da95ca 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -471,14 +471,6 @@
*/
#define ELFIN_SROM_BASE 0x70000000
-#define SROM_BW_REG __REG(ELFIN_SROM_BASE + 0x0)
-#define SROM_BC0_REG __REG(ELFIN_SROM_BASE + 0x4)
-#define SROM_BC1_REG __REG(ELFIN_SROM_BASE + 0x8)
-#define SROM_BC2_REG __REG(ELFIN_SROM_BASE + 0xC)
-#define SROM_BC3_REG __REG(ELFIN_SROM_BASE + 0x10)
-#define SROM_BC4_REG __REG(ELFIN_SROM_BASE + 0x14)
-#define SROM_BC5_REG __REG(ELFIN_SROM_BASE + 0x18)
-
/*
* SDRAM Controller
*/
@@ -721,6 +713,11 @@ static inline unsigned int s3c64xx_get_base_timer(void)
{
return ELFIN_TIMER_BASE;
}
+
+static inline unsigned int s3c64xx_get_base_sromc(void)
+{
+ return ELFIN_SROM_BASE;
+}
#endif
#endif /*__S3C6400_H__*/
diff --git a/arch/arm/include/asm/arch-s3c64xx/sromc.h b/arch/arm/include/asm/arch-s3c64xx/sromc.h
new file mode 100644
index 0000000..fcad635
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c64xx/sromc.h
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2012
+ * Zhong Hongbo <bocui107@gmail.com>
+ *
+ * base on arch/arm/include/asm/arch-s5pc1xx/sromc.h
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_SROMC_H_
+#define __ASM_ARCH_SROMC_H_
+
+#define SROMC_DATA16_WIDTH(x) (1 << ((x * 4) + 0))
+#define SROMC_BYTE_ADDR_MODE(x) (1 << ((x * 4) + 1))
+#define SROMC_WAIT_ENABLE(x) (1 << ((x * 4) + 2))
+#define SROMC_BYTE_ENABLE(x) (1 << ((x * 4) + 3))
+
+#define SROMC_BC_TACS(x) (x << 28) /* 0clk address set-up */
+#define SROMC_BC_TCOS(x) (x << 24) /* 4clk chip selection set-up */
+#define SROMC_BC_TACC(x) (x << 16) /* 14clk access cycle */
+#define SROMC_BC_TCOH(x) (x << 12) /* 1clk chip selection hold */
+#define SROMC_BC_TAH(x) (x << 8) /* 4clk address holding time */
+#define SROMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */
+#define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
+
+#ifndef __ASSEMBLY__
+struct s3c64xx_sromc {
+ unsigned int bw;
+ unsigned int bc[6];
+};
+#endif /* __ASSEMBLY__ */
+
+/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
+void s3c64xx_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
+
+#endif /* __ASM_ARCH_SROMC_H_ */
diff --git a/board/samsung/smdk6400/smdk6400.c b/board/samsung/smdk6400/smdk6400.c
index c40d1f9..be0e18b 100644
--- a/board/samsung/smdk6400/smdk6400.c
+++ b/board/samsung/smdk6400/smdk6400.c
@@ -30,6 +30,7 @@
#include <common.h>
#include <netdev.h>
+#include <asm/arch/sromc.h>
#include <asm/arch/s3c6400.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -53,25 +54,40 @@ static inline void delay(unsigned long loops)
/*
* Miscellaneous platform dependent initialisations
*/
-
+#ifdef CONFIG_CS8900
static void cs8900_pre_init(void)
{
- SROM_BW_REG &= ~(0xf << 4);
- SROM_BW_REG |= (1 << 7) | (1 << 6) | (1 << 4);
- SROM_BC1_REG = ((CS8900_Tacs << 28) + (CS8900_Tcos << 24) +
- (CS8900_Tacc << 16) + (CS8900_Tcoh << 12) +
- (CS8900_Tah << 8) + (CS8900_Tacp << 4) + CS8900_PMC);
+ u32 smc_bw_conf, smc_bc_conf;
+
+ /* Ethernet needs bus width of 16 bits */
+ smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK)
+ | SROMC_WAIT_ENABLE(CONFIG_ENV_SROM_BANK)
+ | SROMC_BYTE_ENABLE(CONFIG_ENV_SROM_BANK);
+ smc_bc_conf = SROMC_BC_TACS(CS8900_Tacs)
+ | SROMC_BC_TCOS(CS8900_Tcos)
+ | SROMC_BC_TACC(CS8900_Tacc)
+ | SROMC_BC_TCOH(CS8900_Tcoh)
+ | SROMC_BC_TAH(CS8900_Tah)
+ | SROMC_BC_TACP(CS8900_Tacp)
+ | SROMC_BC_PMC(CS8900_PMC);
+
+ /* Select and configure the SROMC bank */
+ s3c64xx_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
+
+}
+#else
+#define cs8900_pre_init() do {} while (0)
+#endif
+
+static void norflash_srom_init(void)
+{
+ u32 smc_bw_conf, smc_bc_conf;
}
int board_init(void)
{
cs8900_pre_init();
- /* NOR-flash in SROM0 */
-
- /* Enable WAIT */
- SROM_BW_REG |= 4 | 8 | 1;
-
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
index 2816f93..37fecee 100644
--- a/include/configs/smdk6400.h
+++ b/include/configs/smdk6400.h
@@ -78,6 +78,7 @@
/*
* Hardware drivers
*/
+#define CONFIG_ENV_SROM_BANK 2 /* Select SROM Bank-2 for Ethernet*/
#define CONFIG_CS8900 /* we have a CS8900 on-board */
#define CONFIG_CS8900_BASE 0x18800300
#define CONFIG_CS8900_BUS16 /* follow the Linux driver */
--
1.7.5.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 10/13] S3C64XX: Switch to use read/writel to operation clock system
2012-07-07 9:56 [U-Boot] S3c64xx: Switch all I/O to use readl/writel function Zhong Hongbo
` (8 preceding siblings ...)
2012-07-07 9:57 ` [U-Boot] [PATCH 09/13] S3C64XX: Change SROM init to use read/write operation Zhong Hongbo
@ 2012-07-07 9:57 ` Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 11/13] S3c64xx: clear GPIO, Interrupt, Watchdog flag Zhong Hongbo
` (3 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Zhong Hongbo @ 2012-07-07 9:57 UTC (permalink / raw)
To: u-boot
From: Zhong Hongbo <bocui107@gmail.com>
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
---
arch/arm/cpu/arm1176/s3c64xx/reset.S | 4 +-
arch/arm/cpu/arm1176/s3c64xx/speed.c | 50 ++++++---
arch/arm/include/asm/arch-s3c64xx/clock.h | 147 +++++++++++++++++++++++
arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 167 +--------------------------
board/samsung/smdk6400/lowlevel_init.S | 58 ++++------
drivers/usb/host/s3c64xx-hcd.c | 30 +++++-
6 files changed, 240 insertions(+), 216 deletions(-)
create mode 100644 arch/arm/include/asm/arch-s3c64xx/clock.h
diff --git a/arch/arm/cpu/arm1176/s3c64xx/reset.S b/arch/arm/cpu/arm1176/s3c64xx/reset.S
index eae572e..9e5ee84 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/reset.S
+++ b/arch/arm/cpu/arm1176/s3c64xx/reset.S
@@ -26,9 +26,9 @@
.globl reset_cpu
reset_cpu:
ldr r1, =ELFIN_CLOCK_POWER_BASE
- ldr r2, [r1, #SYS_ID_OFFSET]
+ ldr r2, [r1, #0x118] @ SYS_ID_OFFSET
ldr r3, =0xffff
and r2, r3, r2, lsr #12
- str r2, [r1, #SW_RST_OFFSET]
+ str r2, [r1, #0x114] @ SW_RST_OFFSET
_loop_forever:
b _loop_forever
diff --git a/arch/arm/cpu/arm1176/s3c64xx/speed.c b/arch/arm/cpu/arm1176/s3c64xx/speed.c
index 11962ac..05b44b9 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/speed.c
+++ b/arch/arm/cpu/arm1176/s3c64xx/speed.c
@@ -31,12 +31,13 @@
*/
#include <common.h>
+#include <asm/io.h>
#include <asm/arch/s3c6400.h>
+#include <asm/arch/clock.h>
#define APLL 0
#define MPLL 1
#define EPLL 2
-
/* ------------------------------------------------------------------------- */
/*
* NOTE: This describes the proper use of this file.
@@ -50,17 +51,20 @@
static ulong get_PLLCLK(int pllreg)
{
+ struct s3c64xx_clock *clk =
+ (struct s3c64xx_clock *)s3c64xx_get_base_clock();
+
ulong r, m, p, s;
switch (pllreg) {
case APLL:
- r = APLL_CON_REG;
+ r = readl(&clk->apll_con);
break;
case MPLL:
- r = MPLL_CON_REG;
+ r = readl(&clk->mpll_con);
break;
case EPLL:
- r = EPLL_CON0_REG;
+ r = readl(&clk->epll_con0);
break;
default:
hang();
@@ -76,9 +80,11 @@ static ulong get_PLLCLK(int pllreg)
/* return ARMCORE frequency */
ulong get_ARMCLK(void)
{
+ struct s3c64xx_clock *clk =
+ (struct s3c64xx_clock *)s3c64xx_get_base_clock();
ulong div;
- div = CLK_DIV0_REG;
+ div = readl(&clk->clk_div0);
return get_PLLCLK(APLL) / ((div & 0x7) + 1);
}
@@ -92,16 +98,20 @@ ulong get_FCLK(void)
/* return HCLK frequency */
ulong get_HCLK(void)
{
+ struct s3c64xx_clock *clk =
+ (struct s3c64xx_clock *)s3c64xx_get_base_clock();
ulong fclk;
+ ulong other;
- uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
- uint hclk_div = ((CLK_DIV0_REG >> 8) & 0x1) + 1;
+ uint hclkx2_div = ((readl(&clk->clk_div0) >> 9) & 0x7) + 1;
+ uint hclk_div = ((readl(&clk->clk_div0) >> 8) & 0x1) + 1;
/*
* Bit 7 exists on s3c6410, and not on s3c6400, it is reserved on
* s3c6400 and is always 0, and it is indeed running in ASYNC mode
*/
- if (OTHERS_REG & 0x80)
+ other = readl(&clk->others);
+ if (other & 0x80)
fclk = get_FCLK(); /* SYNC Mode */
else
fclk = get_PLLCLK(MPLL); /* ASYNC Mode */
@@ -112,11 +122,15 @@ ulong get_HCLK(void)
/* return PCLK frequency */
ulong get_PCLK(void)
{
+ struct s3c64xx_clock *clk =
+ (struct s3c64xx_clock *)s3c64xx_get_base_clock();
ulong fclk;
- uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
- uint pre_div = ((CLK_DIV0_REG >> 12) & 0xf) + 1;
+ uint hclkx2_div = ((readl(&clk->clk_div0) >> 9) & 0x7) + 1;
+ uint pre_div = ((readl(&clk->clk_div0) >> 12) & 0xf) + 1;
+ ulong other;
- if (OTHERS_REG & 0x80)
+ other = readl(&clk->others);
+ if (other & 0x80)
fclk = get_FCLK(); /* SYNC Mode */
else
fclk = get_PLLCLK(MPLL); /* ASYNC Mode */
@@ -132,14 +146,20 @@ ulong get_UCLK(void)
int print_cpuinfo(void)
{
- printf("\nCPU: S3C6400@%luMHz\n", get_ARMCLK() / 1000000);
+ struct s3c64xx_clock *clk =
+ (struct s3c64xx_clock *)s3c64xx_get_base_clock();
+ ulong other;
+
+ printf("\nCPU: S3C64XX@%luMHz\n", get_ARMCLK() / 1000000);
printf(" Fclk = %luMHz, Hclk = %luMHz, Pclk = %luMHz ",
get_FCLK() / 1000000, get_HCLK() / 1000000,
get_PCLK() / 1000000);
- if (OTHERS_REG & 0x80)
- printf("(SYNC Mode) \n");
+ other = readl(&clk->others);
+ if (other & 0x80)
+ printf("(SYNC Mode)\n");
else
- printf("(ASYNC Mode) \n");
+ printf("(ASYNC Mode)\n");
+
return 0;
}
diff --git a/arch/arm/include/asm/arch-s3c64xx/clock.h b/arch/arm/include/asm/arch-s3c64xx/clock.h
new file mode 100644
index 0000000..83b3651
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c64xx/clock.h
@@ -0,0 +1,147 @@
+/*
+ * (C) Copyright 2012
+ * Hongbo Zhong <bocui107@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_CLOCK_H_
+#define __ASM_ARM_ARCH_CLOCK_H_
+
+#ifndef __ASSEMBLY__
+
+#if defined(CONFIG_S3C6400)
+struct s3c64xx_clock {
+ unsigned int apll_lock;
+ unsigned int mpll_lock;
+ unsigned int epll_lock;
+ unsigned int apll_con;
+ unsigned int mpll_con;
+ unsigned int epll_con0;
+ unsigned int epll_con1;
+ unsigned int clk_src;
+ unsigned int clk_div0;
+ unsigned int clk_div1;
+ unsigned int clk_div2;
+ unsigned int clk_out;
+ unsigned int hclk_gate;
+ unsigned int pclk_gate;
+ unsigned int sclk_gate;
+ unsigned char res1[0xc4];
+ unsigned int ahb_con0;
+ unsigned int ahb_con1;
+ unsigned int ahb_con2;
+ unsigned char res2[0x04];
+ unsigned int sdma_sel;
+ unsigned int sw_rst;
+ unsigned int sys_id;
+ unsigned char res3[0x4];
+ unsigned int mem_sys_cfg;
+ unsigned int qos_override0;
+ unsigned int qos_override1;
+ unsigned int mem_cfg_stat;
+ unsigned char res4[0x6d4];
+ unsigned int pwr_cfg;
+ unsigned int eint_mask;
+ unsigned char res5[0x4];
+ unsigned int normal_cfg;
+ unsigned int stop_cfg;
+ unsigned int sleep_cfg;
+ unsigned char res6[0x4];
+ unsigned int osc_freq;
+ unsigned int osc_stable;
+ unsigned int pwr_stable;
+ unsigned char res7[0x4];
+ unsigned int mtc_stable;
+ unsigned char res8[0xcc];
+ unsigned int others;
+ unsigned int rst_stat;
+ unsigned int wakeup_stat;
+ unsigned int blk_pwr_stat;
+ unsigned int inf_reg0;
+ unsigned int inf_reg1;
+ unsigned int inf_reg2;
+ unsigned int inf_reg3;
+ unsigned int inf_reg4;
+ unsigned int inf_reg5;
+ unsigned int inf_reg6;
+ unsigned int inf_reg7;
+};
+
+#else
+struct s3c64xx_clock {
+ unsigned int apll_lock;
+ unsigned int mpll_lock;
+ unsigned int epll_lock;
+ unsigned int apll_con;
+ unsigned int mpll_con;
+ unsigned int epll_con0;
+ unsigned int epll_con1;
+ unsigned int clk_src;
+ unsigned int clk_div0;
+ unsigned int clk_div1;
+ unsigned int clk_div2;
+ unsigned int clk_out;
+ unsigned int hclk_gate;
+ unsigned int pclk_gate;
+ unsigned int sclk_gate;
+ unsigned int mem0_clk_gate;
+ unsigned char res1[0xc0];
+ unsigned int ahb_con0;
+ unsigned int ahb_con1;
+ unsigned int ahb_con2;
+ unsigned int clk_src2;
+ unsigned int sdma_sel;
+ unsigned char res2[0x04];
+ unsigned int sys_id;
+ unsigned char res3[0x4];
+ unsigned int mem_sys_cfg;
+ unsigned char res4[0x4];
+ unsigned int qos_override1;
+ unsigned int mem_cfg_stat;
+ unsigned char res5[0x6d4];
+ unsigned int pwr_cfg;
+ unsigned int eint_mask;
+ unsigned char res6[0x4];
+ unsigned int normal_cfg;
+ unsigned int stop_cfg;
+ unsigned int sleep_cfg;
+ unsigned int stop_mem_cfg;
+ unsigned int osc_freq;
+ unsigned int osc_stable;
+ unsigned int pwr_stable;
+ unsigned char res7[0x4];
+ unsigned int mtc_stable;
+ unsigned char res8[0x4];
+ unsigned int misc_con;
+ unsigned char res9[0xc8];
+ unsigned int others;
+ unsigned int rst_stat;
+ unsigned int wakeup_stat;
+ unsigned int blk_pwr_stat;
+ unsigned int inf_reg0;
+ unsigned int inf_reg1;
+ unsigned int inf_reg2;
+ unsigned int inf_reg3;
+ unsigned int inf_reg4;
+ unsigned int inf_reg5;
+ unsigned int inf_reg6;
+ unsigned int inf_reg7;
+};
+#endif /* CONFIG_S3C6400 */
+#endif /* __ASSEMBLY__ */
+#endif
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index 4da95ca..d15b37b 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -42,168 +42,6 @@
#define ELFIN_CLOCK_POWER_BASE 0x7e00f000
-/* Clock & Power Controller for mDirac3*/
-#define APLL_LOCK_OFFSET 0x00
-#define MPLL_LOCK_OFFSET 0x04
-#define EPLL_LOCK_OFFSET 0x08
-#define APLL_CON_OFFSET 0x0C
-#define MPLL_CON_OFFSET 0x10
-#define EPLL_CON0_OFFSET 0x14
-#define EPLL_CON1_OFFSET 0x18
-#define CLK_SRC_OFFSET 0x1C
-#define CLK_DIV0_OFFSET 0x20
-#define CLK_DIV1_OFFSET 0x24
-#define CLK_DIV2_OFFSET 0x28
-#define CLK_OUT_OFFSET 0x2C
-#define HCLK_GATE_OFFSET 0x30
-#define PCLK_GATE_OFFSET 0x34
-#define SCLK_GATE_OFFSET 0x38
-#define AHB_CON0_OFFSET 0x100
-#define AHB_CON1_OFFSET 0x104
-#define AHB_CON2_OFFSET 0x108
-#define SELECT_DMA_OFFSET 0x110
-#define SW_RST_OFFSET 0x114
-#define SYS_ID_OFFSET 0x118
-#define MEM_SYS_CFG_OFFSET 0x120
-#define QOS_OVERRIDE0_OFFSET 0x124
-#define QOS_OVERRIDE1_OFFSET 0x128
-#define MEM_CFG_STAT_OFFSET 0x12C
-#define PWR_CFG_OFFSET 0x804
-#define EINT_MASK_OFFSET 0x808
-#define NOR_CFG_OFFSET 0x810
-#define STOP_CFG_OFFSET 0x814
-#define SLEEP_CFG_OFFSET 0x818
-#define OSC_FREQ_OFFSET 0x820
-#define OSC_STABLE_OFFSET 0x824
-#define PWR_STABLE_OFFSET 0x828
-#define FPC_STABLE_OFFSET 0x82C
-#define MTC_STABLE_OFFSET 0x830
-#define OTHERS_OFFSET 0x900
-#define RST_STAT_OFFSET 0x904
-#define WAKEUP_STAT_OFFSET 0x908
-#define BLK_PWR_STAT_OFFSET 0x90C
-#define INF_REG0_OFFSET 0xA00
-#define INF_REG1_OFFSET 0xA04
-#define INF_REG2_OFFSET 0xA08
-#define INF_REG3_OFFSET 0xA0C
-#define INF_REG4_OFFSET 0xA10
-#define INF_REG5_OFFSET 0xA14
-#define INF_REG6_OFFSET 0xA18
-#define INF_REG7_OFFSET 0xA1C
-
-#define OSC_CNT_VAL_OFFSET 0x824
-#define PWR_CNT_VAL_OFFSET 0x828
-#define FPC_CNT_VAL_OFFSET 0x82C
-#define MTC_CNT_VAL_OFFSET 0x830
-
-#define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET)
-#define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET)
-#define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET)
-#define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET)
-#define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET)
-#define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET)
-#define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET)
-#define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET)
-#define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET)
-#define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET)
-#define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET)
-#define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET)
-#define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET)
-#define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET)
-#define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET)
-#define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET)
-#define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET)
-#define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET)
-#define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- SELECT_DMA_OFFSET)
-#define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET)
-#define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET)
-#define MEM_SYS_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- MEM_SYS_CFG_OFFSET)
-#define QOS_OVERRIDE0_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- QOS_OVERRIDE0_OFFSET)
-#define QOS_OVERRIDE1_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- QOS_OVERRIDE1_OFFSET)
-#define MEM_CFG_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- MEM_CFG_STAT_OFFSET)
-#define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET)
-#define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET)
-#define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET)
-#define STOP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET)
-#define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET)
-#define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET)
-#define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- OSC_CNT_VAL_OFFSET)
-#define PWR_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- PWR_CNT_VAL_OFFSET)
-#define FPC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- FPC_CNT_VAL_OFFSET)
-#define MTC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- MTC_CNT_VAL_OFFSET)
-#define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)
-#define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
-#define WAKEUP_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- WAKEUP_STAT_OFFSET)
-#define BLK_PWR_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- BLK_PWR_STAT_OFFSET)
-#define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
-#define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET)
-#define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET)
-#define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET)
-#define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET)
-#define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET)
-#define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET)
-#define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET)
-
-#define APLL_LOCK (ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET)
-#define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET)
-#define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET)
-#define APLL_CON (ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET)
-#define MPLL_CON (ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET)
-#define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET)
-#define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET)
-#define CLK_SRC (ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET)
-#define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET)
-#define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET)
-#define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET)
-#define CLK_OUT (ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET)
-#define HCLK_GATE (ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET)
-#define PCLK_GATE (ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET)
-#define SCLK_GATE (ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET)
-#define AHB_CON0 (ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET)
-#define AHB_CON1 (ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET)
-#define AHB_CON2 (ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET)
-#define SELECT_DMA (ELFIN_CLOCK_POWER_BASE + SELECT_DMA_OFFSET)
-#define SW_RST (ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET)
-#define SYS_ID (ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET)
-#define MEM_SYS_CFG (ELFIN_CLOCK_POWER_BASE + MEM_SYS_CFG_OFFSET)
-#define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE0_OFFSET)
-#define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE1_OFFSET)
-#define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE + MEM_CFG_STAT_OFFSET)
-#define PWR_CFG (ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET)
-#define EINT_MASK (ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET)
-#define NOR_CFG (ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET)
-#define STOP_CFG (ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET)
-#define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET)
-#define OSC_FREQ (ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET)
-#define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + OSC_CNT_VAL_OFFSET)
-#define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE + PWR_CNT_VAL_OFFSET)
-#define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + FPC_CNT_VAL_OFFSET)
-#define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + MTC_CNT_VAL_OFFSET)
-#define OTHERS (ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)
-#define RST_STAT (ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
-#define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
-#define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE + BLK_PWR_STAT_OFFSET)
-#define INF_REG0 (ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
-#define INF_REG1 (ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET)
-#define INF_REG2 (ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET)
-#define INF_REG3 (ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET)
-#define INF_REG4 (ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET)
-#define INF_REG5 (ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET)
-#define INF_REG6 (ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET)
-#define INF_REG7 (ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET)
-
-
/*
* GPIO
*/
@@ -718,6 +556,11 @@ static inline unsigned int s3c64xx_get_base_sromc(void)
{
return ELFIN_SROM_BASE;
}
+
+static inline unsigned int s3c64xx_get_base_clock(void)
+{
+ return ELFIN_CLOCK_POWER_BASE;
+}
#endif
#endif /*__S3C6400_H__*/
diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S
index 81e5c6a..8a24cc1 100644
--- a/board/samsung/smdk6400/lowlevel_init.S
+++ b/board/samsung/smdk6400/lowlevel_init.S
@@ -106,7 +106,7 @@ lowlevel_init:
bl mem_ctrl_asm_init
/* Wakeup support. Don't know if it's going to be used, untested. */
- ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
+ ldr r0, =(ELFIN_CLOCK_POWER_BASE + 0x904) @ RST_STAT_OFFSET
ldr r1, [r0]
bic r1, r1, #0xfffffff7
cmp r1, #0x8
@@ -119,23 +119,24 @@ lowlevel_init:
wakeup_reset:
/* Clear wakeup status register */
- ldr r0, =(ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
+ ldr r0, =(ELFIN_CLOCK_POWER_BASE + 0x908) @ WAKEUP_STAT_OFFSET
ldr r1, [r0]
str r1, [r0]
/* LED test */
ldr r0, =ELFIN_GPIO_BASE
ldr r1, =0x3000
- str r1, [r0, #GPNDAT_OFFSET]
+ str r1, [r0, #0x834] @ GPNDAT_OFFSET
/* Load return address and jump to kernel */
- ldr r0, =(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
+ ldr r0, =(ELFIN_CLOCK_POWER_BASE + 0xa00) @ INF_REG0_OFFSET
/* r1 = physical address of s3c6400_cpu_resume function */
ldr r1, [r0]
/* Jump to kernel (sleep-s3c6400.S) */
mov pc, r1
nop
nop
+
/*
* system_clock_init: Initialize core clock and bus clock.
* void system_clock_init(void)
@@ -144,10 +145,10 @@ system_clock_init:
ldr r0, =ELFIN_CLOCK_POWER_BASE /* 0x7e00f000 */
#ifdef CONFIG_SYNC_MODE
- ldr r1, [r0, #OTHERS_OFFSET]
+ ldr r1, [r0, #0x900] @ OTHERS_OFFSET
mov r2, #0x40
orr r1, r1, r2
- str r1, [r0, #OTHERS_OFFSET]
+ str r1, [r0, #0x900]
nop
nop
@@ -157,10 +158,10 @@ system_clock_init:
ldr r2, =0x80
orr r1, r1, r2
- str r1, [r0, #OTHERS_OFFSET]
+ str r1, [r0, #0x900]
check_syncack:
- ldr r1, [r0, #OTHERS_OFFSET]
+ ldr r1, [r0, #0x900]
ldr r2, =0xf00
and r1, r1, r2
cmp r1, #0xf00
@@ -177,69 +178,58 @@ check_syncack:
* seem to make much sense on S3C6400.
*/
#ifndef CONFIG_S3C6400
- ldr r1, [r0, #OTHERS_OFFSET]
+ ldr r1, [r0, #0x900] @ OTHERS_OFFSET
bic r1, r1, #0xC0
orr r1, r1, #0x40
- str r1, [r0, #OTHERS_OFFSET]
+ str r1, [r0, #0x900]
wait_for_async:
- ldr r1, [r0, #OTHERS_OFFSET]
+ ldr r1, [r0, #0x900] @ OTHERS_OFFSET
and r1, r1, #0xf00
cmp r1, #0x0
bne wait_for_async
#endif
- ldr r1, [r0, #OTHERS_OFFSET]
+ ldr r1, [r0, #0x900] @ OTHERS_OFFSET
bic r1, r1, #0x40
- str r1, [r0, #OTHERS_OFFSET]
+ str r1, [r0, #0x900]
#endif
mov r1, #0xff00
orr r1, r1, #0xff
- str r1, [r0, #APLL_LOCK_OFFSET]
- str r1, [r0, #MPLL_LOCK_OFFSET]
+ str r1, [r0, #0x0] @ APLL_LOCK_OFFSET
+ str r1, [r0, #0x4] @ MPLL_LOCK_OFFSET
/* Set Clock Divider */
- ldr r1, [r0, #CLK_DIV0_OFFSET]
+ ldr r1, [r0, #0x20] @ CLK_DIV0_OFFSET
bic r1, r1, #0x30000
bic r1, r1, #0xff00
bic r1, r1, #0xff
ldr r2, =CLK_DIV_VAL
orr r1, r1, r2
- str r1, [r0, #CLK_DIV0_OFFSET]
+ str r1, [r0, #0x20]
ldr r1, =APLL_VAL
- str r1, [r0, #APLL_CON_OFFSET]
+ str r1, [r0, #0x0c] @ APLL_CON_OFFSET
ldr r1, =MPLL_VAL
- str r1, [r0, #MPLL_CON_OFFSET]
+ str r1, [r0, #0x10] @ MPLL_CON_OFFSET
/* FOUT of EPLL is 96MHz */
ldr r1, =0x200203
- str r1, [r0, #EPLL_CON0_OFFSET]
+ str r1, [r0, #0x14] @ EPLL_CON0_OFFSET
ldr r1, =0x0
- str r1, [r0, #EPLL_CON1_OFFSET]
+ str r1, [r0, #0x18] @ EPLL_CON1_OFFSET
/* APLL, MPLL, EPLL select to Fout */
- ldr r1, [r0, #CLK_SRC_OFFSET]
+ ldr r1, [r0, #0x1c] @ CLK_SRC_OFFSET
orr r1, r1, #0x7
- str r1, [r0, #CLK_SRC_OFFSET]
+ str r1, [r0, #0x1c]
/* wait at least 200us to stablize all clock */
mov r1, #0x10000
1: subs r1, r1, #1
bne 1b
- /* Synchronization for VIC port */
-#if defined(CONFIG_SYNC_MODE)
- ldr r1, [r0, #OTHERS_OFFSET]
- orr r1, r1, #0x20
- str r1, [r0, #OTHERS_OFFSET]
-#elif !defined(CONFIG_S3C6400)
- /* According to 661558um_S3C6400X_rev10.pdf 0x20 is reserved */
- ldr r1, [r0, #OTHERS_OFFSET]
- bic r1, r1, #0x20
- str r1, [r0, #OTHERS_OFFSET]
-#endif
mov pc, lr
diff --git a/drivers/usb/host/s3c64xx-hcd.c b/drivers/usb/host/s3c64xx-hcd.c
index cd295da..74b5951 100644
--- a/drivers/usb/host/s3c64xx-hcd.c
+++ b/drivers/usb/host/s3c64xx-hcd.c
@@ -25,21 +25,45 @@
*/
#include <common.h>
+#include <asm/io.h>
#include <asm/arch/s3c6400.h>
+#include <asm/arch/clock.h>
int usb_cpu_init(void)
{
- OTHERS_REG |= 0x10000;
+ unsigned int val;
+ struct s3c64xx_clock *clk =
+ (struct s3c64xx_clock *)s3c64xx_get_base_clock();
+
+ val = readl(&clk->others);
+ val |= 0x10000;
+ writel(val, &clk->others);
+
return 0;
}
int usb_cpu_stop(void)
{
- OTHERS_REG &= ~0x10000;
+ unsigned int val;
+ struct s3c64xx_clock *clk =
+ (struct s3c64xx_clock *)s3c64xx_get_base_clock();
+
+ val = readl(&clk->others);
+ val &= ~0x10000;
+ writel(val, &clk->others);
+
return 0;
}
void usb_cpu_init_fail(void)
{
- OTHERS_REG &= ~0x10000;
+ unsigned int val;
+ struct s3c64xx_clock *clk =
+ (struct s3c64xx_clock *)s3c64xx_get_base_clock();
+
+ val = readl(&clk->others);
+ val &= ~0x10000;
+ writel(val, &clk->others);
+
+ return 0;
}
--
1.7.5.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 11/13] S3c64xx: clear GPIO, Interrupt, Watchdog flag.
2012-07-07 9:56 [U-Boot] S3c64xx: Switch all I/O to use readl/writel function Zhong Hongbo
` (9 preceding siblings ...)
2012-07-07 9:57 ` [U-Boot] [PATCH 10/13] S3C64XX: Switch to use read/writel to operation clock system Zhong Hongbo
@ 2012-07-07 9:57 ` Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 12/13] S3C6400: clear memory init variable Zhong Hongbo
` (2 subsequent siblings)
13 siblings, 0 replies; 20+ messages in thread
From: Zhong Hongbo @ 2012-07-07 9:57 UTC (permalink / raw)
To: u-boot
From: Zhong Hongbo <bocui107@gmail.com>
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
---
arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 294 +--------------------------
board/samsung/smdk6400/lowlevel_init.S | 50 ++---
board/samsung/smdk6400/mem_init.S | 4 +
3 files changed, 30 insertions(+), 318 deletions(-)
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index d15b37b..736cea2 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -47,172 +47,6 @@
*/
#define ELFIN_GPIO_BASE 0x7f008000
-#define GPACON_OFFSET 0x00
-#define GPADAT_OFFSET 0x04
-#define GPAPUD_OFFSET 0x08
-#define GPACONSLP_OFFSET 0x0C
-#define GPAPUDSLP_OFFSET 0x10
-#define GPBCON_OFFSET 0x20
-#define GPBDAT_OFFSET 0x24
-#define GPBPUD_OFFSET 0x28
-#define GPBCONSLP_OFFSET 0x2C
-#define GPBPUDSLP_OFFSET 0x30
-#define GPCCON_OFFSET 0x40
-#define GPCDAT_OFFSET 0x44
-#define GPCPUD_OFFSET 0x48
-#define GPCCONSLP_OFFSET 0x4C
-#define GPCPUDSLP_OFFSET 0x50
-#define GPDCON_OFFSET 0x60
-#define GPDDAT_OFFSET 0x64
-#define GPDPUD_OFFSET 0x68
-#define GPDCONSLP_OFFSET 0x6C
-#define GPDPUDSLP_OFFSET 0x70
-#define GPECON_OFFSET 0x80
-#define GPEDAT_OFFSET 0x84
-#define GPEPUD_OFFSET 0x88
-#define GPECONSLP_OFFSET 0x8C
-#define GPEPUDSLP_OFFSET 0x90
-#define GPFCON_OFFSET 0xA0
-#define GPFDAT_OFFSET 0xA4
-#define GPFPUD_OFFSET 0xA8
-#define GPFCONSLP_OFFSET 0xAC
-#define GPFPUDSLP_OFFSET 0xB0
-#define GPGCON_OFFSET 0xC0
-#define GPGDAT_OFFSET 0xC4
-#define GPGPUD_OFFSET 0xC8
-#define GPGCONSLP_OFFSET 0xCC
-#define GPGPUDSLP_OFFSET 0xD0
-#define GPHCON0_OFFSET 0xE0
-#define GPHCON1_OFFSET 0xE4
-#define GPHDAT_OFFSET 0xE8
-#define GPHPUD_OFFSET 0xEC
-#define GPHCONSLP_OFFSET 0xF0
-#define GPHPUDSLP_OFFSET 0xF4
-#define GPICON_OFFSET 0x100
-#define GPIDAT_OFFSET 0x104
-#define GPIPUD_OFFSET 0x108
-#define GPICONSLP_OFFSET 0x10C
-#define GPIPUDSLP_OFFSET 0x110
-#define GPJCON_OFFSET 0x120
-#define GPJDAT_OFFSET 0x124
-#define GPJPUD_OFFSET 0x128
-#define GPJCONSLP_OFFSET 0x12C
-#define GPJPUDSLP_OFFSET 0x130
-#define MEM0DRVCON_OFFSET 0x1D0
-#define MEM1DRVCON_OFFSET 0x1D4
-#define GPKCON0_OFFSET 0x800
-#define GPKCON1_OFFSET 0x804
-#define GPKDAT_OFFSET 0x808
-#define GPKPUD_OFFSET 0x80C
-#define GPLCON0_OFFSET 0x810
-#define GPLCON1_OFFSET 0x814
-#define GPLDAT_OFFSET 0x818
-#define GPLPUD_OFFSET 0x81C
-#define GPMCON_OFFSET 0x820
-#define GPMDAT_OFFSET 0x824
-#define GPMPUD_OFFSET 0x828
-#define GPNCON_OFFSET 0x830
-#define GPNDAT_OFFSET 0x834
-#define GPNPUD_OFFSET 0x838
-#define GPOCON_OFFSET 0x140
-#define GPODAT_OFFSET 0x144
-#define GPOPUD_OFFSET 0x148
-#define GPOCONSLP_OFFSET 0x14C
-#define GPOPUDSLP_OFFSET 0x150
-#define GPPCON_OFFSET 0x160
-#define GPPDAT_OFFSET 0x164
-#define GPPPUD_OFFSET 0x168
-#define GPPCONSLP_OFFSET 0x16C
-#define GPPPUDSLP_OFFSET 0x170
-#define GPQCON_OFFSET 0x180
-#define GPQDAT_OFFSET 0x184
-#define GPQPUD_OFFSET 0x188
-#define GPQCONSLP_OFFSET 0x18C
-#define GPQPUDSLP_OFFSET 0x190
-
-#define EINTPEND_OFFSET 0x924
-
-#define GPACON_REG __REG(ELFIN_GPIO_BASE + GPACON_OFFSET)
-#define GPADAT_REG __REG(ELFIN_GPIO_BASE + GPADAT_OFFSET)
-#define GPAPUD_REG __REG(ELFIN_GPIO_BASE + GPAPUD_OFFSET)
-#define GPACONSLP_REG __REG(ELFIN_GPIO_BASE + GPACONSLP_OFFSET)
-#define GPAPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET)
-#define GPBCON_REG __REG(ELFIN_GPIO_BASE + GPBCON_OFFSET)
-#define GPBDAT_REG __REG(ELFIN_GPIO_BASE + GPBDAT_OFFSET)
-#define GPBPUD_REG __REG(ELFIN_GPIO_BASE + GPBPUD_OFFSET)
-#define GPBCONSLP_REG __REG(ELFIN_GPIO_BASE + GPBCONSLP_OFFSET)
-#define GPBPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET)
-#define GPCCON_REG __REG(ELFIN_GPIO_BASE + GPCCON_OFFSET)
-#define GPCDAT_REG __REG(ELFIN_GPIO_BASE + GPCDAT_OFFSET)
-#define GPCPUD_REG __REG(ELFIN_GPIO_BASE + GPCPUD_OFFSET)
-#define GPCCONSLP_REG __REG(ELFIN_GPIO_BASE + GPCCONSLP_OFFSET)
-#define GPCPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET)
-#define GPDCON_REG __REG(ELFIN_GPIO_BASE + GPDCON_OFFSET)
-#define GPDDAT_REG __REG(ELFIN_GPIO_BASE + GPDDAT_OFFSET)
-#define GPDPUD_REG __REG(ELFIN_GPIO_BASE + GPDPUD_OFFSET)
-#define GPDCONSLP_REG __REG(ELFIN_GPIO_BASE + GPDCONSLP_OFFSET)
-#define GPDPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET)
-#define GPECON_REG __REG(ELFIN_GPIO_BASE + GPECON_OFFSET)
-#define GPEDAT_REG __REG(ELFIN_GPIO_BASE + GPEDAT_OFFSET)
-#define GPEPUD_REG __REG(ELFIN_GPIO_BASE + GPEPUD_OFFSET)
-#define GPECONSLP_REG __REG(ELFIN_GPIO_BASE + GPECONSLP_OFFSET)
-#define GPEPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET)
-#define GPFCON_REG __REG(ELFIN_GPIO_BASE + GPFCON_OFFSET)
-#define GPFDAT_REG __REG(ELFIN_GPIO_BASE + GPFDAT_OFFSET)
-#define GPFPUD_REG __REG(ELFIN_GPIO_BASE + GPFPUD_OFFSET)
-#define GPFCONSLP_REG __REG(ELFIN_GPIO_BASE + GPFCONSLP_OFFSET)
-#define GPFPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET)
-#define GPGCON_REG __REG(ELFIN_GPIO_BASE + GPGCON_OFFSET)
-#define GPGDAT_REG __REG(ELFIN_GPIO_BASE + GPGDAT_OFFSET)
-#define GPGPUD_REG __REG(ELFIN_GPIO_BASE + GPGPUD_OFFSET)
-#define GPGCONSLP_REG __REG(ELFIN_GPIO_BASE + GPGCONSLP_OFFSET)
-#define GPGPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET)
-#define GPHCON0_REG __REG(ELFIN_GPIO_BASE + GPHCON0_OFFSET)
-#define GPHCON1_REG __REG(ELFIN_GPIO_BASE + GPHCON1_OFFSET)
-#define GPHDAT_REG __REG(ELFIN_GPIO_BASE + GPHDAT_OFFSET)
-#define GPHPUD_REG __REG(ELFIN_GPIO_BASE + GPHPUD_OFFSET)
-#define GPHCONSLP_REG __REG(ELFIN_GPIO_BASE + GPHCONSLP_OFFSET)
-#define GPHPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET)
-#define GPICON_REG __REG(ELFIN_GPIO_BASE + GPICON_OFFSET)
-#define GPIDAT_REG __REG(ELFIN_GPIO_BASE + GPIDAT_OFFSET)
-#define GPIPUD_REG __REG(ELFIN_GPIO_BASE + GPIPUD_OFFSET)
-#define GPICONSLP_REG __REG(ELFIN_GPIO_BASE + GPICONSLP_OFFSET)
-#define GPIPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET)
-#define GPJCON_REG __REG(ELFIN_GPIO_BASE + GPJCON_OFFSET)
-#define GPJDAT_REG __REG(ELFIN_GPIO_BASE + GPJDAT_OFFSET)
-#define GPJPUD_REG __REG(ELFIN_GPIO_BASE + GPJPUD_OFFSET)
-#define GPJCONSLP_REG __REG(ELFIN_GPIO_BASE + GPJCONSLP_OFFSET)
-#define GPJPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET)
-#define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET)
-#define GPKCON1_REG __REG(ELFIN_GPIO_BASE + GPKCON1_OFFSET)
-#define GPKDAT_REG __REG(ELFIN_GPIO_BASE + GPKDAT_OFFSET)
-#define GPKPUD_REG __REG(ELFIN_GPIO_BASE + GPKPUD_OFFSET)
-#define GPLCON0_REG __REG(ELFIN_GPIO_BASE + GPLCON0_OFFSET)
-#define GPLCON1_REG __REG(ELFIN_GPIO_BASE + GPLCON1_OFFSET)
-#define GPLDAT_REG __REG(ELFIN_GPIO_BASE + GPLDAT_OFFSET)
-#define GPLPUD_REG __REG(ELFIN_GPIO_BASE + GPLPUD_OFFSET)
-#define GPMCON_REG __REG(ELFIN_GPIO_BASE + GPMCON_OFFSET)
-#define GPMDAT_REG __REG(ELFIN_GPIO_BASE + GPMDAT_OFFSET)
-#define GPMPUD_REG __REG(ELFIN_GPIO_BASE + GPMPUD_OFFSET)
-#define GPNCON_REG __REG(ELFIN_GPIO_BASE + GPNCON_OFFSET)
-#define GPNDAT_REG __REG(ELFIN_GPIO_BASE + GPNDAT_OFFSET)
-#define GPNPUD_REG __REG(ELFIN_GPIO_BASE + GPNPUD_OFFSET)
-#define GPOCON_REG __REG(ELFIN_GPIO_BASE + GPOCON_OFFSET)
-#define GPODAT_REG __REG(ELFIN_GPIO_BASE + GPODAT_OFFSET)
-#define GPOPUD_REG __REG(ELFIN_GPIO_BASE + GPOPUD_OFFSET)
-#define GPOCONSLP_REG __REG(ELFIN_GPIO_BASE + GPOCONSLP_OFFSET)
-#define GPOPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET)
-#define GPPCON_REG __REG(ELFIN_GPIO_BASE + GPPCON_OFFSET)
-#define GPPDAT_REG __REG(ELFIN_GPIO_BASE + GPPDAT_OFFSET)
-#define GPPPUD_REG __REG(ELFIN_GPIO_BASE + GPPPUD_OFFSET)
-#define GPPCONSLP_REG __REG(ELFIN_GPIO_BASE + GPPCONSLP_OFFSET)
-#define GPPPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET)
-#define GPQCON_REG __REG(ELFIN_GPIO_BASE + GPQCON_OFFSET)
-#define GPQDAT_REG __REG(ELFIN_GPIO_BASE + GPQDAT_OFFSET)
-#define GPQPUD_REG __REG(ELFIN_GPIO_BASE + GPQPUD_OFFSET)
-#define GPQCONSLP_REG __REG(ELFIN_GPIO_BASE + GPQCONSLP_OFFSET)
-#define GPQPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET)
-
/*
* Bus Matrix
*/
@@ -220,90 +54,6 @@
#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12)
-#define S3C64XX_MEM_SYS_CFG_NAND 0x0008
-#define S3C64XX_MEM_SYS_CFG_ONENAND S3C64XX_MEM_SYS_CFG_16BIT
-
-#define GPACON (ELFIN_GPIO_BASE + GPACON_OFFSET)
-#define GPADAT (ELFIN_GPIO_BASE + GPADAT_OFFSET)
-#define GPAPUD (ELFIN_GPIO_BASE + GPAPUD_OFFSET)
-#define GPACONSLP (ELFIN_GPIO_BASE + GPACONSLP_OFFSET)
-#define GPAPUDSLP (ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET)
-#define GPBCON (ELFIN_GPIO_BASE + GPBCON_OFFSET)
-#define GPBDAT (ELFIN_GPIO_BASE + GPBDAT_OFFSET)
-#define GPBPUD (ELFIN_GPIO_BASE + GPBPUD_OFFSET)
-#define GPBCONSLP (ELFIN_GPIO_BASE + GPBCONSLP_OFFSET)
-#define GPBPUDSLP (ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET)
-#define GPCCON (ELFIN_GPIO_BASE + GPCCON_OFFSET)
-#define GPCDAT (ELFIN_GPIO_BASE + GPCDAT_OFFSET)
-#define GPCPUD (ELFIN_GPIO_BASE + GPCPUD_OFFSET)
-#define GPCCONSLP (ELFIN_GPIO_BASE + GPCCONSLP_OFFSET)
-#define GPCPUDSLP (ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET)
-#define GPDCON (ELFIN_GPIO_BASE + GPDCON_OFFSET)
-#define GPDDAT (ELFIN_GPIO_BASE + GPDDAT_OFFSET)
-#define GPDPUD (ELFIN_GPIO_BASE + GPDPUD_OFFSET)
-#define GPDCONSLP (ELFIN_GPIO_BASE + GPDCONSLP_OFFSET)
-#define GPDPUDSLP (ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET)
-#define GPECON (ELFIN_GPIO_BASE + GPECON_OFFSET)
-#define GPEDAT (ELFIN_GPIO_BASE + GPEDAT_OFFSET)
-#define GPEPUD (ELFIN_GPIO_BASE + GPEPUD_OFFSET)
-#define GPECONSLP (ELFIN_GPIO_BASE + GPECONSLP_OFFSET)
-#define GPEPUDSLP (ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET)
-#define GPFCON (ELFIN_GPIO_BASE + GPFCON_OFFSET)
-#define GPFDAT (ELFIN_GPIO_BASE + GPFDAT_OFFSET)
-#define GPFPUD (ELFIN_GPIO_BASE + GPFPUD_OFFSET)
-#define GPFCONSLP (ELFIN_GPIO_BASE + GPFCONSLP_OFFSET)
-#define GPFPUDSLP (ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET)
-#define GPGCON (ELFIN_GPIO_BASE + GPGCON_OFFSET)
-#define GPGDAT (ELFIN_GPIO_BASE + GPGDAT_OFFSET)
-#define GPGPUD (ELFIN_GPIO_BASE + GPGPUD_OFFSET)
-#define GPGCONSLP (ELFIN_GPIO_BASE + GPGCONSLP_OFFSET)
-#define GPGPUDSLP (ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET)
-#define GPHCON0 (ELFIN_GPIO_BASE + GPHCON0_OFFSET)
-#define GPHCON1 (ELFIN_GPIO_BASE + GPHCON1_OFFSET)
-#define GPHDAT (ELFIN_GPIO_BASE + GPHDAT_OFFSET)
-#define GPHPUD (ELFIN_GPIO_BASE + GPHPUD_OFFSET)
-#define GPHCONSLP (ELFIN_GPIO_BASE + GPHCONSLP_OFFSET)
-#define GPHPUDSLP (ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET)
-#define GPICON (ELFIN_GPIO_BASE + GPICON_OFFSET)
-#define GPIDAT (ELFIN_GPIO_BASE + GPIDAT_OFFSET)
-#define GPIPUD (ELFIN_GPIO_BASE + GPIPUD_OFFSET)
-#define GPICONSLP (ELFIN_GPIO_BASE + GPICONSLP_OFFSET)
-#define GPIPUDSLP (ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET)
-#define GPJCON (ELFIN_GPIO_BASE + GPJCON_OFFSET)
-#define GPJDAT (ELFIN_GPIO_BASE + GPJDAT_OFFSET)
-#define GPJPUD (ELFIN_GPIO_BASE + GPJPUD_OFFSET)
-#define GPJCONSLP (ELFIN_GPIO_BASE + GPJCONSLP_OFFSET)
-#define GPJPUDSLP (ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET)
-#define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET)
-#define GPKCON1 (ELFIN_GPIO_BASE + GPKCON1_OFFSET)
-#define GPKDAT (ELFIN_GPIO_BASE + GPKDAT_OFFSET)
-#define GPKPUD (ELFIN_GPIO_BASE + GPKPUD_OFFSET)
-#define GPLCON0 (ELFIN_GPIO_BASE + GPLCON0_OFFSET)
-#define GPLCON1 (ELFIN_GPIO_BASE + GPLCON1_OFFSET)
-#define GPLDAT (ELFIN_GPIO_BASE + GPLDAT_OFFSET)
-#define GPLPUD (ELFIN_GPIO_BASE + GPLPUD_OFFSET)
-#define GPMCON (ELFIN_GPIO_BASE + GPMCON_OFFSET)
-#define GPMDAT (ELFIN_GPIO_BASE + GPMDAT_OFFSET)
-#define GPMPUD (ELFIN_GPIO_BASE + GPMPUD_OFFSET)
-#define GPNCON (ELFIN_GPIO_BASE + GPNCON_OFFSET)
-#define GPNDAT (ELFIN_GPIO_BASE + GPNDAT_OFFSET)
-#define GPNPUD (ELFIN_GPIO_BASE + GPNPUD_OFFSET)
-#define GPOCON (ELFIN_GPIO_BASE + GPOCON_OFFSET)
-#define GPODAT (ELFIN_GPIO_BASE + GPODAT_OFFSET)
-#define GPOPUD (ELFIN_GPIO_BASE + GPOPUD_OFFSET)
-#define GPOCONSLP (ELFIN_GPIO_BASE + GPOCONSLP_OFFSET)
-#define GPOPUDSLP (ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET)
-#define GPPCON (ELFIN_GPIO_BASE + GPPCON_OFFSET)
-#define GPPDAT (ELFIN_GPIO_BASE + GPPDAT_OFFSET)
-#define GPPPUD (ELFIN_GPIO_BASE + GPPPUD_OFFSET)
-#define GPPCONSLP (ELFIN_GPIO_BASE + GPPCONSLP_OFFSET)
-#define GPPPUDSLP (ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET)
-#define GPQCON (ELFIN_GPIO_BASE + GPQCON_OFFSET)
-#define GPQDAT (ELFIN_GPIO_BASE + GPQDAT_OFFSET)
-#define GPQPUD (ELFIN_GPIO_BASE + GPQPUD_OFFSET)
-#define GPQCONSLP (ELFIN_GPIO_BASE + GPQCONSLP_OFFSET)
-#define GPQPUDSLP (ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET)
-
/*
* Memory controller
*/
@@ -395,22 +145,12 @@
*/
#define ELFIN_VIC0_BASE_ADDR 0x71200000
#define ELFIN_VIC1_BASE_ADDR 0x71300000
-#define oINTMOD 0x0C /* VIC INT SELECT (IRQ or FIQ) */
-#define oINTUNMSK 0x10 /* VIC INT EN (write 1 to unmask) */
-#define oINTMSK 0x14 /* VIC INT EN CLEAR (write 1 to mask) */
-#define oINTSUBMSK 0x1C /* VIC SOFT INT CLEAR */
-#define oVECTADDR 0xF00 /* VIC ADDRESS */
/*
* Watchdog timer
*/
#define ELFIN_WATCHDOG_BASE 0x7E004000
-#define WTCON_REG __REG(0x7E004004)
-#define WTDAT_REG __REG(0x7E004008)
-#define WTCNT_REG __REG(0x7E00400C)
-
-
/*
* UART
*/
@@ -421,27 +161,10 @@
*/
#define ELFIN_TIMER_BASE 0x7F006000
-#if defined(CONFIG_CLK_400_100_50)
-#define STARTUP_AMDIV 400
-#define STARTUP_MDIV 400
-#define STARTUP_PDIV 6
-#define STARTUP_SDIV 1
-#elif defined(CONFIG_CLK_400_133_66)
-#define STARTUP_AMDIV 400
-#define STARTUP_MDIV 533
-#define STARTUP_PDIV 6
-#define STARTUP_SDIV 1
-#elif defined(CONFIG_CLK_533_133_66)
#define STARTUP_AMDIV 533
#define STARTUP_MDIV 533
#define STARTUP_PDIV 6
#define STARTUP_SDIV 1
-#elif defined(CONFIG_CLK_667_133_66)
-#define STARTUP_AMDIV 667
-#define STARTUP_MDIV 533
-#define STARTUP_PDIV 6
-#define STARTUP_SDIV 1
-#endif
#define STARTUP_PCLKDIV 3
#define STARTUP_HCLKX2DIV 1
@@ -456,21 +179,12 @@
#define STARTUP_MPLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
STARTUP_PDIV) * STARTUP_MDIV)
-#if defined(CONFIG_SYNC_MODE)
-#define APLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \
- (STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
- STARTUP_PDIV) * STARTUP_MDIV)
-#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
- (STARTUP_HCLKDIV + 1))
-#else
#define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | \
(STARTUP_PDIV << 8) | STARTUP_SDIV)
#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
STARTUP_PDIV) * STARTUP_AMDIV)
#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
(STARTUP_HCLKDIV + 1))
-#endif
/*-----------------------------------------------------------------------
@@ -552,14 +266,14 @@ static inline unsigned int s3c64xx_get_base_timer(void)
return ELFIN_TIMER_BASE;
}
-static inline unsigned int s3c64xx_get_base_sromc(void)
+static inline unsigned int s3c64xx_get_base_clock(void)
{
- return ELFIN_SROM_BASE;
+ return ELFIN_CLOCK_POWER_BASE;
}
-static inline unsigned int s3c64xx_get_base_clock(void)
+static inline unsigned int s3c64xx_get_base_sromc(void)
{
- return ELFIN_CLOCK_POWER_BASE;
+ return ELFIN_SROM_BASE;
}
#endif
diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S
index 8a24cc1..3feb164 100644
--- a/board/samsung/smdk6400/lowlevel_init.S
+++ b/board/samsung/smdk6400/lowlevel_init.S
@@ -46,13 +46,13 @@ lowlevel_init:
/* LED on only #8 */
ldr r0, =ELFIN_GPIO_BASE
ldr r1, =0x55540000
- str r1, [r0, #GPNCON_OFFSET]
+ str r1, [r0, #0x830] @ GPNCON_OFFSET
ldr r1, =0x55555555
- str r1, [r0, #GPNPUD_OFFSET]
+ str r1, [r0, #0x838] @ GPNPUD_OFFSET
ldr r1, =0xf000
- str r1, [r0, #GPNDAT_OFFSET]
+ str r1, [r0, #0x834] @ GPNDAT_OFFSET
/* Disable Watchdog */
ldr r0, =0x7e000000 @0x7e004000
@@ -61,7 +61,7 @@ lowlevel_init:
str r1, [r0]
/* External interrupt pending clear */
- ldr r0, =(ELFIN_GPIO_BASE+EINTPEND_OFFSET) /*EINTPEND*/
+ ldr r0, =(ELFIN_GPIO_BASE + 0x924) /*EINTPEND*/
ldr r1, [r0]
str r1, [r0]
@@ -70,40 +70,35 @@ lowlevel_init:
/* Disable all interrupts (VIC0 and VIC1) */
mvn r3, #0x0
- str r3, [r0, #oINTMSK]
- str r3, [r1, #oINTMSK]
+ str r3, [r0, #0x14] @ INTMSK
+ str r3, [r1, #0x14]
/* Set all interrupts as IRQ */
mov r3, #0x0
- str r3, [r0, #oINTMOD]
- str r3, [r1, #oINTMOD]
+ str r3, [r0, #0x0c] @ INTMOD
+ str r3, [r1, #0x0c]
/* Pending Interrupt Clear */
mov r3, #0x0
- str r3, [r0, #oVECTADDR]
- str r3, [r1, #oVECTADDR]
+ str r3, [r0, #0xf00] @ VECTADDR
+ str r3, [r1, #0xf00]
+
+#ifdef CONFIG_SPL_BUILD
/* init system clock */
- bl system_clock_init
+ bl system_clock_init
-#ifndef CONFIG_SPL_BUILD
- /* for UART */
- bl uart_asm_init
-#endif
+ /* memory init */
+ bl mem_ctrl_asm_init
-#ifdef CONFIG_BOOT_NAND
/* simple init for NAND */
- bl nand_asm_init
+ bl nand_asm_init
#endif
- /* Memory subsystem address 0x7e00f120 */
- ldr r0, =ELFIN_MEM_SYS_CFG
-
- /* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */
- mov r1, #S3C64XX_MEM_SYS_CFG_NAND
- str r1, [r0]
-
- bl mem_ctrl_asm_init
+#ifndef CONFIG_SPL_BUILD
+ /* for UART */
+ bl uart_asm_init
+#endif
/* Wakeup support. Don't know if it's going to be used, untested. */
ldr r0, =(ELFIN_CLOCK_POWER_BASE + 0x904) @ RST_STAT_OFFSET
@@ -136,7 +131,6 @@ wakeup_reset:
mov pc, r1
nop
nop
-
/*
* system_clock_init: Initialize core clock and bus clock.
* void system_clock_init(void)
@@ -241,11 +235,11 @@ uart_asm_init:
/* set GPIO to enable UART */
ldr r0, =ELFIN_GPIO_BASE
ldr r1, =0x220022
- str r1, [r0, #GPACON_OFFSET]
+ str r1, [r0, #0x0] @GPACON_OFFSET
mov pc, lr
#endif
-#ifdef CONFIG_BOOT_NAND
+#ifdef CONFIG_SPL_BUILD
/*
* NAND Interface init for SMDK6400
*/
diff --git a/board/samsung/smdk6400/mem_init.S b/board/samsung/smdk6400/mem_init.S
index df88cba..4a012e5 100644
--- a/board/samsung/smdk6400/mem_init.S
+++ b/board/samsung/smdk6400/mem_init.S
@@ -28,6 +28,10 @@
.globl mem_ctrl_asm_init
mem_ctrl_asm_init:
+ ldr r0, =ELFIN_MEM_SYS_CFG @Memory sussystem address 0x7e00f120
+ mov r1, #0xd @ Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON
+ str r1, [r0]
+
/* DMC1 base address 0x7e001000 */
ldr r0, =ELFIN_DMC1_BASE
--
1.7.5.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 12/13] S3C6400: clear memory init variable
2012-07-07 9:56 [U-Boot] S3c64xx: Switch all I/O to use readl/writel function Zhong Hongbo
` (10 preceding siblings ...)
2012-07-07 9:57 ` [U-Boot] [PATCH 11/13] S3c64xx: clear GPIO, Interrupt, Watchdog flag Zhong Hongbo
@ 2012-07-07 9:57 ` Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 13/13] S3C6400: Clear system clock variable Zhong Hongbo
2012-07-07 23:49 ` [U-Boot] S3c64xx: Switch all I/O to use readl/writel function Zhong Hongbo
13 siblings, 0 replies; 20+ messages in thread
From: Zhong Hongbo @ 2012-07-07 9:57 UTC (permalink / raw)
To: u-boot
From: Zhong Hongbo <bocui107@gmail.com>
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
---
arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 173 +--------------------------
board/samsung/smdk6400/mem_init.S | 110 +++++++++---------
2 files changed, 56 insertions(+), 227 deletions(-)
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index 736cea2..b254282 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -41,124 +41,16 @@
#include <asm/hardware.h>
#define ELFIN_CLOCK_POWER_BASE 0x7e00f000
-
-/*
- * GPIO
- */
#define ELFIN_GPIO_BASE 0x7f008000
-
-/*
- * Bus Matrix
- */
-#define ELFIN_MEM_SYS_CFG 0x7e00f120
-
-#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12)
-
-/*
- * Memory controller
- */
#define ELFIN_SROM_BASE 0x70000000
-
-/*
- * SDRAM Controller
- */
#define ELFIN_DMC0_BASE 0x7e000000
#define ELFIN_DMC1_BASE 0x7e001000
-
-#define INDEX_DMC_MEMC_STATUS 0x00
-#define INDEX_DMC_MEMC_CMD 0x04
-#define INDEX_DMC_DIRECT_CMD 0x08
-#define INDEX_DMC_MEMORY_CFG 0x0C
-#define INDEX_DMC_REFRESH_PRD 0x10
-#define INDEX_DMC_CAS_LATENCY 0x14
-#define INDEX_DMC_T_DQSS 0x18
-#define INDEX_DMC_T_MRD 0x1C
-#define INDEX_DMC_T_RAS 0x20
-#define INDEX_DMC_T_RC 0x24
-#define INDEX_DMC_T_RCD 0x28
-#define INDEX_DMC_T_RFC 0x2C
-#define INDEX_DMC_T_RP 0x30
-#define INDEX_DMC_T_RRD 0x34
-#define INDEX_DMC_T_WR 0x38
-#define INDEX_DMC_T_WTR 0x3C
-#define INDEX_DMC_T_XP 0x40
-#define INDEX_DMC_T_XSR 0x44
-#define INDEX_DMC_T_ESR 0x48
-#define INDEX_DMC_MEMORY_CFG2 0x4C
-#define INDEX_DMC_CHIP_0_CFG 0x200
-#define INDEX_DMC_CHIP_1_CFG 0x204
-#define INDEX_DMC_CHIP_2_CFG 0x208
-#define INDEX_DMC_CHIP_3_CFG 0x20C
-#define INDEX_DMC_USER_STATUS 0x300
-#define INDEX_DMC_USER_CONFIG 0x304
-
-/*
- * Memory Chip direct command
- */
-#define DMC_NOP0 0x0c0000
-#define DMC_NOP1 0x1c0000
-#define DMC_PA0 0x000000 /* Precharge all */
-#define DMC_PA1 0x100000
-#define DMC_AR0 0x040000 /* Autorefresh */
-#define DMC_AR1 0x140000
-#define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */
-#define DMC_SDR_MR1 0x180032
-#define DMC_DDR_MR0 0x080162
-#define DMC_DDR_MR1 0x180162
-#define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */
-#define DMC_mDDR_MR1 0x180032
-#define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */
-#define DMC_mSDR_EMR1 0x1a0000
-#define DMC_DDR_EMR0 0x090000
-#define DMC_DDR_EMR1 0x190000
-#define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */
-#define DMC_mDDR_EMR1 0x1a0000
-
-/*
- * Definitions for memory configuration
- * Set memory configuration
- * active_chips = 1'b0 (1 chip)
- * qos_master_chip = 3'b000(ARID[3:0])
- * memory burst = 3'b010(burst 4)
- * stop_mem_clock = 1'b0(disable dynamical stop)
- * auto_power_down = 1'b0(disable auto power-down mode)
- * power_down_prd = 6'b00_0000(0 cycle for auto power-down)
- * ap_bit = 1'b0 (bit position of auto-precharge is 10)
- * row_bits = 3'b010(# row address 13)
- * column_bits = 3'b010(# column address 10 )
- *
- * Set user configuration
- * 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR
- *
- * Set chip select for chip [n]
- * row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff
- * CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24]
- */
-
-/*
- * Nand flash controller
- */
+#define ELFIN_MEM_SYS_CFG 0x7e00f120
#define ELFIN_NAND_BASE 0x70200000
-
-/*
- * Interrupt
- */
#define ELFIN_VIC0_BASE_ADDR 0x71200000
#define ELFIN_VIC1_BASE_ADDR 0x71300000
-
-/*
- * Watchdog timer
- */
#define ELFIN_WATCHDOG_BASE 0x7E004000
-
-/*
- * UART
- */
#define ELFIN_UART_BASE 0x7F005000
-
-/*
- * PWM timer
- */
#define ELFIN_TIMER_BASE 0x7F006000
#define STARTUP_AMDIV 533
@@ -187,69 +79,6 @@
(STARTUP_HCLKDIV + 1))
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define DMC1_MEM_CFG 0x00010012 /* burst 4, 13-bit row, 10-bit col */
-#define DMC1_MEM_CFG2 0xB45
-#define DMC1_CHIP0_CFG 0x150F8 /* 0x5000_0000~0x57ff_ffff (128 MiB) */
-#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
-
-/* Memory Parameters */
-/* DDR Parameters */
-#define DDR_tREFRESH 7800 /* ns */
-#define DDR_tRAS 45 /* ns (min: 45ns)*/
-#define DDR_tRC 68 /* ns (min: 67.5ns)*/
-#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
-#define DDR_tRFC 80 /* ns (min: 80ns)*/
-#define DDR_tRP 23 /* ns (min: 22.5ns)*/
-#define DDR_tRRD 15 /* ns (min: 15ns)*/
-#define DDR_tWR 15 /* ns (min: 15ns)*/
-#define DDR_tXSR 120 /* ns (min: 120ns)*/
-#define DDR_CASL 3 /* CAS Latency 3 */
-
-/*
- * mDDR memory configuration
- */
-
-#define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000)
-
-#define DMC_DDR_BA_EMRS 2
-#define DMC_DDR_MEM_CASLAT 3
-/* 6 Set Cas Latency to 3 */
-#define DMC_DDR_CAS_LATENCY (DDR_CASL << 1)
-/* Min 0.75 ~ 1.25 */
-#define DMC_DDR_t_DQSS 1
-/* Min 2 tck */
-#define DMC_DDR_t_MRD 2
-/* 7, Min 45ns */
-#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1)
-/* 10, Min 67.5ns */
-#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1)
-/* 4,5(TRM), Min 22.5ns */
-#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1)
-#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3)
-/* 11,18(TRM) Min 80ns */
-#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1)
-#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5)
-/* 4, 5(TRM) Min 22.5ns */
-#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1)
-#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3)
-/* 3, Min 15ns */
-#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1)
-/* Min 15ns */
-#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1)
-#define DMC_DDR_t_WTR 2
-/* 1tck + tIS(1.5ns) */
-#define DMC_DDR_t_XP 2
-/* 17, Min 120ns */
-#define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1)
-#define DMC_DDR_t_ESR DMC_DDR_t_XSR
-/* TRM 2656 */
-#define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH))
-/* 2b01 : mDDR */
-#define DMC_DDR_USER_CONFIG 1
-
#ifndef __ASSEMBLY__
static inline unsigned int s3c64xx_get_base_uart(void)
{
diff --git a/board/samsung/smdk6400/mem_init.S b/board/samsung/smdk6400/mem_init.S
index 4a012e5..8b41484 100644
--- a/board/samsung/smdk6400/mem_init.S
+++ b/board/samsung/smdk6400/mem_init.S
@@ -36,98 +36,98 @@ mem_ctrl_asm_init:
ldr r0, =ELFIN_DMC1_BASE
ldr r1, =0x4
- str r1, [r0, #INDEX_DMC_MEMC_CMD]
+ str r1, [r0, #0x04] @ INDEX_DMC_MEMC_CMD
- ldr r1, =DMC_DDR_REFRESH_PRD
- str r1, [r0, #INDEX_DMC_REFRESH_PRD]
+ ldr r1, =0x40d
+ str r1, [r0, #0x10] @ INDEX_DMC_REFRESH_PRD
- ldr r1, =DMC_DDR_CAS_LATENCY
- str r1, [r0, #INDEX_DMC_CAS_LATENCY]
+ ldr r1, =(0x3 << 1)
+ str r1, [r0, #0x14] @ INDEX_DMC_CAS_LATENCY
- ldr r1, =DMC_DDR_t_DQSS
- str r1, [r0, #INDEX_DMC_T_DQSS]
+ ldr r1, =0x1
+ str r1, [r0, #0x18] @ INDEX_DMC_T_DQSS
- ldr r1, =DMC_DDR_t_MRD
- str r1, [r0, #INDEX_DMC_T_MRD]
+ ldr r1, =0x2
+ str r1, [r0, #0x1c] @ INDEX_DMC_T_MRD
- ldr r1, =DMC_DDR_t_RAS
- str r1, [r0, #INDEX_DMC_T_RAS]
+ ldr r1, =0x6
+ str r1, [r0, #0x20] @ INDEX_DMC_T_RAS
- ldr r1, =DMC_DDR_t_RC
- str r1, [r0, #INDEX_DMC_T_RC]
+ ldr r1, =0xa
+ str r1, [r0, #0x24] @ INDEX_DMC_T_RC
- ldr r1, =DMC_DDR_t_RCD
- ldr r2, =DMC_DDR_schedule_RCD
+ ldr r1, =0x4
+ ldr r2, =(0x1 << 3)
orr r1, r1, r2
- str r1, [r0, #INDEX_DMC_T_RCD]
+ str r1, [r0, #0x28] @ INDEX_DMC_T_RCD
- ldr r1, =DMC_DDR_t_RFC
- ldr r2, =DMC_DDR_schedule_RFC
+ ldr r1, =0xb
+ ldr r2, =(0x8 << 5)
orr r1, r1, r2
- str r1, [r0, #INDEX_DMC_T_RFC]
+ str r1, [r0, #0x2c] @ INDEX_DMC_T_RFC
- ldr r1, =DMC_DDR_t_RP
- ldr r2, =DMC_DDR_schedule_RP
+ ldr r1, =0x4
+ ldr r2, =(0x1 << 3)
orr r1, r1, r2
- str r1, [r0, #INDEX_DMC_T_RP]
+ str r1, [r0, #0x30] @ INDEX_DMC_T_RP
- ldr r1, =DMC_DDR_t_RRD
- str r1, [r0, #INDEX_DMC_T_RRD]
+ ldr r1, =0x2
+ str r1, [r0, #0x34] @ INDEX_DMC_T_RRD
- ldr r1, =DMC_DDR_t_WR
- str r1, [r0, #INDEX_DMC_T_WR]
+ ldr r1, =0x2
+ str r1, [r0, #0x38] @ INDEX_DMC_T_WR
- ldr r1, =DMC_DDR_t_WTR
- str r1, [r0, #INDEX_DMC_T_WTR]
+ ldr r1, =0x2
+ str r1, [r0, #0x3c] @ INDEX_DMC_T_WTR
- ldr r1, =DMC_DDR_t_XP
- str r1, [r0, #INDEX_DMC_T_XP]
+ ldr r1, =0x2
+ str r1, [r0, #0x40] @ INDEX_DMC_T_XP
- ldr r1, =DMC_DDR_t_XSR
- str r1, [r0, #INDEX_DMC_T_XSR]
+ ldr r1, =0x10
+ str r1, [r0, #0x44] @ INDEX_DMC_T_XSR
- ldr r1, =DMC_DDR_t_ESR
- str r1, [r0, #INDEX_DMC_T_ESR]
+ ldr r1, =0x10
+ str r1, [r0, #0x48] @ INDEX_DMC_T_ESR
- ldr r1, =DMC1_MEM_CFG
- str r1, [r0, #INDEX_DMC_MEMORY_CFG]
+ ldr r1, =0x00010012
+ str r1, [r0, #0x0c] @ INDEX_DMC_MEMORY_CFG
- ldr r1, =DMC1_MEM_CFG2
- str r1, [r0, #INDEX_DMC_MEMORY_CFG2]
+ ldr r1, =0x000100122
+ str r1, [r0, #0x4c] @ INDEX_DMC_MEMORY_CFG2
- ldr r1, =DMC1_CHIP0_CFG
- str r1, [r0, #INDEX_DMC_CHIP_0_CFG]
+ ldr r1, =0x150F8
+ str r1, [r0, #0x200] @ INDEX_DMC_CHIP_0_CFG
- ldr r1, =DMC_DDR_32_CFG
- str r1, [r0, #INDEX_DMC_USER_CONFIG]
+ ldr r1, =0x0
+ str r1, [r0, #0x304] @ INDEX_DMC_USER_CONFIG
/* DMC0 DDR Chip 0 configuration direct command reg */
- ldr r1, =DMC_NOP0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
+ ldr r1, =0x0c0000
+ str r1, [r0, #0x08] @ INDEX_DMC_DIRECT_CMD
/* Precharge All */
- ldr r1, =DMC_PA0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
+ ldr r1, =0x000000
+ str r1, [r0, #0x08] @ INDEX_DMC_DIRECT_CMD
/* Auto Refresh 2 time */
- ldr r1, =DMC_AR0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
+ ldr r1, =0x040000
+ str r1, [r0, #0x08] @ INDEX_DMC_DIRECT_CMD
+ str r1, [r0, #0x08]
/* MRS */
- ldr r1, =DMC_mDDR_EMR0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
+ ldr r1, =0x0a0000
+ str r1, [r0, #0x08] @ INDEX_DMC_DIRECT_CMD
/* Mode Reg */
- ldr r1, =DMC_mDDR_MR0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
+ ldr r1, =0x080032
+ str r1, [r0, #0x08] @ INDEX_DMC_DIRECT_CMD
/* Enable DMC1 */
mov r1, #0x0
- str r1, [r0, #INDEX_DMC_MEMC_CMD]
+ str r1, [r0, #0x04] @ INDEX_DMC_MEMC_CMD
check_dmc1_ready:
- ldr r1, [r0, #INDEX_DMC_MEMC_STATUS]
+ ldr r1, [r0, #0x00] @ INDEX_DMC_MEMC_STATUS
mov r2, #0x3
and r1, r1, r2
cmp r1, #0x1
--
1.7.5.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 13/13] S3C6400: Clear system clock variable
2012-07-07 9:56 [U-Boot] S3c64xx: Switch all I/O to use readl/writel function Zhong Hongbo
` (11 preceding siblings ...)
2012-07-07 9:57 ` [U-Boot] [PATCH 12/13] S3C6400: clear memory init variable Zhong Hongbo
@ 2012-07-07 9:57 ` Zhong Hongbo
2012-07-07 23:49 ` [U-Boot] S3c64xx: Switch all I/O to use readl/writel function Zhong Hongbo
13 siblings, 0 replies; 20+ messages in thread
From: Zhong Hongbo @ 2012-07-07 9:57 UTC (permalink / raw)
To: u-boot
From: Zhong Hongbo <bocui107@gmail.com>
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
---
arch/arm/include/asm/arch-s3c64xx/s3c6400.h | 26 --------------------------
board/samsung/smdk6400/lowlevel_init.S | 6 +++---
2 files changed, 3 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index b254282..acc6a37 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -53,32 +53,6 @@
#define ELFIN_UART_BASE 0x7F005000
#define ELFIN_TIMER_BASE 0x7F006000
-#define STARTUP_AMDIV 533
-#define STARTUP_MDIV 533
-#define STARTUP_PDIV 6
-#define STARTUP_SDIV 1
-
-#define STARTUP_PCLKDIV 3
-#define STARTUP_HCLKX2DIV 1
-#define STARTUP_HCLKDIV 1
-#define STARTUP_MPLLDIV 1
-#define STARTUP_APLLDIV 0
-
-#define CLK_DIV_VAL ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \
- (STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV)
-#define MPLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \
- (STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_MPLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
- STARTUP_PDIV) * STARTUP_MDIV)
-
-#define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | \
- (STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
- STARTUP_PDIV) * STARTUP_AMDIV)
-#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
- (STARTUP_HCLKDIV + 1))
-
-
#ifndef __ASSEMBLY__
static inline unsigned int s3c64xx_get_base_uart(void)
{
diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S
index 3feb164..7ccee59 100644
--- a/board/samsung/smdk6400/lowlevel_init.S
+++ b/board/samsung/smdk6400/lowlevel_init.S
@@ -199,13 +199,13 @@ wait_for_async:
bic r1, r1, #0x30000
bic r1, r1, #0xff00
bic r1, r1, #0xff
- ldr r2, =CLK_DIV_VAL
+ ldr r2, =0x3310
orr r1, r1, r2
str r1, [r0, #0x20]
- ldr r1, =APLL_VAL
+ ldr r1, =0x82150601
str r1, [r0, #0x0c] @ APLL_CON_OFFSET
- ldr r1, =MPLL_VAL
+ ldr r1, =0x82150601
str r1, [r0, #0x10] @ MPLL_CON_OFFSET
/* FOUT of EPLL is 96MHz */
--
1.7.5.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] S3c64xx: Switch all I/O to use readl/writel function
2012-07-07 9:56 [U-Boot] S3c64xx: Switch all I/O to use readl/writel function Zhong Hongbo
` (12 preceding siblings ...)
2012-07-07 9:57 ` [U-Boot] [PATCH 13/13] S3C6400: Clear system clock variable Zhong Hongbo
@ 2012-07-07 23:49 ` Zhong Hongbo
13 siblings, 0 replies; 20+ messages in thread
From: Zhong Hongbo @ 2012-07-07 23:49 UTC (permalink / raw)
To: u-boot
Add Guennadi to the loop.
Thanks,
hongbo
On 07/07/2012 05:56 PM, Zhong Hongbo wrote:
> This serial patch intent to:
> 1. Switch all I/O to use readl/writel function
> 2. Change nand_spl to use SPL framework
> 3. S3C64XX serial includes s3c6400 and s3c6410,
> Here seprate cpu and board file to support to board's of s3c6410.
>
>
> I test this patch on my s3c6410 development board. the log as following:
>
> U-Boot 2012.04.01-10905-g9fa0c77 (Jul 07 2012 - 15:50:57) for SMDK6400
>
>
> CPU: S3C64XX at 532MHz
> Fclk = 532MHz, Hclk = 133MHz, Pclk = 66MHz (ASYNC Mode)
> Board: DMATEK6410
> DRAM: 128 MiB
> WARNING: Caches not enabled
> NAND: 128 MiB
> *** Warning - bad CRC, using default environment
>
> In: serial
> Out: serial
> Err: serial
> Net: dm9000
> Hit any key to stop autoboot: 0
> DMATEK6410 #
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 02/13] S3C64XX: Switch to use readl/writel to operate nand flash
2012-07-07 9:57 ` [U-Boot] [PATCH 02/13] S3C64XX: Switch to use readl/writel to operate nand flash Zhong Hongbo
@ 2012-07-09 22:19 ` Scott Wood
[not found] ` <4FFC2015.508@gmail.com>
0 siblings, 1 reply; 20+ messages in thread
From: Scott Wood @ 2012-07-09 22:19 UTC (permalink / raw)
To: u-boot
On 07/07/2012 04:57 AM, Zhong Hongbo wrote:
> +static inline unsigned int s3c64xx_get_base_nand(void)
> +{
> + return ELFIN_NAND_BASE;
> +}
unsigned long or uintptr_t would be more appropriate, even if U-Boot is
unlikely to be 64-bit any time soon.
Or better, "struct s3c64xx_nand *".
> @@ -89,15 +96,16 @@ static void s3c_nand_select_chip(struct mtd_info *mtd, int chip)
> */
> static void s3c_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
> {
> + struct s3c64xx_nand *const nand = s3c_get_base_nand();
Is there any benefit to declaring local variables const like this? Why
this one and not all the others that never get altered?
-Scott
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 07/13] S3C6400: Delete nand_spl for S3C6400
2012-07-07 9:57 ` [U-Boot] [PATCH 07/13] S3C6400: Delete nand_spl for S3C6400 Zhong Hongbo
@ 2012-07-09 22:21 ` Scott Wood
0 siblings, 0 replies; 20+ messages in thread
From: Scott Wood @ 2012-07-09 22:21 UTC (permalink / raw)
To: u-boot
On 07/07/2012 04:57 AM, Zhong Hongbo wrote:
> From: Zhong Hongbo <bocui107@gmail.com>
>
> The old spl use nand_spl directory file to support
> nand flash boot. We will adopt the new SPL framework
> to implement it.
>
> Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
> ---
> board/samsung/smdk6400/config.mk | 28 -------
> boards.cfg | 4 +-
> include/configs/smdk6400.h | 4 +-
> nand_spl/board/samsung/smdk6400/Makefile | 117 ----------------------------
> nand_spl/board/samsung/smdk6400/config.mk | 40 ----------
> nand_spl/board/samsung/smdk6400/u-boot.lds | 78 ------------------
> 6 files changed, 4 insertions(+), 267 deletions(-)
> delete mode 100644 board/samsung/smdk6400/config.mk
> delete mode 100644 nand_spl/board/samsung/smdk6400/Makefile
> delete mode 100644 nand_spl/board/samsung/smdk6400/config.mk
> delete mode 100644 nand_spl/board/samsung/smdk6400/u-boot.lds
Shouldn't this come after the introduction of new SPL support, to
preserve bisectability?
> @@ -113,7 +113,6 @@
> #define CONFIG_CMD_PING
> #define CONFIG_CMD_ELF
> #define CONFIG_CMD_FAT
> -#define CONFIG_CMD_EXT2
>
> #define CONFIG_BOOTDELAY 3
>
> @@ -288,6 +287,7 @@
>
> #if !defined(CONFIG_ENABLE_MMU)
> #define CONFIG_CMD_USB 1
> +#define CONFIG_CMD_EXT2
> #define CONFIG_USB_S3C64XX
> #define CONFIG_USB_OHCI_NEW 1
> #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x74300000
I'm not sure how this is relevant.
-Scott
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 02/13] S3C64XX: Switch to use readl/writel to operate nand flash
[not found] ` <4FFC2015.508@gmail.com>
@ 2012-07-10 13:00 ` Zhong Hongbo
2012-07-10 15:36 ` Scott Wood
0 siblings, 1 reply; 20+ messages in thread
From: Zhong Hongbo @ 2012-07-10 13:00 UTC (permalink / raw)
To: u-boot
On 07/10/2012 08:29 PM, Zhong Hongbo wrote:
> On 07/10/2012 06:19 AM, Scott Wood wrote:
>> On 07/07/2012 04:57 AM, Zhong Hongbo wrote:
>>> +static inline unsigned int s3c64xx_get_base_nand(void)
>>> +{
>>> + return ELFIN_NAND_BASE;
>>> +}
>>
>> unsigned long or uintptr_t would be more appropriate, even if U-Boot is
>> unlikely to be 64-bit any time soon.
>
> Ok, I will fix it in V2.
>
> Thanks,
> hongbo
>>
>> Or better, "struct s3c64xx_nand *".
>>
>>> @@ -89,15 +96,16 @@ static void s3c_nand_select_chip(struct mtd_info *mtd, int chip)
>>> */
>>> static void s3c_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
>>> {
>>> + struct s3c64xx_nand *const nand = s3c_get_base_nand();
>>
>> Is there any benefit to declaring local variables const like this?
>
> I reference the nand driver of S5PXX CPU. So ...
Sorry, I make a mistake, The S5PXX have not nand flash support. When i
do the patch, I use the format as following?
struct s3c64xx_nand *nand = s3c_get_base_nand();
But when I use checkpatch.pl script to check the patch. more and more
waring about the line, it said that you should add 'const' before nand
variable.
Thanks,
hongbo
>
> Why
>> this one and not all the others that never get altered?
>
> Ok, I will change it. And i just found the S3c64XX is orphaned board.
> So Thanks you for the foucus it!
>
> Thanks,
> hongbo
>>
>> -Scott
>>
>>
>
>
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 02/13] S3C64XX: Switch to use readl/writel to operate nand flash
2012-07-10 13:00 ` Zhong Hongbo
@ 2012-07-10 15:36 ` Scott Wood
2012-07-11 12:34 ` Zhong Hongbo
0 siblings, 1 reply; 20+ messages in thread
From: Scott Wood @ 2012-07-10 15:36 UTC (permalink / raw)
To: u-boot
On 07/10/2012 08:00 AM, Zhong Hongbo wrote:
> On 07/10/2012 08:29 PM, Zhong Hongbo wrote:
>> On 07/10/2012 06:19 AM, Scott Wood wrote:
>>> On 07/07/2012 04:57 AM, Zhong Hongbo wrote:
>>>> @@ -89,15 +96,16 @@ static void s3c_nand_select_chip(struct mtd_info *mtd, int chip)
>>>> */
>>>> static void s3c_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
>>>> {
>>>> + struct s3c64xx_nand *const nand = s3c_get_base_nand();
>>>
>>> Is there any benefit to declaring local variables const like this?
>>
>> I reference the nand driver of S5PXX CPU. So ...
> Sorry, I make a mistake, The S5PXX have not nand flash support. When i
> do the patch, I use the format as following?
>
> struct s3c64xx_nand *nand = s3c_get_base_nand();
>
> But when I use checkpatch.pl script to check the patch. more and more
> waring about the line, it said that you should add 'const' before nand
> variable.
Could you paste the exact output from checkpatch.pl?
-Scott
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 02/13] S3C64XX: Switch to use readl/writel to operate nand flash
2012-07-10 15:36 ` Scott Wood
@ 2012-07-11 12:34 ` Zhong Hongbo
0 siblings, 0 replies; 20+ messages in thread
From: Zhong Hongbo @ 2012-07-11 12:34 UTC (permalink / raw)
To: u-boot
Hi Scott,
On 07/10/2012 11:36 PM, Scott Wood wrote:
> On 07/10/2012 08:00 AM, Zhong Hongbo wrote:
>> On 07/10/2012 08:29 PM, Zhong Hongbo wrote:
>>> On 07/10/2012 06:19 AM, Scott Wood wrote:
>>>> On 07/07/2012 04:57 AM, Zhong Hongbo wrote:
>>>>> @@ -89,15 +96,16 @@ static void s3c_nand_select_chip(struct mtd_info *mtd, int chip)
>>>>> */
>>>>> static void s3c_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
>>>>> {
>>>>> + struct s3c64xx_nand *const nand = s3c_get_base_nand();
>>>>
>>>> Is there any benefit to declaring local variables const like this?
>>>
>>> I reference the nand driver of S5PXX CPU. So ...
>> Sorry, I make a mistake, The S5PXX have not nand flash support. When i
>> do the patch, I use the format as following?
>>
>> struct s3c64xx_nand *nand = s3c_get_base_nand();
>>
>> But when I use checkpatch.pl script to check the patch. more and more
>> waring about the line, it said that you should add 'const' before nand
>> variable.
>
> Could you paste the exact output from checkpatch.pl?
Just redo the patch, I can not reproduce the issue. Thank you for your
point.
Thanks,
hongbo
>
> -Scott
>
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2012-07-11 12:34 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-07-07 9:56 [U-Boot] S3c64xx: Switch all I/O to use readl/writel function Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 01/13] smdk6400: Move smdk6400 board from Makefile to boards.cfg Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 02/13] S3C64XX: Switch to use readl/writel to operate nand flash Zhong Hongbo
2012-07-09 22:19 ` Scott Wood
[not found] ` <4FFC2015.508@gmail.com>
2012-07-10 13:00 ` Zhong Hongbo
2012-07-10 15:36 ` Scott Wood
2012-07-11 12:34 ` Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 03/13] S3C64XX: Use readl/writel to operate uart Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 04/13] S3C64XX: add pwm for s3c64xx support Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 05/13] S3C64XX: reference s5p cpu time system for s3c64xx timer Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 06/13] S3C64xx: mov cpu_init.S to the board directory Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 07/13] S3C6400: Delete nand_spl for S3C6400 Zhong Hongbo
2012-07-09 22:21 ` Scott Wood
2012-07-07 9:57 ` [U-Boot] [PATCH 08/13] S3C6400: Adopt SPL framwork to support spl for nand flash Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 09/13] S3C64XX: Change SROM init to use read/write operation Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 10/13] S3C64XX: Switch to use read/writel to operation clock system Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 11/13] S3c64xx: clear GPIO, Interrupt, Watchdog flag Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 12/13] S3C6400: clear memory init variable Zhong Hongbo
2012-07-07 9:57 ` [U-Boot] [PATCH 13/13] S3C6400: Clear system clock variable Zhong Hongbo
2012-07-07 23:49 ` [U-Boot] S3c64xx: Switch all I/O to use readl/writel function Zhong Hongbo
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