[U-Boot] [PATCH] Move L2-cache enable/disable function to soc dependent code

[U-Boot] [PATCH] Move L2-cache enable/disable function to soc dependent code

[Kim, Heung Jun]

The L2 cache enable/disable function in the cpu/arm_cortexa8/cpu.c moved
to cpu/arm_cortexa8/omap3/cache.c.

Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
---
 cpu/arm_cortexa8/cpu.c                 |   65 +--------------------
 cpu/arm_cortexa8/omap3/Makefile        |    2 +-
 cpu/arm_cortexa8/omap3/board.c         |    4 +-
 cpu/arm_cortexa8/omap3/cache.c         |   99 ++++++++++++++++++++++++++++++++
 include/asm-arm/arch-omap3/sys_proto.h |    2 +
 5 files changed, 107 insertions(+), 65 deletions(-)
 create mode 100644 cpu/arm_cortexa8/omap3/cache.c

diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index 3e1780b..209bbd0 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -41,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #endif

 #ifndef CONFIG_L2_OFF
-void l2cache_disable(void);
+void l2_cache_disable(void);
 #endif

 static void cache_flush(void);
@@ -80,7 +80,7 @@ int cleanup_before_linux(void)

 #ifndef CONFIG_L2_OFF
 	/* turn off L2 cache */
-	l2cache_disable();
+	l2_cache_disable();
 	/* invalidate L2 cache also */
 	v7_flush_dcache_all(get_device_type());
 #endif
@@ -89,71 +89,12 @@ int cleanup_before_linux(void)
 	asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));

 #ifndef CONFIG_L2_OFF
-	l2cache_enable();
+	l2_cache_enable();
 #endif

 	return 0;
 }

-void l2cache_enable()
-{
-	unsigned long i;
-	volatile unsigned int j;
-
-	/* ES2 onwards we can disable/enable L2 ourselves */
-	if (get_cpu_rev() >= CPU_3XX_ES20) {
-		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
-		__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
-		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
-	} else {
-		/* Save r0, r12 and restore them after usage */
-		__asm__ __volatile__("mov %0, r12":"=r"(j));
-		__asm__ __volatile__("mov %0, r0":"=r"(i));
-
-		/*
-		 * GP Device ROM code API usage here
-		 * r12 = AUXCR Write function and r0 value
-		 */
-		__asm__ __volatile__("mov r12, #0x3");
-		__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
-		__asm__ __volatile__("orr r0, r0, #0x2");
-		/* SMI instruction to call ROM Code API */
-		__asm__ __volatile__(".word 0xE1600070");
-		__asm__ __volatile__("mov r0, %0":"=r"(i));
-		__asm__ __volatile__("mov r12, %0":"=r"(j));
-	}
-
-}
-
-void l2cache_disable()
-{
-	unsigned long i;
-	volatile unsigned int j;
-
-	/* ES2 onwards we can disable/enable L2 ourselves */
-	if (get_cpu_rev() >= CPU_3XX_ES20) {
-		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
-		__asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
-		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
-	} else {
-		/* Save r0, r12 and restore them after usage */
-		__asm__ __volatile__("mov %0, r12":"=r"(j));
-		__asm__ __volatile__("mov %0, r0":"=r"(i));
-
-		/*
-		 * GP Device ROM code API usage here
-		 * r12 = AUXCR Write function and r0 value
-		 */
-		__asm__ __volatile__("mov r12, #0x3");
-		__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
-		__asm__ __volatile__("bic r0, r0, #0x2");
-		/* SMI instruction to call ROM Code API */
-		__asm__ __volatile__(".word 0xE1600070");
-		__asm__ __volatile__("mov r0, %0":"=r"(i));
-		__asm__ __volatile__("mov r12, %0":"=r"(j));
-	}
-}
-
 static void cache_flush(void)
 {
 	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile
index b96b3dd..f83036b 100644
--- a/cpu/arm_cortexa8/omap3/Makefile
+++ b/cpu/arm_cortexa8/omap3/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	=  $(obj)lib$(SOC).a

 SOBJS	:= lowlevel_init.o
-COBJS	:= sys_info.o board.o clock.o interrupts.o mem.o syslib.o
+COBJS	:= sys_info.o board.o clock.o interrupts.o mem.o syslib.o cache.o

 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
index 51d5cf6..26cb436 100644
--- a/cpu/arm_cortexa8/omap3/board.c
+++ b/cpu/arm_cortexa8/omap3/board.c
@@ -206,9 +206,9 @@ void s_init(void)
 #endif

 #ifdef CONFIG_L2_OFF
-	l2cache_disable();
+	l2_cache_disable();
 #else
-	l2cache_enable();
+	l2_cache_enable();
 #endif
 	/*
 	 * Writing to AuxCR in U-boot using SMI for GP DEV
diff --git a/cpu/arm_cortexa8/omap3/cache.c b/cpu/arm_cortexa8/omap3/cache.c
new file mode 100644
index 0000000..d195046
--- /dev/null
+++ b/cpu/arm_cortexa8/omap3/cache.c
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2009
+ * Samsung Electornics, HeungJun Kim <riverful.kim@samsung.com>
+ *
+ * (C) Copyright 2008 Texas Insturments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * L2 cache specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/sys_proto.h>
+
+void l2_cache_enable()
+{
+	unsigned long i;
+	volatile unsigned int j;
+
+	/* ES2 onwards we can disable/enable L2 ourselves */
+	if (get_cpu_rev() >= CPU_3XX_ES20) {
+		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
+		__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
+		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
+	} else {
+		/* Save r0, r12 and restore them after usage */
+		__asm__ __volatile__("mov %0, r12":"=r"(j));
+		__asm__ __volatile__("mov %0, r0":"=r"(i));
+
+		/*
+		 * GP Device ROM code API usage here
+		 * r12 = AUXCR Write function and r0 value
+		 */
+		__asm__ __volatile__("mov r12, #0x3");
+		__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
+		__asm__ __volatile__("orr r0, r0, #0x2");
+		/* SMI instruction to call ROM Code API */
+		__asm__ __volatile__(".word 0xE1600070");
+		__asm__ __volatile__("mov r0, %0":"=r"(i));
+		__asm__ __volatile__("mov r12, %0":"=r"(j));
+	}
+
+}
+
+void l2_cache_disable()
+{
+	unsigned long i;
+	volatile unsigned int j;
+
+	/* ES2 onwards we can disable/enable L2 ourselves */
+	if (get_cpu_rev() >= CPU_3XX_ES20) {
+		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
+		__asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
+		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
+	} else {
+		/* Save r0, r12 and restore them after usage */
+		__asm__ __volatile__("mov %0, r12":"=r"(j));
+		__asm__ __volatile__("mov %0, r0":"=r"(i));
+
+		/*
+		 * GP Device ROM code API usage here
+		 * r12 = AUXCR Write function and r0 value
+		 */
+		__asm__ __volatile__("mov r12, #0x3");
+		__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
+		__asm__ __volatile__("bic r0, r0, #0x2");
+		/* SMI instruction to call ROM Code API */
+		__asm__ __volatile__(".word 0xE1600070");
+		__asm__ __volatile__("mov r0, %0":"=r"(i));
+		__asm__ __volatile__("mov r12, %0":"=r"(j));
+	}
+}
+
diff --git a/include/asm-arm/arch-omap3/sys_proto.h
b/include/asm-arm/arch-omap3/sys_proto.h
index 7361d08..4f43aef 100644
--- a/include/asm-arm/arch-omap3/sys_proto.h
+++ b/include/asm-arm/arch-omap3/sys_proto.h
@@ -63,5 +63,7 @@ void make_cs1_contiguous(void);
 void omap_nand_switch_ecc(int);
 void power_init_r(void);
 void dieid_num_r(void);
+void l2_cache_disable();
+void l2_cache_enable();

 #endif
-- 
1.5.6.3

[U-Boot] [PATCH] Move L2-cache enable/disable function to soc dependent code

[Jean-Christophe PLAGNIOL-VILLARD]

On 20:27 Fri 29 May     , Kim, Heung Jun wrote:
> The L2 cache enable/disable function in the cpu/arm_cortexa8/cpu.c moved
> to cpu/arm_cortexa8/omap3/cache.c.
please mention omap3 in the title too
> 
> Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
> ---
> + * (C) Copyright 2002
> + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +/*
> + * L2 cache specific code
> + */
> +
> +#include <common.h>
> +#include <command.h>
> +#include <asm/arch/sys_proto.h>
> +
> +void l2_cache_enable()
> +{
> +	unsigned long i;
> +	volatile unsigned int j;
> +
as it's nearly only in asm implement it in assembly olny will be better
> +	/* ES2 onwards we can disable/enable L2 ourselves */
> +	if (get_cpu_rev() >= CPU_3XX_ES20) {
> +		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
> +		__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
<snip>
> diff --git a/include/asm-arm/arch-omap3/sys_proto.h
> b/include/asm-arm/arch-omap3/sys_proto.h
> index 7361d08..4f43aef 100644
> --- a/include/asm-arm/arch-omap3/sys_proto.h
> +++ b/include/asm-arm/arch-omap3/sys_proto.h
> @@ -63,5 +63,7 @@ void make_cs1_contiguous(void);
>  void omap_nand_switch_ecc(int);
>  void power_init_r(void);
>  void dieid_num_r(void);
> +void l2_cache_disable();
> +void l2_cache_enable();
please move these two funtcions in
include/asm-arm/cache.h

please rebase it against the u-boot-arm/next

Best Regards,
J.

[U-Boot] [PATCH] Move L2-cache enable/disable function to soc dependent code

[HeungJun, Kim]

Ok. Jean.
Very thanks to review. 
I have a question about one thing you pointed out.

===
as it's nearly only in asm implement it in assembly olny will be better
> +	/* ES2 onwards we can disable/enable L2 ourselves */
> +	if (get_cpu_rev() >= CPU_3XX_ES20) {
> +		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
> +		__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
===

I think you tell me the position is in the assembly code like lowlevel_init.S. Is it right?
Can you explain more detailed about this part, plz? :)

If my thinking is alright, I'll re-update this patch soon. 

Best Regards,
Riverful

----- ?? ??? -----
?? ??: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
?? ??: 2009? 5? 30? ??? ?? 6:46
?? ??: Kim, Heung Jun <riverful@gmail.com>
??: u-boot at lists.denx.de; Dirk Behme <dirk.behme@googlemail.com>; riverful.kim at samsung.com; inki.dae at samsung.com; mk7.kang at samsung.com; kyungmin.park at samsung.com; bhmin at samsung.com; jh106.choi at samsung.com
??: Re: [U-Boot] [PATCH] Move L2-cache enable/disable function to soc	dependent code

On 20:27 Fri 29 May     , Kim, Heung Jun wrote:
> The L2 cache enable/disable function in the cpu/arm_cortexa8/cpu.c moved
> to cpu/arm_cortexa8/omap3/cache.c.
please mention omap3 in the title too
> 
> Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
> ---
> + * (C) Copyright 2002
> + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +/*
> + * L2 cache specific code
> + */
> +
> +#include <common.h>
> +#include <command.h>
> +#include <asm/arch/sys_proto.h>
> +
> +void l2_cache_enable()
> +{
> +	unsigned long i;
> +	volatile unsigned int j;
> +
as it's nearly only in asm implement it in assembly olny will be better
> +	/* ES2 onwards we can disable/enable L2 ourselves */
> +	if (get_cpu_rev() >= CPU_3XX_ES20) {
> +		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
> +		__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
<snip>
> diff --git a/include/asm-arm/arch-omap3/sys_proto.h
> b/include/asm-arm/arch-omap3/sys_proto.h
> index 7361d08..4f43aef 100644
> --- a/include/asm-arm/arch-omap3/sys_proto.h
> +++ b/include/asm-arm/arch-omap3/sys_proto.h
> @@ -63,5 +63,7 @@ void make_cs1_contiguous(void);
>  void omap_nand_switch_ecc(int);
>  void power_init_r(void);
>  void dieid_num_r(void);
> +void l2_cache_disable();
> +void l2_cache_enable();
please move these two funtcions in
include/asm-arm/cache.h

please rebase it against the u-boot-arm/next

Best Regards,
J.