From mboxrd@z Thu Jan  1 00:00:00 1970
From: HeungJun, Kim <riverful@gmail.com>
Date: Sat, 30 May 2009 20:34:31 +0900
Subject: [U-Boot] [PATCH] Move L2-cache enable/disable function to
	soc	dependent code
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Ok. Jean.
Very thanks to review. 
I have a question about one thing you pointed out.

===
as it's nearly only in asm implement it in assembly olny will be better
> +	/* ES2 onwards we can disable/enable L2 ourselves */
> +	if (get_cpu_rev() >= CPU_3XX_ES20) {
> +		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
> +		__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
===

I think you tell me the position is in the assembly code like lowlevel_init.S. Is it right?
Can you explain more detailed about this part, plz? :)

If my thinking is alright, I'll re-update this patch soon. 

Best Regards,
Riverful

----- ?? ??? -----
?? ??: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
?? ??: 2009? 5? 30? ??? ?? 6:46
?? ??: Kim, Heung Jun <riverful@gmail.com>
??: u-boot at lists.denx.de; Dirk Behme <dirk.behme@googlemail.com>; riverful.kim at samsung.com; inki.dae at samsung.com; mk7.kang at samsung.com; kyungmin.park at samsung.com; bhmin at samsung.com; jh106.choi at samsung.com
??: Re: [U-Boot] [PATCH] Move L2-cache enable/disable function to soc	dependent code

On 20:27 Fri 29 May     , Kim, Heung Jun wrote:
> The L2 cache enable/disable function in the cpu/arm_cortexa8/cpu.c moved
> to cpu/arm_cortexa8/omap3/cache.c.
please mention omap3 in the title too
> 
> Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
> ---
> + * (C) Copyright 2002
> + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +/*
> + * L2 cache specific code
> + */
> +
> +#include <common.h>
> +#include <command.h>
> +#include <asm/arch/sys_proto.h>
> +
> +void l2_cache_enable()
> +{
> +	unsigned long i;
> +	volatile unsigned int j;
> +
as it's nearly only in asm implement it in assembly olny will be better
> +	/* ES2 onwards we can disable/enable L2 ourselves */
> +	if (get_cpu_rev() >= CPU_3XX_ES20) {
> +		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
> +		__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
<snip>
> diff --git a/include/asm-arm/arch-omap3/sys_proto.h
> b/include/asm-arm/arch-omap3/sys_proto.h
> index 7361d08..4f43aef 100644
> --- a/include/asm-arm/arch-omap3/sys_proto.h
> +++ b/include/asm-arm/arch-omap3/sys_proto.h
> @@ -63,5 +63,7 @@ void make_cs1_contiguous(void);
>  void omap_nand_switch_ecc(int);
>  void power_init_r(void);
>  void dieid_num_r(void);
> +void l2_cache_disable();
> +void l2_cache_enable();
please move these two funtcions in
include/asm-arm/cache.h

please rebase it against the u-boot-arm/next

Best Regards,
J.