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[108.18.137.133]) by smtp.googlemail.com with ESMTPSA id q13-20020ac8410d000000b002e1b59b2492sm9577997qtl.88.2022.03.20.16.41.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 20 Mar 2022 16:41:08 -0700 (PDT) Subject: Re: [PATCH v1 5/8] clk: imx: Add initial support for i.MXRT1170 clock driver To: Jesse Taube , u-boot@lists.denx.de Cc: sbabic@denx.de, festevam@gmail.com, festevam@denx.de, uboot-imx@nxp.com, giulio.benetti@benettiengineering.com, lukma@denx.de, sjg@chromium.org, jagan@amarulasolutions.com, kever.yang@rock-chips.com, andre.przywara@arm.com, pbrobinson@gmail.com, tharvey@gateworks.com, paul.liu@linaro.org, christianshewitt@gmail.com, samuel@sholland.org References: <20220317183300.315173-1-Mr.Bossman075@gmail.com> <20220317183300.315173-6-Mr.Bossman075@gmail.com> <5b364f05-25ac-18cd-4bb7-96121b808d5e@gmail.com> <59bf1d7f-361f-1b17-09c4-503d0ed61f4a@gmail.com> From: Sean Anderson Message-ID: <4a9bd496-0681-e9da-9004-e5499b2bb2f3@gmail.com> Date: Sun, 20 Mar 2022 19:41:07 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <59bf1d7f-361f-1b17-09c4-503d0ed61f4a@gmail.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On 3/20/22 6:45 PM, Jesse Taube wrote: >=20 >=20 > On 3/20/22 15:17, Sean Anderson wrote: >> On 3/17/22 2:32 PM, Jesse Taube wrote: >>> Add clock driver support for i.MXRT1170. >>> >>> Signed-off-by: Jesse Taube >>> --- >>> =C2=A0=C2=A0 drivers/clk/imx/Kconfig=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 |=C2=A0 16 +++ >>> =C2=A0=C2=A0 drivers/clk/imx/Makefile=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 |=C2=A0=C2=A0 1 + >>> =C2=A0=C2=A0 drivers/clk/imx/clk-imxrt1170.c | 215 ++++++++++++++++++= ++++++++++++++ >>> =C2=A0=C2=A0 3 files changed, 232 insertions(+) >>> =C2=A0=C2=A0 create mode 100644 drivers/clk/imx/clk-imxrt1170.c >>> >>> diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig >>> index 96721bcbf3..ae56603194 100644 >>> --- a/drivers/clk/imx/Kconfig >>> +++ b/drivers/clk/imx/Kconfig >>> @@ -100,3 +100,19 @@ config CLK_IMXRT1050 >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 select CLK_CCF >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 help >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 This enables support= clock driver for i.MXRT1050 platforms. >>> + >>> +config SPL_CLK_IMXRT1170 >>> +=C2=A0=C2=A0=C2=A0 bool "SPL clock support for i.MXRT1170" >>> +=C2=A0=C2=A0=C2=A0 depends on ARCH_IMXRT && SPL >>> +=C2=A0=C2=A0=C2=A0 select SPL_CLK >>> +=C2=A0=C2=A0=C2=A0 select SPL_CLK_CCF >>> +=C2=A0=C2=A0=C2=A0 help >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 This enables SPL DM/DTS support for c= lock driver in i.MXRT1170. >>> + >>> +config CLK_IMXRT1170 >>> +=C2=A0=C2=A0=C2=A0 bool "Clock support for i.MXRT1170" >>> +=C2=A0=C2=A0=C2=A0 depends on ARCH_IMXRT >>> +=C2=A0=C2=A0=C2=A0 select CLK >>> +=C2=A0=C2=A0=C2=A0 select CLK_CCF >>> +=C2=A0=C2=A0=C2=A0 help >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 This enables support clock driver for= i.MXRT1170 platforms. >>> diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile >>> index 01bbbdf3ae..3ed326739a 100644 >>> --- a/drivers/clk/imx/Makefile >>> +++ b/drivers/clk/imx/Makefile >>> @@ -19,3 +19,4 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) +=3D clk-imx8mp= =2Eo clk-pll14xx.o \ >>> =C2=A0=C2=A0 obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) +=3D clk-imxrt102= 0.o >>> =C2=A0=C2=A0 obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) +=3D clk-imxrt105= 0.o >>> +obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1170) +=3D clk-imxrt1170.o >>> diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-im= xrt1170.c >>> new file mode 100644 >>> index 0000000000..6ea46b6a52 >>> --- /dev/null >>> +++ b/drivers/clk/imx/clk-imxrt1170.c >>> @@ -0,0 +1,215 @@ >>> +// SPDX-License-Identifier: GPL-2.0+ >>> +/* >>> + * Copyright (C) 2022 >>> + * Author(s): Jesse Taube >>> + */ >>> + >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> +#include >>> + >>> +#include "clk.h" >>> + >>> +static ulong imxrt1170_clk_get_rate(struct clk *clk) >>> +{ >>> +=C2=A0=C2=A0=C2=A0 struct clk *c; >>> +=C2=A0=C2=A0=C2=A0 int ret; >>> + >>> +=C2=A0=C2=A0=C2=A0 debug("%s(#%lu)\n", __func__, clk->id); >> >> Consider dev_dbg() if you do a v2. >> >>> + >>> +=C2=A0=C2=A0=C2=A0 ret =3D clk_get_by_id(clk->id, &c); >>> +=C2=A0=C2=A0=C2=A0 if (ret) >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return ret; >>> + >>> +=C2=A0=C2=A0=C2=A0 return clk_get_rate(c); >>> +} >>> + >>> +static ulong imxrt1170_clk_set_rate(struct clk *clk, ulong rate) >>> +{ >>> +=C2=A0=C2=A0=C2=A0 struct clk *c; >>> +=C2=A0=C2=A0=C2=A0 int ret; >>> + >>> +=C2=A0=C2=A0=C2=A0 debug("%s(#%lu), rate: %lu\n", __func__, clk->id,= rate); >>> + >>> +=C2=A0=C2=A0=C2=A0 ret =3D clk_get_by_id(clk->id, &c); >>> +=C2=A0=C2=A0=C2=A0 if (ret) >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return ret; >>> + >>> +=C2=A0=C2=A0=C2=A0 return clk_set_rate(c, rate); >>> +} >>> + >>> +static int __imxrt1170_clk_enable(struct clk *clk, bool enable) >>> +{ >>> +=C2=A0=C2=A0=C2=A0 struct clk *c; >>> +=C2=A0=C2=A0=C2=A0 int ret; >>> + >>> +=C2=A0=C2=A0=C2=A0 debug("%s(#%lu) en: %d\n", __func__, clk->id, ena= ble); >>> + >>> +=C2=A0=C2=A0=C2=A0 ret =3D clk_get_by_id(clk->id, &c); >>> +=C2=A0=C2=A0=C2=A0 if (ret) >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return ret; >>> + >>> +=C2=A0=C2=A0=C2=A0 if (enable) >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ret =3D clk_enable(c); >>> +=C2=A0=C2=A0=C2=A0 else >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ret =3D clk_disable(c); >>> + >>> +=C2=A0=C2=A0=C2=A0 return ret; >>> +} >>> + >>> +static int imxrt1170_clk_disable(struct clk *clk) >>> +{ >>> +=C2=A0=C2=A0=C2=A0 return __imxrt1170_clk_enable(clk, 0); >>> +} >>> + >>> +static int imxrt1170_clk_enable(struct clk *clk) >>> +{ >>> +=C2=A0=C2=A0=C2=A0 return __imxrt1170_clk_enable(clk, 1); >>> +} >>> + >>> +static int imxrt1170_clk_set_parent(struct clk *clk, struct clk *par= ent) >>> +{ >>> +=C2=A0=C2=A0=C2=A0 struct clk *c, *cp; >>> +=C2=A0=C2=A0=C2=A0 int ret; >>> + >>> +=C2=A0=C2=A0=C2=A0 debug("%s(#%lu), parent: %lu\n", __func__, clk->i= d, parent->id); >>> + >>> +=C2=A0=C2=A0=C2=A0 ret =3D clk_get_by_id(clk->id, &c); >>> +=C2=A0=C2=A0=C2=A0 if (ret) >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return ret; >>> + >>> +=C2=A0=C2=A0=C2=A0 ret =3D clk_get_by_id(parent->id, &cp); >>> +=C2=A0=C2=A0=C2=A0 if (ret) >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return ret; >>> + >>> +=C2=A0=C2=A0=C2=A0 return clk_set_parent(c, cp); >>> +} >>> + >>> +static struct clk_ops imxrt1170_clk_ops =3D { >>> +=C2=A0=C2=A0=C2=A0 .set_rate =3D imxrt1170_clk_set_rate, >>> +=C2=A0=C2=A0=C2=A0 .get_rate =3D imxrt1170_clk_get_rate, >>> +=C2=A0=C2=A0=C2=A0 .enable =3D imxrt1170_clk_enable, >>> +=C2=A0=C2=A0=C2=A0 .disable =3D imxrt1170_clk_disable, >>> +=C2=A0=C2=A0=C2=A0 .set_parent =3D imxrt1170_clk_set_parent, >>> +}; >>> + >>> +static const char * const lpuart1_sels[] =3D {"rcosc48M_div2", "osc"= , "rcosc400M", "rcosc16M", >>> +"pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3"}; >>> +static const char * const gpt1_sels[] =3D {"rcosc48M_div2", "osc", "= rcosc400M", "rcosc16M", >>> +"pll3_div2", "pll1_div5", "pll3_pfd2", "pll3_pfd3"}; >>> +static const char * const usdhc1_sels[] =3D {"rcosc48M_div2", "osc",= "rcosc400M", "rcosc16M", >>> +"pll2_pfd2", "pll2_pfd0", "pll1_div5", "pll_arm"}; >>> +static const char * const semc_sels[] =3D {"rcosc48M_div2", "osc", "= rcosc400M", "rcosc16M", >>> +"pll1_div5", "pll2_sys", "pll2_pfd2", "pll3_pfd0"}; >>> + >>> +static int imxrt1170_clk_probe(struct udevice *dev) >>> +{ >>> +=C2=A0=C2=A0=C2=A0 void *base; >>> + >>> +=C2=A0=C2=A0=C2=A0 /* Anatop clocks */ >>> +=C2=A0=C2=A0=C2=A0 base =3D (void *)ofnode_get_addr(ofnode_by_compat= ible(ofnode_null(), "fsl,imxrt-anatop")); >> >> Where does this compatible come from? I don't see it in Linux or U-Boo= t. > It is slowly being merged into mainline it should be in linux-next soon= > Here is the imx8mm one in mainline > https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/frees= cale/imx8mm.dtsi#L577 > The rest of the imx family should move to this at some point. Hm, this sort of thing should really be a reference of some kind, but it appears that this is what all the other imx clocks do. --Sean >>> + >>> +=C2=A0=C2=A0=C2=A0 clk_dm(IMXRT1170_CLK_PLL_ARM, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 imx_clk= _pllv3(IMX_PLLV3_SYS, "pll_arm", "osc", >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 base + 0x200, 0xff)); >>> +=C2=A0=C2=A0=C2=A0 clk_dm(IMXRT1170_CLK_PLL3, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 imx_clk= _pllv3(IMX_PLLV3_GENERICV2, "pll3_sys", "osc", >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 base + 0x210, 1)); >>> +=C2=A0=C2=A0=C2=A0 clk_dm(IMXRT1170_CLK_PLL2, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 imx_clk= _pllv3(IMX_PLLV3_GENERICV2, "pll2_sys", "osc", >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 base + 0x240, 1)); >>> + >>> +=C2=A0=C2=A0=C2=A0 clk_dm(IMXRT1170_CLK_PLL3_PFD0, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 imx_clk= _pfd("pll3_pfd0", "pll3_sys", base + 0x230, 0)); >>> +=C2=A0=C2=A0=C2=A0 clk_dm(IMXRT1170_CLK_PLL3_PFD1, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 imx_clk= _pfd("pll3_pfd1", "pll3_sys", base + 0x230, 1)); >>> +=C2=A0=C2=A0=C2=A0 clk_dm(IMXRT1170_CLK_PLL3_PFD2, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 imx_clk= _pfd("pll3_pfd2", "pll3_sys", base + 0x230, 2)); >>> +=C2=A0=C2=A0=C2=A0 clk_dm(IMXRT1170_CLK_PLL3_PFD3, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 imx_clk= _pfd("pll3_pfd3", "pll3_sys", base + 0x230, 3)); >>> + >>> +=C2=A0=C2=A0=C2=A0 clk_dm(IMXRT1170_CLK_PLL2_PFD0, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 imx_clk= _pfd("pll2_pfd0", "pll2_sys", base + 0x270, 0)); >>> +=C2=A0=C2=A0=C2=A0 clk_dm(IMXRT1170_CLK_PLL2_PFD1, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 imx_clk= _pfd("pll2_pfd1", "pll2_sys", base + 0x270, 1)); >>> +=C2=A0=C2=A0=C2=A0 clk_dm(IMXRT1170_CLK_PLL2_PFD2, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 imx_clk= _pfd("pll2_pfd2", "pll2_sys", base + 0x270, 2)); >>> +=C2=A0=C2=A0=C2=A0 clk_dm(IMXRT1170_CLK_PLL2_PFD3, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 imx_clk= _pfd("pll2_pfd3", "pll2_sys", base + 0x270, 3)); >>> + >>> +=C2=A0=C2=A0=C2=A0 clk_dm(IMXRT1170_CLK_PLL3_DIV2, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 imx_clk= _fixed_factor("pll3_div2", "pll3_sys", 1, 2)); >>> + >>> +=C2=A0=C2=A0=C2=A0 /* CCM clocks */ >>> +=C2=A0=C2=A0=C2=A0 base =3D dev_read_addr_ptr(dev); >>> +=C2=A0=C2=A0=C2=A0 if (base =3D=3D (void *)FDT_ADDR_T_NONE) >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return -EINVAL; >>> + >>> +=C2=A0=C2=A0=C2=A0 clk_dm(IMXRT1170_CLK_LPUART1_SEL, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 imx_clk= _mux("lpuart1_sel", base + (25 * 0x80), 8, 3, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 lpuart1_sels, ARRAY_SIZE(lpuart1_sels))); >>> +=C2=A0=C2=A0=C2=A0 clk_dm(IMXRT1170_CLK_LPUART1, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 imx_clk= _divider("lpuart1", "lpuart1_sel", >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 base + (25 * 0x80), 0, 8)); >>> + >>> +=C2=A0=C2=A0=C2=A0 clk_dm(IMXRT1170_CLK_USDHC1_SEL, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 imx_clk= _mux("usdhc1_sel", base + (58 * 0x80), 8, 3, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 usdhc1_sels, ARRAY_SIZE(usdhc1_sels))); >>> +=C2=A0=C2=A0=C2=A0 clk_dm(IMXRT1170_CLK_USDHC1, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 imx_clk= _divider("usdhc1", "usdhc1_sel", >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 base + (58 * 0x80), 0, 8)); >>> + >>> +=C2=A0=C2=A0=C2=A0 clk_dm(IMXRT1170_CLK_GPT1_SEL, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 imx_clk= _mux("gpt1_sel", base + (14 * 0x80), 8, 3, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 gpt1_sels, ARRAY_SIZE(gpt1_sels))); >>> +=C2=A0=C2=A0=C2=A0 clk_dm(IMXRT1170_CLK_GPT1, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 imx_clk= _divider("gpt1", "gpt1_sel", >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 base + (14 * 0x80), 0, 8)); >>> + >>> +=C2=A0=C2=A0=C2=A0 clk_dm(IMXRT1170_CLK_SEMC_SEL, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 imx_clk= _mux("semc_sel", base + (4 * 0x80), 8, 3, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 semc_sels, ARRAY_SIZE(semc_sels))); >>> +=C2=A0=C2=A0=C2=A0 clk_dm(IMXRT1170_CLK_SEMC, >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 imx_clk= _divider("semc", "semc_sel", >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 base + (4 * 0x80), 0, 8)); >>> +=C2=A0=C2=A0=C2=A0 struct clk *clk, *clk1; >>> + >>> +=C2=A0=C2=A0=C2=A0 clk_get_by_id(IMXRT1170_CLK_PLL2, &clk); >>> +=C2=A0=C2=A0=C2=A0 clk_enable(clk); >>> +=C2=A0=C2=A0=C2=A0 clk_set_rate(clk, 528000000UL); >>> + >>> +=C2=A0=C2=A0=C2=A0 clk_get_by_id(IMXRT1170_CLK_PLL2_PFD2, &clk); >>> + >>> +=C2=A0=C2=A0=C2=A0 clk_get_by_id(IMXRT1170_CLK_SEMC_SEL, &clk1); >>> +=C2=A0=C2=A0=C2=A0 clk_enable(clk1); >>> +=C2=A0=C2=A0=C2=A0 clk_set_parent(clk1, clk); >>> + >>> +=C2=A0=C2=A0=C2=A0 clk_get_by_id(IMXRT1170_CLK_SEMC, &clk); >>> +=C2=A0=C2=A0=C2=A0 clk_enable(clk); >>> +=C2=A0=C2=A0=C2=A0 clk_set_rate(clk, 132000000UL); >>> + >>> +=C2=A0=C2=A0=C2=A0 clk_get_by_id(IMXRT1170_CLK_PLL3, &clk); >>> +=C2=A0=C2=A0=C2=A0 clk_enable(clk); >>> +=C2=A0=C2=A0=C2=A0 clk_set_rate(clk, 480000000UL); >> >> Can this be done using assigned-clock-(frequency|parent)? > Ah didn't relize U-Boot had this aswell. >>> +=C2=A0=C2=A0=C2=A0 return 0; >>> +} >>> + >>> +static const struct udevice_id imxrt1170_clk_ids[] =3D { >>> +=C2=A0=C2=A0=C2=A0 { .compatible =3D "fsl,imxrt1170-ccm" }, >>> +=C2=A0=C2=A0=C2=A0 { }, >>> +}; >>> + >>> +U_BOOT_DRIVER(imxrt1170_clk) =3D { >>> +=C2=A0=C2=A0=C2=A0 .name =3D "clk_imxrt1170", >>> +=C2=A0=C2=A0=C2=A0 .id =3D UCLASS_CLK, >>> +=C2=A0=C2=A0=C2=A0 .of_match =3D imxrt1170_clk_ids, >>> +=C2=A0=C2=A0=C2=A0 .ops =3D &imxrt1170_clk_ops, >>> +=C2=A0=C2=A0=C2=A0 .probe =3D imxrt1170_clk_probe, >>> +=C2=A0=C2=A0=C2=A0 .flags =3D DM_FLAG_PRE_RELOC, >>> +}; >>> >> >> --Sean