From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 43807C001DF for ; Tue, 1 Aug 2023 11:57:50 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E2A6086BC2; Tue, 1 Aug 2023 13:57:48 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1690891069; bh=QaEoLaWkxiGJZm0A+mD9TBwISQE2ZNUeu5ahDFfdU0o=; h=Date:Subject:To:Cc:References:From:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=omehl9+ohhZFmRgK8tcTXCCNOlREMle4+6X5sIJy4oj2z1TD6J1ZQA2ebdTDtacno jfm0jBwXfUEsFSPEGxd39zRHWXjeTKydvCRMVQaRAlnueK8G7qAEUldVP4glwQCXeA 8+JDazcw3s5i+5APLMaG+IUfNmFZzxfVchDdFukdVxXpSmrLCeaHKDCGHUX2f9Zmf1 CDs3ImrSLWkDpUKq4L/MyW0PCvSg40x+/x7GzLOJLQDfxsolQiQ7yHrMSojw283gk3 VvsQQcAM1ndptEKuS16YOCFee7M3XRVVUCdEofIuQw2A53qdCEye5kBE9//W0ucRN+ /2TgI5c6ndtyg== Received: from [127.0.0.1] (p578adb1c.dip0.t-ipconnect.de [87.138.219.28]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 8A8EF86B4D; Tue, 1 Aug 2023 13:57:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1690891067; bh=QaEoLaWkxiGJZm0A+mD9TBwISQE2ZNUeu5ahDFfdU0o=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=zQtPDJQt4tcS0IdaULKI2qiI2OQedEccONTXP8qItdysI8ay6SOjLA/YgQdc8nKLd WqAl1FcC+hmw5hubpHOhkUadUWiNbMXbSRSYDBRI59K+95y3UmgpOKLSMPfVFeSD06 sQNbHb0MvfE4zISi+IbRikCAWm92D0Md1vRHx0B/xtSwkPC2cBqDxdX5BoaP21yg2n uz9icUoifpABLQY/XCSQzAZtKOmYDZ4yR+bzGSDWW/lQQP3m7I/SqAyKeowvQYMtDx ghTfvrM/kjz8//Tbh6WiBiFw/qTy/1IiGXQ6K2k+mMnUVVgj0YKTuFzPK72WpZStXY lx+waI64V6ApQ== Message-ID: <4df8f13d-ab99-e751-3160-af7218b9f29b@denx.de> Date: Tue, 1 Aug 2023 13:44:00 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.1 Subject: Re: [PATCH v2 02/10] usb: dwc3: core: improve reset sequence Content-Language: en-US To: Eugen Hristev , kever.yang@rock-chips.com, u-boot@lists.denx.de Cc: jonas@kwiboo.se, jagan@edgeble.ai, kernel@collabora.com, Venkatesh Yadav Abbarapu , Tom Rini References: <20230801072811.10354-1-eugen.hristev@collabora.com> <20230801072811.10354-3-eugen.hristev@collabora.com> From: Marek Vasut In-Reply-To: <20230801072811.10354-3-eugen.hristev@collabora.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On 8/1/23 09:28, Eugen Hristev wrote: > From: Venkatesh Yadav Abbarapu > > [ Felipe: Ported from Linux kernel commit > f59dcab17629 ("usb: dwc3: core: improve reset sequence") ] > > According to Synopsys Databook, we shouldn't be relying on > GCTL.CORESOFTRESET bit as that's only for debugging purposes. > Instead, let's use DCTL.CSFTRST if we're OTG or PERIPHERAL mode. > > Host side block will be reset by XHCI driver if necessary. Note that this > reduces amount of time spent on dwc3_probe() by a long margin. > > We're still gonna wait for reset to finish for a long time > (default to 1ms max), but tests show that the reset polling loop executed > at most 19 times (modprobe dwc3 && modprobe -r dwc3 executed 1000 > times in a row). > > Without proper core reset, observing random issues like when the > USB(DWC3) is in device mode, the host device is not able to detect the > USB device. > > Signed-off-by: Venkatesh Yadav Abbarapu > [eugen.hristev@collabora.com: keep the PHY resets code] > Signed-off-by: Eugen Hristev NAK > --- > Not to be merged, I know Marek does not apply any patches to DWC3. That is not true and taken out of context. What needs to happen is, someone needs to sync the DWC3 with Linux instead of picking random subsets patches and turning the driver into a total unmaintainable mess, which will be horribly difficult to sync in the future due to these random patches mixed in the history. I explained how to do it to Xilinx, it is a trivial thing to do, but it seems they did not even bother to try the method.