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From: Fabian Cenedese <Cenedese@indel.ch>
To: u-boot@lists.denx.de
Subject: [U-Boot] P2020 L2 cache as SRAM
Date: Mon, 17 Jan 2011 09:07:54 +0100	[thread overview]
Message-ID: <5.2.0.9.1.20110117090223.049fede8@localhost> (raw)

Hi

We're trying to configure the PPC P2020 cpu to use the L2 cache
as SRAM so we can load the U-Boot code in there. However we
stumble into problems. Sometimes the cpu goes on trap when
trying to access this area. Sometimes there's no trap but we
seem to access a different area. That's probably a problem with
setting up a TLB/LAW.

Has anybody already done this and could share some code with
us?

I've seen that there's a mpc85xx branch with quite some work
going on. Where should we base our work on? Should we use
the master or is it better to use this branch? I'm used to svn,
not git, so there may be other options I don't know about yet.

Thanks

bye  Fabi

             reply	other threads:[~2011-01-17  8:07 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-01-17  8:07 Fabian Cenedese [this message]
2011-01-19  7:50 ` [U-Boot] P2020 L2 cache as SRAM Fabian Cenedese
2011-01-19 20:02   ` Scott Wood
2011-01-20  9:21     ` Fabian Cenedese
2011-10-19 11:53     ` DarkKhan
2011-10-19 12:12       ` Aggrwal Poonam-B10812

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