From mboxrd@z Thu Jan 1 00:00:00 1970 From: Fabian Cenedese Date: Mon, 17 Jan 2011 09:07:54 +0100 Subject: [U-Boot] P2020 L2 cache as SRAM Message-ID: <5.2.0.9.1.20110117090223.049fede8@localhost> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi We're trying to configure the PPC P2020 cpu to use the L2 cache as SRAM so we can load the U-Boot code in there. However we stumble into problems. Sometimes the cpu goes on trap when trying to access this area. Sometimes there's no trap but we seem to access a different area. That's probably a problem with setting up a TLB/LAW. Has anybody already done this and could share some code with us? I've seen that there's a mpc85xx branch with quite some work going on. Where should we base our work on? Should we use the master or is it better to use this branch? I'm used to svn, not git, so there may be other options I don't know about yet. Thanks bye Fabi