[U-Boot] P2020 L2 cache as SRAM

[Fabian Cenedese <Cenedese@indel.ch>]

>> >We're trying to configure the PPC P2020 cpu to use the L2 cache
>> >as SRAM so we can load the U-Boot code in there. However we
>> >stumble into problems. Sometimes the cpu goes on trap when
>> >trying to access this area. Sometimes there's no trap but we
>> >seem to access a different area. That's probably a problem with
>> >setting up a TLB/LAW.
>> >
>> >Has anybody already done this and could share some code with
>> >us?
>> >
>> >I've seen that there's a mpc85xx branch with quite some work
>> >going on. Where should we base our work on? Should we use
>> >the master or is it better to use this branch? I'm used to svn,
>> >not git, so there may be other options I don't know about yet.
>> 
>> I know you're busy with patches and releasing, I just wanted
>> to ask again if anybody has already done this.
>
>Yes, it's been done.  P1_P2_RDB does this when configured for NAND boot.
>
>Look for CONFIG_SYS_INIT_L2_ADDR.

Thanks for the hint. We have seen this and compared it to our
implementation which was based on the AN3646.pdf (chapter 4).
It seems that disabling the errors as done in cpu_init_nand.c
helps quite a bit. We've seen this code before but for some
reason that register got lost in the conversion to assembler.
So now it works fine.

Thanks.

bye  Fabi