[U-Boot] bdi3000 configurtio file for mpc8308RDB

[U-Boot] bdi3000 configurtio file for mpc8308RDB

[Avner Flesch]

Hi,

I need bdi3000 reg file and u-boot configuration file for MPB8308RDB
Where can I find those fies?

Thanks

Avner

[U-Boot] bdi3000 configurtio file for mpc8308RDB

[Wolfgang Denk]

Dear Avner Flesch,

In message <4A6F885E2BDE12468EC281BA9F1CB58F09067363@DBXPRD0610MB359.eurprd06.prod.outlook.com> you wrote:
>
> I need bdi3000 reg file and u-boot configuration file for MPB8308RDB
> Where can I find those fies?

The register files provided with the Abatron firmware are generic
enough. We used the reg8313e.def with the MPC7308RDB.

As for the config file, see the attachment.

Hope this helps.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"A complex system that works is invariably found to have evolved from
a simple system that worked."             - John Gall, _Systemantics_

-------------- next part --------------
; bdiGDB configuration file for MPC8308-RDB board
; -----------------------------------------------
;
[INIT]
; init core register
WREG		MSR	0x00001002	; MSR  : ME,RI
;
WSPR		311	0xFF400000	; set MMRBaseAddr 0xFF400000
; change internal MMR base from 0xff400000 (reset value) to 0xe0000000
WM32		0xff400000 0xe0000000	; IMMRBAR = 0xe0000000
WSPR		311	0xe0000000	; set MMRBaseAddr 0xe0000000

;#############################################
; System Configuration - Local Access Windows 
;#############################################

; Local Bus Local Access Windows
;################################
; WINDOW 0 - NOR FLASH
WM32 0xe0000020 0xfe000000 ; LBLAWBAR0  - begining at 0xfe000000 
WM32 0xe0000024 0x80000016 ; LBLAWAR0   - enable, size = 8MB 


;; ; WINDOW 1 - NAND Flash
;; WM32 0xe0000028 0xf8000000 ; LBLAWBAR1  - begining at 0xf8000000
;; WM32 0xe000002c 0x80000018 ; LBLAWAR1   - enable, size = 32MB 
;; 
;; ; WINDOW 2 - VSC7385
;; WM32 0xe0000030 0xf0000000 ; LBLAWBAR2  - begining at 0xfc100000
;; WM32 0xe0000034 0x80000010 ; LBLAWAR2   - enable, size = 128kB
;; 
;; ; WINDOW 3 - Read Write Buffer
;; ;WM32 0xe0000038 0xfa000000 ; LBLAWBAR3  - begining at 0xfa000000
;; ;WM32 0xe000003c 0x8000000e ; LBLAWAR3   - enable, size = 32kB
;; 
;; ; PCI Local Access Windows
;; ;################################
;; ; WINDOW 0
;; ;WM32 0xe0000060 0x80000000 ; PCILAWBAR0 - begining at 0x80000000
;; ;WM32 0xe0000064 0x8000001c ; PCILAWAR0  - enable, size = 512MB
;; 
;; ; WINDOW 1
;; ;WM32 0xe0000068 0xa0000000 ; PCILAWBAR1 - begining at 0xa0000000
;; ;WM32 0xe000006c 0x8000001c ; PCILAWAR1  - enable, size = 512MB
;; 
; DDR Local Access Windows
;################################
; WINDOW 0 - 1st DDR SODIMM
WM32 0xe00000a0 0x00000000 ; DDRLAWBAR0 - begining at 0x00000000
WM32 0xe00000a4 0x8000001a ; DDRLAWAR0  - enable, size = 128MB

;*********************************
; DDR2 Controller Registers
;*********************************

;DDRCDR
WM32 0xE0000128 0x73000002

; DDR_SDRAM_CLK_CNTL
; CLK_ADJST = b'010' ; 2 Clocks
WM32 0xE0002130 0x02000000

; CS0_BNDS
; SA0 = b'000000000000'
; EA0 = b'000000000111'
WM32 0xE0002000 0x00000007 ;; 128MB

; CS0_CONFIG
; CS_0_EN = b'1'
; AP_0_EN = b'1'
; ODT_RD_CFG = b'0'
; ODT_WR_CFG = b'1'
; BA_BITS_CS_0 = b'00'
; ROW_BITS_CS_0 = b'001' ; 13 row bits
; COL_BITS_CS_0 = b'010' ; 10 columns bits
WM32 0xE0002080 0x80840102

; TIMING_CFG_3
; EXT_REFREC = b'000' ; 0 Clocks
WM32 0xE0002100 0x00000000


; TIMING_CONFIG_1
; bit 1-3 = 2 - PRETOACT precharge activate interval 2 clock cycles
; bit 4-7 = 6 - ACTTOPRE activate to precharge interval 6 clock cycles
; bit 9-11 = 2 = ACTTORW activate to r/w interval 2 clock cycles 
; bit 13 - 15 = 5 - CASLAT CAS latency 3 clock cycles
; bit 16 - 19 = 6 - REFREC refresh recovery time 14 clock cycles 
; bit 21 - 23 = 2 - WRREC data to precharge interval 2 clock cycles 
; bit 25 - 27 = 2 - ACTTOACT activate to activate interval 2 clock cycles
; bit 29 - 31 = 2 - WRTORD write data to read command interval 2 clock cycles
WM32 0xe0002108 0x26256222

; TIMING_CONFIG_2
; bit 19-21  = b010  - WR_DATA_DELAY - 1/2 DRAM clock delay
WM32 0xe000210C 0x0f9028c7
; TIMING_CFG_0
; RWT = b'00' ; 0 Clocks
; WRT = b'00' ; 0 Clocks
; RRT = b'00' ; 0 Clocks
; WWT = b'00' ; 0 Clocks
; ACT_PD_EXIT = b'010' ; 2 Clocks
; PRE_PD_EXIT = b'010' ; 2 Clocks
; ODT_PD_EXIT = b'1000' ; 8 Clocks
; MRS_CYC = b'0010' ; 2 Clocks
WM32 0xE0002104 0x00220802

; DDR_SDRAM_CFG
; MEM_EN = b'0'
; SREN = b'1'
; RD_EN = b'0'
; SDRAM_TYPE = b'011'
; DYN_PWR = b'0'
; 32_BE = b'1'
; 8_BE = b'0'
; NCAP = b'0'
; 2T_EN = b'0'
; x32_EN = b'0'
; PCHB8 = b'0'
; HSE = b'0'
; MEM_HALT = b'0'
; BI = b'0'
WM32 0xE0002110 0x43080000

; DDR_SDRAM_CFG_2
; FRC_SR = b'0'
; DQS_CFG = b'00'
; ODT_CFG = b'10'
; NUM_PR = b'0001'
; D_INIT = b'0'
WM32 0xE0002114 0x00401000

; DDR_SDRAM_MODE
; Extended Mode Register: Outputs=0 or 1?
; Mode Register
WM32 0xE0002118 0x44400232

; DDR_SDRAM_MODE_2
; Extended Mode Register 2
; Extended Mode Register 3
WM32 0xE000211C 0x8000c000
	
; DDR_SDRAM_INTERVAL
; REFINT = 800 Clocks
; BSTOPRE = 100 Clocks
WM32 0xE0002124 0x03200064

;delay before enable
DELAY 300
;Enable: DDR_SDRAM_CFG
WM32 0xE0002110 0xc3080000


; MRTPR - refresh timer prescaler
WM32 0xe0005084 0x20000000 

;#############################################
; Local Bus Interface (LBIU) Configuration
;#############################################

; CS0 - 8MB NOR FLASH 
;WM32 0xe0005000 0xff801001 ; BR0 base address at 0xFF800000, port size 16 bit, GPCM, valid
WM32 0xe0005000 0xfe001001 ; BR0 base address at 0xFE000000, port size 16 bit, GPCM, valid
WM32 0xe0005004 0xff800ff7 ; OR0 8MB flash size, 15 w.s., timing relaxed

;; ; CS1 - NAND FLASH      10/4/2006 4:06PM
;; WM32      0xE0005008      0xF8000C21 ; BR2 base address at 0xF8000000, port size 8 bit, FCM, valid
;; WM32      0xE000500c      0xFFFF83CC ; OR2 32KB flash size, small page
;; 
;; ; CS2 - VSC7385
;; WM32 0xe0005010 0xf0000801 ; BR2 base address at 0xF0000000, port size 8 bit, GPCM, valid
;; WM32 0xe0005014 0xFFFE09FF ; OR2 128KB
;; 
;; ; CS3 - Read Write Buffer
;; ;WM32 0xe0005018 0xfa000801 ; BR3 base address at 0xfa000000, port size 8 bit, GPCM, valid
;; ;WM32 0xe000501c 0xFFFF8FF7 ; OR3 32KB
;; 
; LBCR - local bus enable
WM32 0xe00050d0 0x00000000

; LCRR
; bit 14 - 15 = 0b11 - EADC - 3 external address delay cycles 
; bit 28 - 31 = 0x0010  - CLKDIV - system clock:memory bus clock = 2
WM32 0xe00050d4 0x00030002
; WM32 0xe00050d4 0x00010002

;WM32 0xE0000800 0x00000000 ; ACR - Enable Core


;; ;WM32 0xfa000000 0x00000000 ; write board LEDs
;; 
;; ;
;; ; NAND Flash settings
;; ;
;; WM32      0xE00050E0      0x0000E000 ; FMR


[TARGET]
CPUTYPE		8313			;the CPU type
JTAGCLOCK	0			;use 16 MHz JTAG clock
POWERUP		2000			;start delay after power-up detected in ms
WAKEUP		500			;give reset time to complete
STARTUP		RESET			;halt immediately at the boot vector
RCW		0xa0606c00 0x44060000	;override reset configuration words
;BOOTADDR	0xfff00100		;boot address used for start-up break
BOOTADDR	0x00000100		;boot address used for start-up break
BREAKMODE	HARD			;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE	HWBP			;TRACE or HWBP, HWBP uses a hardware breakpoint
VECTOR		NOCATCH


[HOST]
IP		192.168.1.1
FILE		mpc8308rdb/u-boot.bin
FORMAT		BIN 0x10000
LOAD		MANUAL	;load code MANUAL or AUTO after reset
PROMPT		8308>

[FLASH]
CHIPTYPE	AM29BX16	;Flash type: MX29LV640BTTC-90G
CHIPSIZE	0x1000000	;The size of one flash chip in bytes
BUSWIDTH	16		;The width of the flash memory bus in bits (8 | 16 | 32 | 64)
WORKSPACE	0x00001000	;workspace in DDR RAM
FILE		mpc8308rdb/u-boot.bin
FORMAT		BIN 0xfe000000
;ERASE		0xfe100000	;erase sector 8
;ERASE		0xfe120000	;erase sector 9
;ERASE		0xfe140000	;erase sector 10
;ERASE		0xfe160000	;erase sector 11
ERASE		0xfe000000 0x10000 6 ; erase 6 sectors


[REGS]
FILE		BDI2000/reg8313e.def

[U-Boot] bdi3000 configurtio file for mpc8308RDB

[David Hawkins]

Hi Wolfgang and Avner (and the Freescale developers),

>> I need bdi3000 reg file and u-boot configuration file for MPB8308RDB
>> Where can I find those fies?
>
> The register files provided with the Abatron firmware are generic
> enough. We used the reg8313e.def with the MPC7308RDB.
>
> As for the config file, see the attachment.

I've just purchased a couple of these boards, so thanks for the
configuration file Wolfgang.

I'm planning on using this processor as a PCIe end-point in
a CompactPCI Serial (CPCI-S.0) board.

I used the MPC8349EA on the CompactPCI incarnation of this type
of hardware (based on Wolfgang's recommendation of the part):

http://www.ovro.caltech.edu/~dwh/carma_board/

Ira Snyder worked on the U-Boot and PowerPC code, and he's pushed
all the work we've done into the mainline U-Boot and Linux trees,
i.e., we give back to the community :)

The MPC8308 processor will essentially act as a PCI Express bridge
to some data processing FPGAs.

Grazing through the MPC8308 errata, there don't appear to be any
major 'gotchas' with this part. The local bus is not multiplexed,
so I'll need some minor changes to my UPM bridge logic, but
other than that it looks very similar to the MPC8349EA.

Has anyone had any bad experiences with this part, or is there
some 'feature' of the part I should be aware of?

Just looking for comments/feedback.

Thanks!

Cheers,
Dave

[U-Boot] bdi3000 configurtio file for mpc8308RDB

[Kim Phillips]

On Thu, 26 Jul 2012 10:05:46 -0700
David Hawkins <dwh@ovro.caltech.edu> wrote:

> Has anyone had any bad experiences with this part, or is there
> some 'feature' of the part I should be aware of?

it has a different DMA engine than the rest of the mpc8xxx parts.
Ilya Yanok added support for it - see Linux commit ba2eea2,
drivers/dma/mpc512x_dma.c.

Kim

[U-Boot] bdi3000 configurtio file for mpc8308RDB

[Wolfgang Denk]

Dear David Hawkins,

In message <501178EA.6050701@ovro.caltech.edu> you wrote:
>
> Grazing through the MPC8308 errata, there don't appear to be any
> major 'gotchas' with this part. ...

... not unless you try to use USB device mode.

> Has anyone had any bad experiences with this part, or is there
> some 'feature' of the part I should be aware of?

USB device mode doesn't work reliably, and FSL was never able or
willing to come up with a solution.  When this issue happens, the USB
device controller not only returns a truncated packet to the gadget
driver, but doesn't report URB completion to the host either.  The
host never gets an URB complete event, so you will see first a delay,
and then the host resets the device.  The issue can be reproduced with
massive writes to a mass-storage device.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Human beings were created by water to transport it uphill.

[U-Boot] bdi3000 configurtio file for mpc8308RDB

[David Hawkins]

Hi Wolfgang,

>> Grazing through the MPC8308 errata, there don't appear to be any
>> major 'gotchas' with this part. ...
>
> ... not unless you try to use USB device mode.

Ah, that is a gotcha then.

>> Has anyone had any bad experiences with this part, or is there
>> some 'feature' of the part I should be aware of?
>
> USB device mode doesn't work reliably, and FSL was never able or
> willing to come up with a solution.  When this issue happens, the USB
> device controller not only returns a truncated packet to the gadget
> driver, but doesn't report URB completion to the host either.  The
> host never gets an URB complete event, so you will see first a delay,
> and then the host resets the device.  The issue can be reproduced with
> massive writes to a mass-storage device.

The CPCI-S.0 specification defines USB, Ethernet, and PCIe over the
backplane.

We're going to use Ethernet for monitor/control traffic, and
PCIe for data transfers.

I had planned on using the PowerPC USB interface to implement at
least some form of 'USB device' communication with the board,
eg., something like USB-to-Serial or CDC class.

In your opinion, is MPC8308 USB Device Mode completely broken?

If that is the case, then if I want a UART over CPCI-S.0 USB,
I can use an FTDI FT245/FT232 on the CPCI-S.0 USB interface and
wire it into either a PowerPC UART or the system control FPGA.

How about USB Host mode? The board will communicate with a rear
transition module (another board plugged in from the rear side
of the chassis). If MPC8308 USB Host Mode is reliable, then I can
wire the USB interface through the backplane for use on the
RTM, eg., for talking to an FT245/232 device or a USB microcontroller.

Thanks for the valuable feedback.

Cheers,
Dave

[U-Boot] bdi3000 configurtio file for mpc8308RDB

[David Hawkins]

Hi Kim,

>> Has anyone had any bad experiences with this part, or is there
>> some 'feature' of the part I should be aware of?
>
> it has a different DMA engine than the rest of the mpc8xxx parts.
> Ilya Yanok added support for it - see Linux commit ba2eea2,
> drivers/dma/mpc512x_dma.c.

Thanks.

I'd noted that it did not have the external DMA pins that
the MPC8349EA has. However, I believe that I can live with
that. We had used those pins for flow control with an
FPGA configuration controller. However, I can do that with
an interrupt if need be.

Ira - could you please take a look at the DMA controller
and see if you think it'll work for us.

Cheers,
Dave

[U-Boot] bdi3000 configurtio file for mpc8308RDB

[Wolfgang Denk]

Dear David Hawkins,

In message <50118FE1.2000806@ovro.caltech.edu> you wrote:
> 
> In your opinion, is MPC8308 USB Device Mode completely broken?

Define completely...

When acting as a mass storage device, we saw some ~14 MB/s throughput
to the device when the bug did not trigger;  when it did, we got 1.8
MB/s and less, and many device reset messages in the system logs.

> How about USB Host mode? The board will communicate with a rear
> transition module (another board plugged in from the rear side
> of the chassis). If MPC8308 USB Host Mode is reliable, then I can
> wire the USB interface through the backplane for use on the
> RTM, eg., for talking to an FT245/232 device or a USB microcontroller.

Host mode workes fine.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If some day we are defeated, well, war has  its  fortunes,  good  and
bad.
	-- Commander Kor, "Errand of Mercy", stardate 3201.7

[U-Boot] bdi3000 configurtio file for mpc8308RDB

[David Hawkins]

Hi Wolfgang,

>> In your opinion, is MPC8308 USB Device Mode completely broken?
>
> Define completely...

:)

> When acting as a mass storage device, we saw some ~14 MB/s throughput
> to the device when the bug did not trigger;  when it did, we got 1.8
> MB/s and less, and many device reset messages in the system logs.

Ok, that sounds annoying enough that I won't bother to support
the MPC8308 device mode down the backplane.

>> How about USB Host mode? The board will communicate with a rear
>> transition module (another board plugged in from the rear side
>> of the chassis). If MPC8308 USB Host Mode is reliable, then I can
>> wire the USB interface through the backplane for use on the
>> RTM, eg., for talking to an FT245/232 device or a USB microcontroller.
>
> Host mode works fine.

Great! I'll put a USB3300 PHY on the board, and run the
USB over to the RTM.

Thanks for sharing your experiences, its much appreciated.

Cheers,
Dave

[U-Boot] bdi3000 configurtio file for mpc8308RDB

[Wolfgang Denk]

Dear Avner Flesch,

In message <4A6F885E2BDE12468EC281BA9F1CB58F0906A782@DBXPRD0610MB359.eurprd06.prod.outlook.com> you wrote:
> 
> Thank you very much.
> Unfortunately , the only register file I have is for mpc8xx, I'll appreciate it very much
> if you will also attach the reg8313e.def you have

It appears you have only the BDI firmware for the MPC8xx family of
processors then.  You will have to get "gdbcop21.zip" (BDI2000) resp.
"gdbcop30.zip" (BDI3000) from Abatron (current version is v1.33 of
February 1, 2012).

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
######## This message was made from 100% recycled electrons. ########