[U-Boot] [PATCH v2] Add support for Bluegiga APX4 Development Kit

Lauri Hintsala
2012-07-31T07:51:12Z

Hello Stefano,

Could you review the patch?

Thanks!

Best Regards,
Lauri Hintsala

On 07/09/2012 04:14 PM, Veli-Pekka Peltola wrote:
> This adds support for Bluegiga APX4 Development Kit. It is built around
> Freescale i.MX28. Currently supported features are: ethernet, I2C, MMC,
> RTC and USB. APX4 has only one ethernet port.
>
> Signed-off-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
> Signed-off-by: Lauri Hintsala <lauri.hintsala@bluegiga.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> Changes after v1 from last December:
> - Updating MAINTAINERS file which I missed last time
> - Started to use SPL
> - Increased size of environment on NAND
> - Better commit message
>
> Our strategy to use fuses differs from other i.MX28 based boards. We store
> serial number to CUST3. We don't have ethernet MAC address on fuses so our
> customers could use their own address range. If I have some time later this
> week or next week, I will do some refactorization on that so we could have
> generic OTP reading function.
>
> MAINTAINERS | 4 +
> board/bluegiga/apx4devkit/Makefile | 47 +++++++
> board/bluegiga/apx4devkit/apx4devkit.c | 150 ++++++++++++++++++++
> board/bluegiga/apx4devkit/spl_boot.c | 164 ++++++++++++++++++++++
> board/bluegiga/apx4devkit/u-boot.bd | 14 ++
> boards.cfg | 1 +
> include/configs/apx4devkit.h | 238 ++++++++++++++++++++++++++++++++
> 7 files changed, 618 insertions(+)
> create mode 100644 board/bluegiga/apx4devkit/Makefile
> create mode 100644 board/bluegiga/apx4devkit/apx4devkit.c
> create mode 100644 board/bluegiga/apx4devkit/spl_boot.c
> create mode 100644 board/bluegiga/apx4devkit/u-boot.bd
> create mode 100644 include/configs/apx4devkit.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 54eeab7..5c3fc6e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -784,6 +784,10 @@ Linus Walleij <linus.walleij@linaro.org>
> integratorap various
> integratorcp various
>
> +Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
> +
> + apx4devkit i.MX28
> +
> Luka Perkov <uboot@lukaperkov.net>
>
> ib62x0 ARM926EJS
> diff --git a/board/bluegiga/apx4devkit/Makefile b/board/bluegiga/apx4devkit/Makefile
> new file mode 100644
> index 0000000..68ab8f3
> --- /dev/null
> +++ b/board/bluegiga/apx4devkit/Makefile
> @@ -0,0 +1,47 @@
> +#
> +# (C) Copyright 2000-2006
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(BOARD).o
> +
> +ifndef CONFIG_SPL_BUILD
> +COBJS := apx4devkit.o
> +else
> +COBJS := spl_boot.o
> +endif
> +
> +SRCS := $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS))
> +
> +$(LIB): $(obj).depend $(OBJS)
> + $(call cmd_link_o_target, $(OBJS))
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/bluegiga/apx4devkit/apx4devkit.c b/board/bluegiga/apx4devkit/apx4devkit.c
> new file mode 100644
> index 0000000..c89c6aa
> --- /dev/null
> +++ b/board/bluegiga/apx4devkit/apx4devkit.c
> @@ -0,0 +1,150 @@
> +/*
> + * Bluegiga APX4 Development Kit
> + *
> + * Copyright (C) 2012 Bluegiga Technologies Oy
> + *
> + * Authors:
> + * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
> + * Lauri Hintsala <lauri.hintsala@bluegiga.com>
> + *
> + * Based on m28evk.c:
> + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
> + * on behalf of DENX Software Engineering GmbH
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <common.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/iomux-mx28.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/sys_proto.h>
> +#include <linux/mii.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +#include <errno.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/* Functions */
> +int board_early_init_f(void)
> +{
> + /* IO0 clock at 480MHz */
> + mx28_set_ioclk(MXC_IOCLK0, 480000);
> + /* IO1 clock at 480MHz */
> + mx28_set_ioclk(MXC_IOCLK1, 480000);
> +
> + /* SSP0 clock at 96MHz */
> + mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
> +
> + return 0;
> +}
> +
> +int dram_init(void)
> +{
> + return mx28_dram_init();
> +}
> +
> +int board_init(void)
> +{
> + /* Adress of boot parameters */
> + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_CMD_MMC
> +int board_mmc_init(bd_t *bis)
> +{
> + return mxsmmc_initialize(bis, 0, NULL);
> +}
> +#endif
> +
> +
> +#ifdef CONFIG_CMD_NET
> +
> +#define MII_PHY_CTRL2 0x1f
> +int fecmxc_mii_postcall(int phy)
> +{
> + /* change PHY RMII clock to 50MHz */
> + miiphy_write("FEC", 0, MII_PHY_CTRL2, 0x8180);
> +
> + return 0;
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> + int ret;
> + struct eth_device *dev;
> +
> + ret = cpu_eth_init(bis);
> + if (ret) {
> + printf("FEC MXS: Unable to init FEC clocks\n");
> + return ret;
> + }
> +
> + ret = fecmxc_initialize(bis);
> + if (ret) {
> + printf("FEC MXS: Unable to init FEC\n");
> + return ret;
> + }
> +
> + dev = eth_get_dev_by_name("FEC");
> + if (!dev) {
> + printf("FEC MXS: Unable to get FEC device entry\n");
> + return -EINVAL;
> + }
> +
> + ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
> + if (ret) {
> + printf("FEC MXS: Unable to register FEC MII postcall\n");
> + return ret;
> + }
> +
> + return ret;
> +}
> +#endif
> +
> +#ifdef CONFIG_SERIAL_TAG
> +#define MXS_OCOTP_MAX_TIMEOUT 1000000
> +void get_board_serial(struct tag_serialnr *serialnr)
> +{
> + struct mx28_ocotp_regs *ocotp_regs =
> + (struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
> +
> + serialnr->high = 0;
> + serialnr->low = 0;
> +
> + writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
> +
> + if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
> + MXS_OCOTP_MAX_TIMEOUT)) {
> + printf("MXS: Can't get serial number from OCOTP\n");
> + return;
> + }
> +
> + serialnr->low = readl(&ocotp_regs->hw_ocotp_cust3);
> +}
> +#endif
> +
> +#ifdef CONFIG_REVISION_TAG
> +u32 get_board_rev(void)
> +{
> + if (getenv("revision#") != NULL)
> + return simple_strtoul(getenv("revision#"), NULL, 10);
> + return 0;
> +}
> +#endif
> diff --git a/board/bluegiga/apx4devkit/spl_boot.c b/board/bluegiga/apx4devkit/spl_boot.c
> new file mode 100644
> index 0000000..53e20da
> --- /dev/null
> +++ b/board/bluegiga/apx4devkit/spl_boot.c
> @@ -0,0 +1,164 @@
> +/*
> + * Bluegiga APX4 Development Kit
> + *
> + * Copyright (C) 2012 Bluegiga Technologies Oy
> + *
> + * Authors:
> + * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
> + * Lauri Hintsala <lauri.hintsala@bluegiga.com>
> + *
> + * Based on spl_boot.c:
> + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
> + * on behalf of DENX Software Engineering GmbH
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <common.h>
> +#include <config.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +#include <asm/arch/iomux-mx28.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/sys_proto.h>
> +
> +#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
> +#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
> +#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
> +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
> +
> +const iomux_cfg_t iomux_setup[] = {
> + /* DUART */
> + MX28_PAD_PWM0__DUART_RX,
> + MX28_PAD_PWM1__DUART_TX,
> +
> + /* LED */
> + MX28_PAD_PWM3__GPIO_3_28,
> +
> + /* MMC0 */
> + MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
> + MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
> + MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
> + MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
> + MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
> + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
> + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL),
> + MX28_PAD_SSP0_SCK__SSP0_SCK |
> + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
> +
> + /* GPMI NAND */
> + MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
> + MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
> + MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
> + MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
> + MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
> + MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
> + MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
> + MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
> + MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
> + MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
> + MX28_PAD_GPMI_RDN__GPMI_RDN |
> + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
> + MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
> + MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
> + MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
> + MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
> +
> + /* FEC0 */
> + MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
> + MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
> + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
> + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
> + MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
> + MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
> + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
> + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
> + MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
> +
> + /* I2C */
> + MX28_PAD_I2C0_SCL__I2C0_SCL,
> + MX28_PAD_I2C0_SDA__I2C0_SDA,
> +
> + /* EMI */
> + MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
> +
> + MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
> + MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
> +};
> +
> +void board_init_ll(void)
> +{
> + mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
> +
> + /* switch LED on */
> + gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
> +}
> +
> +void mx28_adjust_memory_params(uint32_t *dram_vals)
> +{
> + /*
> + * All address lines are routed from CPU to memory chip.
> + * ADDR_PINS field is set to zero.
> + */
> + dram_vals[0x74 >> 2] = 0x0f02000a;
> +
> + /* Used memory has 4 banks. EIGHT_BANK_MODE bit is disabled. */
> + dram_vals[0x7c >> 2] = 0x00000101;
> +}
> diff --git a/board/bluegiga/apx4devkit/u-boot.bd b/board/bluegiga/apx4devkit/u-boot.bd
> new file mode 100644
> index 0000000..c60615a
> --- /dev/null
> +++ b/board/bluegiga/apx4devkit/u-boot.bd
> @@ -0,0 +1,14 @@
> +sources {
> + u_boot_spl="spl/u-boot-spl.bin";
> + u_boot="u-boot.bin";
> +}
> +
> +section (0) {
> + load u_boot_spl > 0x0000;
> + load ivt (entry = 0x0014) > 0x8000;
> + hab call 0x8000;
> +
> + load u_boot > 0x40000100;
> + load ivt (entry = 0x40000100) > 0x8000;
> + hab call 0x8000;
> +}
> diff --git a/boards.cfg b/boards.cfg
> index 1a5dcab..b1297bb 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -170,6 +170,7 @@ tx25 arm arm926ejs tx25 karo
> zmx25 arm arm926ejs zmx25 syteco mx25
> imx27lite arm arm926ejs imx27lite logicpd mx27
> magnesium arm arm926ejs imx27lite logicpd mx27
> +apx4devkit arm arm926ejs - bluegiga mx28
> m28evk arm arm926ejs - denx mx28
> mx28evk arm arm926ejs - freescale mx28
> nhk8815 arm arm926ejs nhk8815 st nomadik
> diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h
> new file mode 100644
> index 0000000..9e7ead5
> --- /dev/null
> +++ b/include/configs/apx4devkit.h
> @@ -0,0 +1,238 @@
> +/*
> + * Copyright (C) 2012 Bluegiga Technologies Oy
> + *
> + * Authors:
> + * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
> + * Lauri Hintsala <lauri.hintsala@bluegiga.com>
> + *
> + * Based on m28evk.h:
> + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
> + * on behalf of DENX Software Engineering GmbH
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#include <asm/arch/regs-base.h>
> +
> +/* SoC configurations */
> +#define CONFIG_MX28 /* i.MX28 SoC */
> +#define CONFIG_MXS_GPIO /* GPIO control */
> +#define CONFIG_SYS_HZ 1000 /* Ticks per second */
> +
> +#define MACH_TYPE_APX4DEVKIT 3712
> +#define CONFIG_MACH_TYPE MACH_TYPE_APX4DEVKIT
> +
> +#define CONFIG_SYS_NO_FLASH
> +#define CONFIG_SYS_ICACHE_OFF
> +#define CONFIG_SYS_DCACHE_OFF
> +#define CONFIG_BOARD_EARLY_INIT_F
> +#define CONFIG_ARCH_CPU_INIT
> +#define CONFIG_ARCH_MISC_INIT
> +
> +/* SPL */
> +#define CONFIG_SPL
> +#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
> +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mx28"
> +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds"
> +#define CONFIG_SPL_LIBCOMMON_SUPPORT
> +#define CONFIG_SPL_LIBGENERIC_SUPPORT
> +#define CONFIG_SPL_GPIO_SUPPORT
> +
> +/* U-Boot Commands */
> +#include <config_cmd_default.h>
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DOS_PARTITION
> +
> +#define CONFIG_CMD_CACHE
> +#define CONFIG_CMD_DATE
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_EXT2
> +#define CONFIG_CMD_FAT
> +#define CONFIG_CMD_I2C
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_MMC
> +#define CONFIG_CMD_NAND
> +#define CONFIG_CMD_NET
> +#define CONFIG_CMD_NFS
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_SAVEENV
> +#define CONFIG_CMD_USB
> +
> +/* Memory configurations */
> +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
> +#define PHYS_SDRAM_1 0x40000000 /* Base address */
> +#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
> +#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
> +#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
> +#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
> +
> +/* Point initial SP in SRAM so SPL can use it too. */
> +#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
> +#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +/*
> + * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
> + * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
> + * binary. In case there was more of this mess, 0x100 bytes are skipped.
> + */
> +#define CONFIG_SYS_TEXT_BASE 0x40000100
> +
> +#define CONFIG_ENV_OVERWRITE
> +
> +/* U-Boot general configurations */
> +#define CONFIG_SYS_LONGHELP
> +#define CONFIG_SYS_PROMPT "=> "
> +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
> +#define CONFIG_SYS_PBSIZE \
> + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> + /* Print buffer size */
> +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
> + /* Boot argument buffer size */
> +#define CONFIG_VERSION_VARIABLE /* U-Boot version */
> +#define CONFIG_AUTO_COMPLETE /* Command auto complete */
> +#define CONFIG_CMDLINE_EDITING /* Command history etc. */
> +#define CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +#define CONFIG_OF_LIBFDT
> +#define CONFIG_ENV_IS_IN_NAND
> +
> +/* Serial Driver */
> +#define CONFIG_PL011_SERIAL
> +#define CONFIG_PL011_CLOCK 24000000
> +#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
> +#define CONFIG_CONS_INDEX 0
> +#define CONFIG_BAUDRATE 115200 /* Default baud rate */
> +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
> +
> +/* DMA */
> +#define CONFIG_APBH_DMA
> +
> +/* MMC Driver */
> +#ifdef CONFIG_ENV_IS_IN_MMC
> +#define CONFIG_ENV_OFFSET (256 * 1024)
> +#define CONFIG_ENV_SIZE (16 * 1024)
> +#define CONFIG_SYS_MMC_ENV_DEV 0
> +#endif
> +
> +#ifdef CONFIG_CMD_MMC
> +#define CONFIG_MMC
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_MMC_BOUNCE_BUFFER
> +#define CONFIG_MXS_MMC
> +#endif
> +
> +/* NAND Driver */
> +#ifdef CONFIG_ENV_IS_IN_NAND
> +#define CONFIG_ENV_SECT_SIZE (128 * 1024)
> +#define CONFIG_ENV_SIZE (128 * 1024)
> +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
> +#define CONFIG_ENV_RANGE (384 * 1024)
> +#define CONFIG_ENV_OFFSET 0x120000
> +#define CONFIG_ENV_OFFSET_REDUND \
> + (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
> +#endif
> +
> +#ifdef CONFIG_CMD_NAND
> +#define CONFIG_NAND_MXS
> +#define CONFIG_SYS_MAX_NAND_DEVICE 1
> +#define CONFIG_SYS_NAND_BASE 0x60000000
> +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
> +
> +#define CONFIG_CMD_UBI
> +#define CONFIG_CMD_UBIFS
> +#define CONFIG_CMD_MTDPARTS
> +#define CONFIG_RBTREE
> +#define CONFIG_LZO
> +#define CONFIG_MTD_DEVICE
> +#define CONFIG_MTD_PARTITIONS
> +#define MTDIDS_DEFAULT "nand0=gpmi-nand"
> +#define MTDPARTS_DEFAULT \
> + "mtdparts=gpmi-nand:128k(bootstrap),1024k(boot),768k(env),-(root)"
> +#else
> +#define MTDPARTS_DEFAULT ""
> +#endif
> +
> +/* Ethernet on SOC (FEC) */
> +#ifdef CONFIG_CMD_NET
> +#define CONFIG_NET_MULTI
> +#define CONFIG_ETHPRIME "FEC"
> +#define CONFIG_FEC_MXC
> +#define CONFIG_FEC_MXC_PHYADDR 0
> +#define IMX_FEC_BASE MXS_ENET0_BASE
> +#define CONFIG_MII
> +#define CONFIG_DISCOVER_PHY
> +#define CONFIG_FEC_XCV_TYPE RMII
> +#endif
> +
> +/* USB */
> +#ifdef CONFIG_CMD_USB
> +#define CONFIG_USB_EHCI
> +#define CONFIG_USB_EHCI_MXS
> +#define CONFIG_EHCI_MXS_PORT 1
> +#define CONFIG_EHCI_IS_TDI
> +#define CONFIG_USB_STORAGE
> +#endif
> +
> +/* I2C */
> +#ifdef CONFIG_CMD_I2C
> +#define CONFIG_I2C_MXS
> +#define CONFIG_HARD_I2C
> +#define CONFIG_SYS_I2C_SPEED 400000
> +#endif
> +
> +/* RTC */
> +#if defined(CONFIG_CMD_DATE)
> +#define CONFIG_RTC_PCF8563
> +#define CONFIG_SYS_I2C_RTC_ADDR 0x51
> +#endif
> +
> +/* Boot Linux */
> +#define CONFIG_CMDLINE_TAG
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_BOOTDELAY 1
> +#define CONFIG_BOOTFILE "uImage"
> +#define CONFIG_BOOTCOMMAND "run bootcmd_nand"
> +#define CONFIG_LOADADDR 0x41000000
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +#define CONFIG_SERIAL_TAG
> +#define CONFIG_REVISION_TAG
> +
> +/* Extra Environments */
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "mtdparts=" MTDPARTS_DEFAULT "\0" \
> + "verify=no\0" \
> + "bootcmd=run bootcmd_nand\0" \
> + "kernelargs=console=tty0 console=ttyAMA0,115200 consoleblank=0\0" \
> + "bootargs_nand=" \
> + "setenv bootargs ${kernelargs} ubi.mtd=3,2048 " \
> + "root=ubi0:rootfs rootfstype=ubifs ${mtdparts} rw\0" \
> + "bootcmd_nand=" \
> + "run bootargs_nand && ubi part root 2048 && " \
> + "ubifsmount rootfs && ubifsload 41000000 boot/uImage && " \
> + "bootm 41000000\0" \
> + "bootargs_mmc=" \
> + "setenv bootargs ${kernelargs} " \
> + "root=/dev/mmcblk0p2 rootwait ${mtdparts} rw\0" \
> + "bootcmd_mmc=" \
> + "run bootargs_mmc && mmc rescan && " \
> + "ext2load mmc 0:2 41000000 boot/uImage && bootm 41000000\0" \
> +""
> +
> +#endif /* __CONFIG_H */
>