[U-Boot] [PATCH 0/17]: Improve am33xx support

[U-Boot] [PATCH 0/17]: Improve am33xx support

[Tom Rini]

Hey all,

The following series of patches improves am33xx support, and cleans up
omap3/4/5 slightly.  The slight cleanup to omap3/4/5 is that we can all
share a single function to see if we are executing in SDRAM or not.  The
rest of the series cleans up the EMIF code for am33xx.  While I had
hoped to be able to re-use the omap4/5 code as the EMIF unit is the same
block, it's simply wired up too differently to reuse the same codebase.
We can however reuse the register structs so some of the commits here
are about changing to use that.  There's also bugfixes to the DDR2 init
sequence and cleanups that will make adding DDR3 support easier.  I also
update the am335x_evm config to be like a "normal" board and support
common commands and booting Linux.

-- 
Tom

[U-Boot] [PATCH 01/17] omap3/omap4/omap5/am33xx: Use a common running_from_sdram function

[Tom Rini]

On all OMAP3+ platforms we know that SDRAM starts at 0x80000000 and we
can use 0xD0000000 as the end.

Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/omap3/board.c            |    4 ++--
 arch/arm/cpu/armv7/omap3/sys_info.c         |   12 ------------
 arch/arm/include/asm/arch-omap3/sys_proto.h |    1 -
 arch/arm/include/asm/arch-omap4/omap.h      |    5 -----
 arch/arm/include/asm/arch-omap4/sys_proto.h |    8 --------
 arch/arm/include/asm/arch-omap5/omap.h      |    5 -----
 arch/arm/include/asm/arch-omap5/sys_proto.h |    8 --------
 arch/arm/include/asm/omap_common.h          |   14 ++++++++++++++
 8 files changed, 16 insertions(+), 41 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index f2e52e9..7639bdd 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -177,7 +177,7 @@ void secureworld_exit()
 void try_unlock_memory()
 {
 	int mode;
-	int in_sdram = is_running_in_sdram();
+	int in_sdram = running_from_sdram();
 
 	/*
 	 * if GP device unlock device SRAM for general use
@@ -210,7 +210,7 @@ void try_unlock_memory()
  *****************************************************************************/
 void s_init(void)
 {
-	int in_sdram = is_running_in_sdram();
+	int in_sdram = running_from_sdram();
 
 	watchdog_init();
 
diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c
index 3c80113..a49e84a 100644
--- a/arch/arm/cpu/armv7/omap3/sys_info.c
+++ b/arch/arm/cpu/armv7/omap3/sys_info.c
@@ -240,18 +240,6 @@ u32 is_running_in_sram(void)
 	return 0;		/* running in FLASH or SDRAM */
 }
 
-/********************************************************
- *  is_running_in_sdram() - tell if currently running in
- *  SDRAM.
- *******************************************************/
-u32 is_running_in_sdram(void)
-{
-	if (get_base() > 4)
-		return 1;	/* in SDRAM */
-
-	return 0;		/* running in SRAM or FLASH */
-}
-
 /***************************************************************
  *  get_boot_type() - Is this an XIP type device or a stream one
  *  bits 4-0 specify type. Bit 5 says mem/perif
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 9e52b12..269b8cc 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -57,7 +57,6 @@ u32 get_sysboot_value(void);
 u32 is_gpmc_muxed(void);
 u32 get_gpmc0_type(void);
 u32 get_gpmc0_width(void);
-u32 is_running_in_sdram(void);
 u32 is_running_in_sram(void);
 u32 is_running_in_flash(void);
 u32 get_device_type(void);
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index 03bd923..83d3813 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -42,11 +42,6 @@
 #define OMAP44XX_L4_WKUP_BASE	0x4A300000
 #define OMAP44XX_L4_PER_BASE	0x48000000
 
-#define OMAP44XX_DRAM_ADDR_SPACE_START	0x80000000
-#define OMAP44XX_DRAM_ADDR_SPACE_END	0xD0000000
-#define DRAM_ADDR_SPACE_START	OMAP44XX_DRAM_ADDR_SPACE_START
-#define DRAM_ADDR_SPACE_END	OMAP44XX_DRAM_ADDR_SPACE_END
-
 /* CONTROL */
 #define CTRL_BASE		(OMAP44XX_L4_CORE_BASE + 0x2000)
 #define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index d633573..48a6550 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -67,14 +67,6 @@ void force_emif_self_refresh(void);
  */
 extern struct omap_boot_parameters boot_params;
 
-static inline u32 running_from_sdram(void)
-{
-	u32 pc;
-	asm volatile ("mov %0, pc" : "=r" (pc));
-	return ((pc >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
-	    (pc < OMAP44XX_DRAM_ADDR_SPACE_END));
-}
-
 static inline u8 uboot_loaded_by_spl(void)
 {
 	/*
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 7f05cb5..c697e0b 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -39,11 +39,6 @@
 #define OMAP54XX_L4_WKUP_BASE	0x4Ae00000
 #define OMAP54XX_L4_PER_BASE	0x48000000
 
-#define OMAP54XX_DRAM_ADDR_SPACE_START	0x80000000
-#define OMAP54XX_DRAM_ADDR_SPACE_END	0xFFFFFFFF
-#define DRAM_ADDR_SPACE_START	OMAP54XX_DRAM_ADDR_SPACE_START
-#define DRAM_ADDR_SPACE_END	OMAP54XX_DRAM_ADDR_SPACE_END
-
 /* CONTROL */
 #define CTRL_BASE		(OMAP54XX_L4_CORE_BASE + 0x2000)
 #define CONTROL_PADCONF_CORE	(CTRL_BASE + 0x0800)
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 74feb90..23b02fd 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -68,14 +68,6 @@ void force_emif_self_refresh(void);
  */
 extern struct omap_boot_parameters boot_params;
 
-static inline u32 running_from_sdram(void)
-{
-	u32 pc;
-	asm volatile ("mov %0, pc" : "=r" (pc));
-	return ((pc >= OMAP54XX_DRAM_ADDR_SPACE_START) &&
-	    (pc < OMAP54XX_DRAM_ADDR_SPACE_END));
-}
-
 static inline u8 uboot_loaded_by_spl(void)
 {
 	/*
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 4e95eee..4cf583e 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -118,6 +118,20 @@ static inline u32 omap_revision(void)
 }
 
 /*
+ * These locations are common to all current OMAP and derivative devices.
+ */
+#define DRAM_ADDR_SPACE_START	0x80000000
+#define DRAM_ADDR_SPACE_END	0xD0000000
+
+static inline u32 running_from_sdram(void)
+{
+	u32 pc;
+	asm volatile ("mov %0, pc" : "=r" (pc));
+	return ((pc >= DRAM_ADDR_SPACE_START) &&
+	    (pc < DRAM_ADDR_SPACE_END));
+}
+
+/*
  * silicon revisions.
  * Moving this to common, so that most of code can be moved to common,
  * directories.
-- 
1.7.9.5

[U-Boot] [PATCH 02/17] am335x_evm: Update config for common usage

[Tom Rini]

- Add default commands
- Add HUSH parser
- Make environment, malloc areas larger
- Add ATAGS and OF_LIBFDT
- Add defaults to boot ramdisk and MMC, use uEnv.txt

Signed-off-by: Tom Rini <trini@ti.com>
---
 include/configs/am335x_evm.h |   69 ++++++++++++++++++++++++++++++++++++------
 1 file changed, 59 insertions(+), 10 deletions(-)

diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index d0fbc88..32a7441 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -17,32 +17,81 @@
 #define __CONFIG_AM335X_EVM_H
 
 #define CONFIG_AM33XX
-#define CONFIG_CMD_MEMORY	/* for mtest */
-#undef CONFIG_GZIP
-#undef CONFIG_ZLIB
-#undef CONFIG_SYS_HUSH_PARSER
 #undef CONFIG_CMD_NET
 
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
 
-#define CONFIG_ENV_SIZE			0x400
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (8 * 1024))
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT		"U-Boot# "
 #define CONFIG_SYS_NO_FLASH
 #define MACH_TYPE_TIAM335EVM		3589	/* Until the next sync */
 #define CONFIG_MACH_TYPE		MACH_TYPE_TIAM335EVM
 
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* commands to include */
+#include <config_cmd_default.h>
+
 #define CONFIG_CMD_ASKENV
 #define CONFIG_VERSION_VARIABLE
 
 /* set to negative value for no autoboot */
 #define CONFIG_BOOTDELAY		3
-#define CONFIG_SYS_AUTOLOAD		"no"
-#define CONFIG_BOOTFILE			"uImage"
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"verify=yes\0" \
-	"ramdisk_file=ramdisk.gz\0" \
+	"loadaddr=0x80200000\0" \
+	"rdaddr=0x81000000\0" \
+	"bootfile=/boot/uImage\0" \
+	"console=ttyO0,115200n8\0" \
+	"optargs=\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
+	"ramrootfstype=ext2\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"ramargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${ramroot} " \
+		"rootfstype=${ramrootfstype}\0" \
+	"loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
+	"loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
+	"loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"ramboot=echo Booting from ramdisk ...; " \
+		"run ramargs; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc rescan ${mmcdev}; then " \
+		"echo SD/MMC found on device ${mmcdev};" \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv};" \
+			"run importbootenv;" \
+		"fi;" \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...;" \
+			"run uenvcmd;" \
+		"fi;" \
+		"if run loaduimage; then " \
+			"run mmcboot;" \
+		"fi;" \
+	"fi;" \
 
 /* Clock Defines */
 #define V_OSCK				24000000  /* Clock output from T2 */
-- 
1.7.9.5

[U-Boot] [PATCH 03/17] am33xx: Remove DMM_BASE define

[Tom Rini]

The am33xx does not have a DMM, so don't define the base.

Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/include/asm/arch-am33xx/hardware.h |    1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index 0ec22eb..9be679f 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -53,7 +53,6 @@
 /* EMIF Base address */
 #define EMIF4_0_CFG_BASE		0x4C000000
 #define EMIF4_1_CFG_BASE		0x4D000000
-#define DMM_BASE			0x4E000000
 
 /* PLL related registers */
 #define CM_PER				0x44E00000
-- 
1.7.9.5

[U-Boot] [PATCH 04/17] am33xx: Convert to using <asm/emif.h> to describe the EMIF

[Tom Rini]

Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/am33xx/ddr.c             |   29 ++++++++++++++-------------
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |   27 -------------------------
 2 files changed, 15 insertions(+), 41 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index ed982c1..e592609 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -18,12 +18,13 @@ http://www.ti.com/
 #include <asm/arch/cpu.h>
 #include <asm/arch/ddr_defs.h>
 #include <asm/io.h>
+#include <asm/emif.h>
 
 /**
  * Base address for EMIF instances
  */
-static struct emif_regs *emif_reg = {
-				(struct emif_regs *)EMIF4_0_CFG_BASE};
+static struct emif_reg_struct *emif_reg = {
+				(struct emif_reg_struct *)EMIF4_0_CFG_BASE};
 
 /**
  * Base address for DDR instance
@@ -48,10 +49,10 @@ static struct ddr_cmdtctrl *ioctrl_reg = {
  */
 int config_sdram(struct sdram_config *cfg)
 {
-	writel(cfg->sdrcr, &emif_reg->sdrcr);
-	writel(cfg->sdrcr2, &emif_reg->sdrcr2);
-	writel(cfg->refresh, &emif_reg->sdrrcr);
-	writel(cfg->refresh_sh, &emif_reg->sdrrcsr);
+	writel(cfg->sdrcr, &emif_reg->emif_sdram_config);
+	writel(cfg->sdrcr2, &emif_reg->emif_lpddr2_nvm_config);
+	writel(cfg->refresh, &emif_reg->emif_sdram_ref_ctrl);
+	writel(cfg->refresh_sh, &emif_reg->emif_sdram_ref_ctrl_shdw);
 
 	return 0;
 }
@@ -61,12 +62,12 @@ int config_sdram(struct sdram_config *cfg)
  */
 int set_sdram_timings(struct sdram_timing *t)
 {
-	writel(t->time1, &emif_reg->sdrtim1);
-	writel(t->time1_sh, &emif_reg->sdrtim1sr);
-	writel(t->time2, &emif_reg->sdrtim2);
-	writel(t->time2_sh, &emif_reg->sdrtim2sr);
-	writel(t->time3, &emif_reg->sdrtim3);
-	writel(t->time3_sh, &emif_reg->sdrtim3sr);
+	writel(t->time1, &emif_reg->emif_sdram_tim_1);
+	writel(t->time1_sh, &emif_reg->emif_sdram_tim_1_shdw);
+	writel(t->time2, &emif_reg->emif_sdram_tim_2);
+	writel(t->time2_sh, &emif_reg->emif_sdram_tim_2_shdw);
+	writel(t->time3, &emif_reg->emif_sdram_tim_3);
+	writel(t->time3_sh, &emif_reg->emif_sdram_tim_3_shdw);
 
 	return 0;
 }
@@ -76,8 +77,8 @@ int set_sdram_timings(struct sdram_timing *t)
  */
 int config_ddr_phy(struct ddr_phy_control *p)
 {
-	writel(p->reg, &emif_reg->ddrphycr);
-	writel(p->reg_sh, &emif_reg->ddrphycsr);
+	writel(p->reg, &emif_reg->emif_ddr_phy_ctrl_1);
+	writel(p->reg_sh, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
 
 	return 0;
 }
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 388336f..c62f826 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -56,33 +56,6 @@
 #define DDR_IOCTRL_VALUE	0x18B
 
 /**
- * This structure represents the EMIF registers on AM33XX devices.
- */
-struct emif_regs {
-	unsigned int sdrrev;		/* offset 0x00 */
-	unsigned int sdrstat;		/* offset 0x04 */
-	unsigned int sdrcr;		/* offset 0x08 */
-	unsigned int sdrcr2;		/* offset 0x0C */
-	unsigned int sdrrcr;		/* offset 0x10 */
-	unsigned int sdrrcsr;		/* offset 0x14 */
-	unsigned int sdrtim1;		/* offset 0x18 */
-	unsigned int sdrtim1sr;		/* offset 0x1C */
-	unsigned int sdrtim2;		/* offset 0x20 */
-	unsigned int sdrtim2sr;		/* offset 0x24 */
-	unsigned int sdrtim3;		/* offset 0x28 */
-	unsigned int sdrtim3sr;		/* offset 0x2C */
-	unsigned int res1[2];
-	unsigned int sdrmcr;		/* offset 0x38 */
-	unsigned int sdrmcsr;		/* offset 0x3C */
-	unsigned int res2[8];
-	unsigned int sdritr;		/* offset 0x60 */
-	unsigned int res3[32];
-	unsigned int ddrphycr;		/* offset 0xE4 */
-	unsigned int ddrphycsr;		/* offset 0xE8 */
-	unsigned int ddrphycr2;		/* offset 0xEC */
-};
-
-/**
  * Encapsulates DDR PHY control and corresponding shadow registers.
  */
 struct ddr_phy_control {
-- 
1.7.9.5

[U-Boot] [PATCH 05/17] am33xx: Remove extra check in enable_ddr_clocks

[Tom Rini]

We do not need to check for EMIF_GCLK and L3_GCLK being active.  This
was a hold-over from bringup and no longer required.

Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/am33xx/clock.c |    5 -----
 1 file changed, 5 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index bbb9c13..d05780c 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -255,11 +255,6 @@ void enable_emif_clocks(void)
 	writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
 	/* Enable EMIF0 Clock */
 	writel(PRCM_MOD_EN, &cmper->emifclkctrl);
-	/* Poll for emif_gclk  & L3_G clock  are active */
-	while ((readl(&cmper->l3clkstctrl) & (PRCM_EMIF_CLK_ACTIVITY |
-			PRCM_L3_GCLK_ACTIVITY)) != (PRCM_EMIF_CLK_ACTIVITY |
-			PRCM_L3_GCLK_ACTIVITY))
-		;
 	/* Poll if module is functional */
 	while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
 		;
-- 
1.7.9.5

[U-Boot] [PATCH 06/17] am33xx: Bugfix to config_sdram()

[Tom Rini]

When we change SDRAM_CONFIG this triggers a refresh based on all of the
parameters that we have programmed so we must do this last.

Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/am33xx/ddr.c |    3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index e592609..c37f91b 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -49,10 +49,9 @@ static struct ddr_cmdtctrl *ioctrl_reg = {
  */
 int config_sdram(struct sdram_config *cfg)
 {
-	writel(cfg->sdrcr, &emif_reg->emif_sdram_config);
-	writel(cfg->sdrcr2, &emif_reg->emif_lpddr2_nvm_config);
 	writel(cfg->refresh, &emif_reg->emif_sdram_ref_ctrl);
 	writel(cfg->refresh_sh, &emif_reg->emif_sdram_ref_ctrl_shdw);
+	writel(cfg->sdrcr, &emif_reg->emif_sdram_config);
 
 	return 0;
 }
-- 
1.7.9.5

[U-Boot] [PATCH 07/17] am33xx: Rework DDR2 EMIF initalization slightly

[Tom Rini]

With the previous bugfix we now don't need to set two different REF_CTRL
values and instead set the final value.

Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/am33xx/emif4.c |   17 ++---------------
 1 file changed, 2 insertions(+), 15 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 2f4164d..8f7aadc 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -117,7 +117,6 @@ static void config_vtp(void)
 
 static void config_emif_ddr2(void)
 {
-	int i;
 	int ret;
 	struct sdram_config cfg;
 	struct sdram_timing tmg;
@@ -137,31 +136,19 @@ static void config_emif_ddr2(void)
 
 	cfg.sdrcr = EMIF_SDCFG;
 	cfg.sdrcr2 = EMIF_SDCFG;
-	cfg.refresh = 0x00004650;
-	cfg.refresh_sh = 0x00004650;
+	cfg.refresh = EMIF_SDREF;
+	cfg.refresh_sh = EMIF_SDREF;
 
 	/* Program EMIF instance */
 	ret = config_ddr_phy(&phyc);
 	if (ret < 0)
 		printf("Couldn't configure phyc\n");
 
-	ret = config_sdram(&cfg);
-	if (ret < 0)
-		printf("Couldn't configure SDRAM\n");
 
 	ret = set_sdram_timings(&tmg);
 	if (ret < 0)
 		printf("Couldn't configure timings\n");
 
-	/* Delay */
-	for (i = 0; i < 5000; i++)
-		;
-
-	cfg.refresh = EMIF_SDREF;
-	cfg.refresh_sh = EMIF_SDREF;
-	cfg.sdrcr = EMIF_SDCFG;
-	cfg.sdrcr2 = EMIF_SDCFG;
-
 	ret = config_sdram(&cfg);
 	if (ret < 0)
 		printf("Couldn't configure SDRAM\n");
-- 
1.7.9.5

[U-Boot] [PATCH 08/17] am33xx: Make config_cmd_ctrl / config_ddr_data take const structs

[Tom Rini]

Rework the EMIF4/DDR code slightly to setup the structs that
config_cmd_ctrl and config_ddr_data take to be setup at compile time and
mark them as const.  This lets us simplify the calling path slightly as
well as making it easier to deal with DDR3.

Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/am33xx/ddr.c             |    4 +-
 arch/arm/cpu/armv7/am33xx/emif4.c           |  101 ++++++++++++---------------
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |    4 +-
 3 files changed, 48 insertions(+), 61 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index c37f91b..b4b3c01 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -85,7 +85,7 @@ int config_ddr_phy(struct ddr_phy_control *p)
 /**
  * Configure DDR CMD control registers
  */
-int config_cmd_ctrl(struct cmd_control *cmd)
+int config_cmd_ctrl(const struct cmd_control *cmd)
 {
 	writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
 	writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce);
@@ -111,7 +111,7 @@ int config_cmd_ctrl(struct cmd_control *cmd)
 /**
  * Configure DDR DATA registers
  */
-int config_ddr_data(int macrono, struct ddr_data *data)
+int config_ddr_data(int macrono, const struct ddr_data *data)
 {
 	writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
 	writel(data->datardsratio1, &ddr_reg[macrono]->dt0rdsratio1);
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 8f7aadc..26c6a66 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -47,58 +47,47 @@ void dram_init_banksize(void)
 
 
 #ifdef CONFIG_SPL_BUILD
-static void data_macro_config(int dataMacroNum)
-{
-	struct ddr_data data;
-
-	data.datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
-				|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0));
-	data.datardsratio1 = DDR2_RD_DQS>>2;
-	data.datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
-				|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0));
-	data.datawdsratio1 = DDR2_WR_DQS>>2;
-	data.datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
-				|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0));
-	data.datawiratio1 = DDR2_PHY_WRLVL>>2;
-	data.datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
-				|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0));
-	data.datagiratio1 = DDR2_PHY_GATELVL>>2;
-	data.datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
-				|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0));
-	data.datafwsratio1 = DDR2_PHY_FIFO_WE>>2;
-	data.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
-				|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0));
-	data.datawrsratio1 = DDR2_PHY_WR_DATA>>2;
-	data.datadldiff0 = PHY_DLL_LOCK_DIFF;
-
-	config_ddr_data(dataMacroNum, &data);
-}
-
-static void cmd_macro_config(void)
-{
-	struct cmd_control cmd;
-
-	cmd.cmd0csratio = DDR2_RATIO;
-	cmd.cmd0csforce = CMD_FORCE;
-	cmd.cmd0csdelay = CMD_DELAY;
-	cmd.cmd0dldiff = DDR2_DLL_LOCK_DIFF;
-	cmd.cmd0iclkout = DDR2_INVERT_CLKOUT;
-
-	cmd.cmd1csratio = DDR2_RATIO;
-	cmd.cmd1csforce = CMD_FORCE;
-	cmd.cmd1csdelay = CMD_DELAY;
-	cmd.cmd1dldiff = DDR2_DLL_LOCK_DIFF;
-	cmd.cmd1iclkout = DDR2_INVERT_CLKOUT;
-
-	cmd.cmd2csratio = DDR2_RATIO;
-	cmd.cmd2csforce = CMD_FORCE;
-	cmd.cmd2csdelay = CMD_DELAY;
-	cmd.cmd2dldiff = DDR2_DLL_LOCK_DIFF;
-	cmd.cmd2iclkout = DDR2_INVERT_CLKOUT;
-
-	config_cmd_ctrl(&cmd);
-
-}
+static const struct ddr_data ddr2_data = {
+	.datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
+				|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
+	.datardsratio1 = DDR2_RD_DQS>>2,
+	.datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
+				|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
+	.datawdsratio1 = DDR2_WR_DQS>>2,
+	.datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
+				|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
+	.datawiratio1 = DDR2_PHY_WRLVL>>2,
+	.datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
+				|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
+	.datagiratio1 = DDR2_PHY_GATELVL>>2,
+	.datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
+				|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
+	.datafwsratio1 = DDR2_PHY_FIFO_WE>>2,
+	.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
+				|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
+	.datawrsratio1 = DDR2_PHY_WR_DATA>>2,
+	.datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+static const struct cmd_control ddr2_cmd_ctrl_data = {
+	.cmd0csratio = DDR2_RATIO,
+	.cmd0csforce = CMD_FORCE,
+	.cmd0csdelay = CMD_DELAY,
+	.cmd0dldiff = DDR2_DLL_LOCK_DIFF,
+	.cmd0iclkout = DDR2_INVERT_CLKOUT,
+
+	.cmd1csratio = DDR2_RATIO,
+	.cmd1csforce = CMD_FORCE,
+	.cmd1csdelay = CMD_DELAY,
+	.cmd1dldiff = DDR2_DLL_LOCK_DIFF,
+	.cmd1iclkout = DDR2_INVERT_CLKOUT,
+
+	.cmd2csratio = DDR2_RATIO,
+	.cmd2csforce = CMD_FORCE,
+	.cmd2csdelay = CMD_DELAY,
+	.cmd2dldiff = DDR2_DLL_LOCK_DIFF,
+	.cmd2iclkout = DDR2_INVERT_CLKOUT,
+};
 
 static void config_vtp(void)
 {
@@ -156,18 +145,16 @@ static void config_emif_ddr2(void)
 
 void config_ddr(void)
 {
-	int data_macro_0 = 0;
-	int data_macro_1 = 1;
 	struct ddr_ioctrl ioctrl;
 
 	enable_emif_clocks();
 
 	config_vtp();
 
-	cmd_macro_config();
+	config_cmd_ctrl(&ddr2_cmd_ctrl_data);
 
-	data_macro_config(data_macro_0);
-	data_macro_config(data_macro_1);
+	config_ddr_data(0, &ddr2_data);
+	config_ddr_data(1, &ddr2_data);
 
 	writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
 	writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index c62f826..087082f 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -190,12 +190,12 @@ struct ddr_data {
 /**
  * Configure DDR CMD control registers
  */
-int config_cmd_ctrl(struct cmd_control *cmd);
+int config_cmd_ctrl(const struct cmd_control *cmd);
 
 /**
  * Configure DDR DATA registers
  */
-int config_ddr_data(int data_macrono, struct ddr_data *data);
+int config_ddr_data(int data_macrono, const struct ddr_data *data);
 
 /**
  * This structure represents the DDR io control on AM33XX devices.
-- 
1.7.9.5

[U-Boot] [PATCH 09/17] am33xx: Pass to config_ddr the type of memory that is connected

[Tom Rini]

We need to pass in the type of memory that is connected to the board.
The only reliable way to do this is to know what type of board we are
running on (which later will be knowable in s_init()).  For now, pass in
the value of DDR2.

Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/am33xx/board.c           |    3 ++-
 arch/arm/cpu/armv7/am33xx/emif4.c           |   38 +++++++++++++++------------
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |    2 +-
 arch/arm/include/asm/emif.h                 |    8 +++++-
 4 files changed, 31 insertions(+), 20 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 71309a7..fd2d82b 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -26,6 +26,7 @@
 #include <asm/arch/common_def.h>
 #include <asm/io.h>
 #include <asm/omap_common.h>
+#include <asm/emif.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -97,7 +98,7 @@ void s_init(void)
 
 	preloader_console_init();
 
-	config_ddr();
+	config_ddr(EMIF_REG_SDRAM_TYPE_DDR2);
 #endif
 
 	/* Enable MMC0 */
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 26c6a66..9b1a80c 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -22,6 +22,7 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/clock.h>
 #include <asm/io.h>
+#include <asm/emif.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -29,7 +30,6 @@ struct ddr_regs *ddrregs = (struct ddr_regs *)DDR_PHY_BASE_ADDR;
 struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
 struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
 
-
 int dram_init(void)
 {
 	/* dram_init must store complete ramsize in gd->ram_size */
@@ -143,33 +143,37 @@ static void config_emif_ddr2(void)
 		printf("Couldn't configure SDRAM\n");
 }
 
-void config_ddr(void)
+void config_ddr(short ddr_type)
 {
 	struct ddr_ioctrl ioctrl;
 
 	enable_emif_clocks();
 
-	config_vtp();
+	if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
+		config_vtp();
 
-	config_cmd_ctrl(&ddr2_cmd_ctrl_data);
+		config_cmd_ctrl(&ddr2_cmd_ctrl_data);
 
-	config_ddr_data(0, &ddr2_data);
-	config_ddr_data(1, &ddr2_data);
+		config_ddr_data(0, &ddr2_data);
+		config_ddr_data(1, &ddr2_data);
 
-	writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
-	writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
+		writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
+		writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
 
-	ioctrl.cmd1ctl = DDR_IOCTRL_VALUE;
-	ioctrl.cmd2ctl = DDR_IOCTRL_VALUE;
-	ioctrl.cmd3ctl = DDR_IOCTRL_VALUE;
-	ioctrl.data1ctl = DDR_IOCTRL_VALUE;
-	ioctrl.data2ctl = DDR_IOCTRL_VALUE;
+		ioctrl.cmd1ctl = DDR_IOCTRL_VALUE;
+		ioctrl.cmd2ctl = DDR_IOCTRL_VALUE;
+		ioctrl.cmd3ctl = DDR_IOCTRL_VALUE;
+		ioctrl.data1ctl = DDR_IOCTRL_VALUE;
+		ioctrl.data2ctl = DDR_IOCTRL_VALUE;
 
-	config_io_ctrl(&ioctrl);
+		config_io_ctrl(&ioctrl);
 
-	writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff, &ddrctrl->ddrioctrl);
-	writel(readl(&ddrctrl->ddrckectrl) | 0x00000001, &ddrctrl->ddrckectrl);
+		writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff,
+				&ddrctrl->ddrioctrl);
+		writel(readl(&ddrctrl->ddrckectrl) | 0x00000001,
+				&ddrctrl->ddrckectrl);
 
-	config_emif_ddr2();
+		config_emif_ddr2();
+	}
 }
 #endif
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 087082f..842e45f 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -232,6 +232,6 @@ struct ddr_ctrl {
 	unsigned int ddrckectrl;
 };
 
-void config_ddr(void);
+void config_ddr(short ddr_type);
 
 #endif  /* _DDR_DEFS_H */
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 674c3de..ed251ec 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -19,7 +19,7 @@
 #define EMIF1_BASE				0x4c000000
 #define EMIF2_BASE				0x4d000000
 
-/* Registers shifts and masks */
+/* Registers shifts, masks and values */
 
 /* EMIF_MOD_ID_REV */
 #define EMIF_REG_SCHEME_SHIFT			30
@@ -46,6 +46,12 @@
 /* SDRAM_CONFIG */
 #define EMIF_REG_SDRAM_TYPE_SHIFT			29
 #define EMIF_REG_SDRAM_TYPE_MASK			(0x7 << 29)
+#define EMIF_REG_SDRAM_TYPE_DDR1			0
+#define EMIF_REG_SDRAM_TYPE_LPDDR1			1
+#define EMIF_REG_SDRAM_TYPE_DDR2			2
+#define EMIF_REG_SDRAM_TYPE_DDR3			3
+#define EMIF_REG_SDRAM_TYPE_LPDDR2_S4			4
+#define EMIF_REG_SDRAM_TYPE_LPDDR2_S2			5
 #define EMIF_REG_IBANK_POS_SHIFT			27
 #define EMIF_REG_IBANK_POS_MASK			(0x3 << 27)
 #define EMIF_REG_DDR_TERM_SHIFT			24
-- 
1.7.9.5

[U-Boot] [PATCH 10/17] am33xx: Move the call to ddr_pll_config, make it take the frequency

[Tom Rini]

Depending on if we have DDR2 or DDR3 on the board we will need to call
ddr_pll_config with a different value.  This call can be delayed
slightly to the point where we know which type of memory we have.

Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/am33xx/clock.c            |    5 ++---
 arch/arm/cpu/armv7/am33xx/emif4.c            |    2 ++
 arch/arm/include/asm/arch-am33xx/sys_proto.h |    1 +
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index d05780c..82bbba2 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -216,7 +216,7 @@ static void per_pll_config(void)
 		;
 }
 
-static void ddr_pll_config(void)
+void ddr_pll_config(unsigned int ddrpll_m)
 {
 	u32 clkmode, clksel, div_m2;
 
@@ -234,7 +234,7 @@ static void ddr_pll_config(void)
 		;
 
 	clksel = clksel & (~CLK_SEL_MASK);
-	clksel = clksel | ((DDRPLL_M << CLK_SEL_SHIFT) | DDRPLL_N);
+	clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
 	writel(clksel, &cmwkup->clkseldpllddr);
 
 	div_m2 = div_m2 & CLK_DIV_SEL;
@@ -268,7 +268,6 @@ void pll_init()
 	mpu_pll_config();
 	core_pll_config();
 	per_pll_config();
-	ddr_pll_config();
 
 	/* Enable the required interconnect clocks */
 	enable_interface_clocks();
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 9b1a80c..12f270a 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -21,6 +21,7 @@
 #include <asm/arch/ddr_defs.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 #include <asm/emif.h>
 
@@ -150,6 +151,7 @@ void config_ddr(short ddr_type)
 	enable_emif_clocks();
 
 	if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
+		ddr_pll_config(266);
 		config_vtp();
 
 		config_cmd_ctrl(&ddr2_cmd_ctrl_data);
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 6c58f1b..eef5573 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -30,4 +30,5 @@ int print_cpuinfo(void);
 
 u32 get_device_type(void);
 void setup_clocks_for_console(void);
+void ddr_pll_config(unsigned int ddrpll_M);
 #endif
-- 
1.7.9.5

[U-Boot] [PATCH 11/17] am33xx: Clean up unused DDR defines, prefix more with 'DDR2'

[Tom Rini]

- Remove a handful of unused defines.
- Prefix more values with 'DDR2' as DDR3 will require different values.

Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/am33xx/emif4.c           |   46 +++++++++++++--------------
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |   32 +++++++------------
 2 files changed, 35 insertions(+), 43 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 12f270a..684b123 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -112,22 +112,22 @@ static void config_emif_ddr2(void)
 	struct sdram_timing tmg;
 	struct ddr_phy_control phyc;
 
-	/*Program EMIF0 CFG Registers*/
-	phyc.reg = EMIF_READ_LATENCY;
-	phyc.reg_sh = EMIF_READ_LATENCY;
-	phyc.reg2 = EMIF_READ_LATENCY;
-
-	tmg.time1 = EMIF_TIM1;
-	tmg.time1_sh = EMIF_TIM1;
-	tmg.time2 = EMIF_TIM2;
-	tmg.time2_sh = EMIF_TIM2;
-	tmg.time3 = EMIF_TIM3;
-	tmg.time3_sh = EMIF_TIM3;
-
-	cfg.sdrcr = EMIF_SDCFG;
-	cfg.sdrcr2 = EMIF_SDCFG;
-	cfg.refresh = EMIF_SDREF;
-	cfg.refresh_sh = EMIF_SDREF;
+	/* Program EMIF0 CFG Registers */
+	phyc.reg = DDR2_EMIF_READ_LATENCY;
+	phyc.reg_sh = DDR2_EMIF_READ_LATENCY;
+	phyc.reg2 = DDR2_EMIF_READ_LATENCY;
+
+	tmg.time1 = DDR2_EMIF_TIM1;
+	tmg.time1_sh = DDR2_EMIF_TIM1;
+	tmg.time2 = DDR2_EMIF_TIM2;
+	tmg.time2_sh = DDR2_EMIF_TIM2;
+	tmg.time3 = DDR2_EMIF_TIM3;
+	tmg.time3_sh = DDR2_EMIF_TIM3;
+
+	cfg.sdrcr = DDR2_EMIF_SDCFG;
+	cfg.sdrcr2 = DDR2_EMIF_SDCFG;
+	cfg.refresh = DDR2_EMIF_SDREF;
+	cfg.refresh_sh = DDR2_EMIF_SDREF;
 
 	/* Program EMIF instance */
 	ret = config_ddr_phy(&phyc);
@@ -159,14 +159,14 @@ void config_ddr(short ddr_type)
 		config_ddr_data(0, &ddr2_data);
 		config_ddr_data(1, &ddr2_data);
 
-		writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
-		writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
+		writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
+		writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
 
-		ioctrl.cmd1ctl = DDR_IOCTRL_VALUE;
-		ioctrl.cmd2ctl = DDR_IOCTRL_VALUE;
-		ioctrl.cmd3ctl = DDR_IOCTRL_VALUE;
-		ioctrl.data1ctl = DDR_IOCTRL_VALUE;
-		ioctrl.data2ctl = DDR_IOCTRL_VALUE;
+		ioctrl.cmd1ctl = DDR2_IOCTRL_VALUE;
+		ioctrl.cmd2ctl = DDR2_IOCTRL_VALUE;
+		ioctrl.cmd3ctl = DDR2_IOCTRL_VALUE;
+		ioctrl.data1ctl = DDR2_IOCTRL_VALUE;
+		ioctrl.data2ctl = DDR2_IOCTRL_VALUE;
 
 		config_io_ctrl(&ioctrl);
 
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 842e45f..b4735ba 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -22,38 +22,30 @@
 #include <asm/arch/hardware.h>
 
 /* AM335X EMIF Register values */
-#define EMIF_SDMGT		0x80000000
-#define EMIF_SDRAM		0x00004650
-#define EMIF_PHYCFG		0x2
-#define DDR_PHY_RESET		(0x1 << 10)
-#define DDR_FUNCTIONAL_MODE_EN	0x1
-#define DDR_PHY_READY		(0x1 << 2)
 #define VTP_CTRL_READY		(0x1 << 5)
 #define VTP_CTRL_ENABLE		(0x1 << 6)
-#define VTP_CTRL_LOCK_EN	(0x1 << 4)
 #define VTP_CTRL_START_EN	(0x1)
-#define DDR2_RATIO		0x80
 #define CMD_FORCE		0x00
 #define CMD_DELAY		0x00
+#define PHY_DLL_LOCK_DIFF	0x0
 
-#define EMIF_READ_LATENCY	0x05
-#define EMIF_TIM1		0x0666B3D6
-#define EMIF_TIM2		0x143731DA
-#define EMIF_TIM3		0x00000347
-#define EMIF_SDCFG		0x43805332
-#define EMIF_SDREF		0x0000081a
+#define DDR2_EMIF_READ_LATENCY	0x05
+#define DDR2_EMIF_TIM1		0x0666B3D6
+#define DDR2_EMIF_TIM2		0x143731DA
+#define DDR2_EMIF_TIM3		0x00000347
+#define DDR2_EMIF_SDCFG		0x43805332
+#define DDR2_EMIF_SDREF		0x0000081a
 #define DDR2_DLL_LOCK_DIFF	0x0
-#define DDR2_RD_DQS		0x12
-#define DDR2_PHY_FIFO_WE	0x80
-
+#define DDR2_RATIO		0x80
 #define DDR2_INVERT_CLKOUT	0x00
+#define DDR2_RD_DQS		0x12
 #define DDR2_WR_DQS		0x00
 #define DDR2_PHY_WRLVL		0x00
 #define DDR2_PHY_GATELVL	0x00
 #define DDR2_PHY_WR_DATA	0x40
-#define PHY_RANK0_DELAY		0x01
-#define PHY_DLL_LOCK_DIFF	0x0
-#define DDR_IOCTRL_VALUE	0x18B
+#define DDR2_PHY_FIFO_WE	0x80
+#define DDR2_PHY_RANK0_DELAY	0x1
+#define DDR2_IOCTRL_VALUE	0x18B
 
 /**
  * Encapsulates DDR PHY control and corresponding shadow registers.
-- 
1.7.9.5

[U-Boot] [PATCH 12/17] am335x: ddr_defs: Update EMIF parameters

[Tom Rini]

From: Vaibhav Bedia <vaibhav.bedia@ti.com>

EMIF parameters are calculated based on the AC timing
parameters from the SDRAM datasheet and the DDR frequency.

Current values for these paramters in AM335x U-Boot code,
though reliable, are not fully optimal. The most optimal
settings can be derived based on the guidelines published
at [1]. A pre-computed set of values with the most optimum
settings for AM335x EVM and BeagleBone can be found at [2].

[1] http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips
[2] http://processors.wiki.ti.com/index.php/OMAP_and_Sitara_CCS_support#AM335x

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |   10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index b4735ba..879c5fb 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -29,11 +29,11 @@
 #define CMD_DELAY		0x00
 #define PHY_DLL_LOCK_DIFF	0x0
 
-#define DDR2_EMIF_READ_LATENCY	0x05
-#define DDR2_EMIF_TIM1		0x0666B3D6
-#define DDR2_EMIF_TIM2		0x143731DA
-#define DDR2_EMIF_TIM3		0x00000347
-#define DDR2_EMIF_SDCFG		0x43805332
+#define DDR2_EMIF_READ_LATENCY	0x100005	/* Enable Dynamic Power Down */
+#define DDR2_EMIF_TIM1		0x0666B3C9
+#define DDR2_EMIF_TIM2		0x243631CA
+#define DDR2_EMIF_TIM3		0x0000033F
+#define DDR2_EMIF_SDCFG		0x41805332
 #define DDR2_EMIF_SDREF		0x0000081a
 #define DDR2_DLL_LOCK_DIFF	0x0
 #define DDR2_RATIO		0x80
-- 
1.7.9.5

[U-Boot] [PATCH 13/17] am33xx: Document what we're doing with ddrctrl->ddrckectrl

[Tom Rini]

- Remove the call to set ddrctrl->ddrioctrl as it's all zeros.
- Comment what we're really setting in ddrctrl->ddrckectrl which is that
  we're operating in the normal mode where EMIF/PHY clock is controlled
  by the PHY.

Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/am33xx/emif4.c           |    6 ++----
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |    1 +
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 684b123..e04e970 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -170,10 +170,8 @@ void config_ddr(short ddr_type)
 
 		config_io_ctrl(&ioctrl);
 
-		writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff,
-				&ddrctrl->ddrioctrl);
-		writel(readl(&ddrctrl->ddrckectrl) | 0x00000001,
-				&ddrctrl->ddrckectrl);
+		/* Set CKE to be controlled by EMIF/DDR PHY */
+		writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
 
 		config_emif_ddr2();
 	}
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 879c5fb..f755736 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -28,6 +28,7 @@
 #define CMD_FORCE		0x00
 #define CMD_DELAY		0x00
 #define PHY_DLL_LOCK_DIFF	0x0
+#define DDR_CKE_CTRL_NORMAL	0x1
 
 #define DDR2_EMIF_READ_LATENCY	0x100005	/* Enable Dynamic Power Down */
 #define DDR2_EMIF_TIM1		0x0666B3C9
-- 
1.7.9.5

[U-Boot] [PATCH 14/17] am33xx: Turn a number of 'int' functions to 'void'

[Tom Rini]

A number of memory initalization functions were int and always returned
0.  Further it's not feasible to be doing error checking here, so simply
turn them into void functions.

Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/am33xx/ddr.c             |   29 ++++++---------------------
 arch/arm/cpu/armv7/am33xx/emif4.c           |   16 +++------------
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |   12 +++++------
 3 files changed, 15 insertions(+), 42 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index b4b3c01..7ac144a 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -40,26 +40,19 @@ static struct ddr_cmdtctrl *ioctrl_reg = {
 			(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
 
 /**
- * As a convention, all functions here return 0 on success
- * -1 on failure.
- */
-
-/**
  * Configure SDRAM
  */
-int config_sdram(struct sdram_config *cfg)
+void config_sdram(struct sdram_config *cfg)
 {
 	writel(cfg->refresh, &emif_reg->emif_sdram_ref_ctrl);
 	writel(cfg->refresh_sh, &emif_reg->emif_sdram_ref_ctrl_shdw);
 	writel(cfg->sdrcr, &emif_reg->emif_sdram_config);
-
-	return 0;
 }
 
 /**
  * Set SDRAM timings
  */
-int set_sdram_timings(struct sdram_timing *t)
+void set_sdram_timings(struct sdram_timing *t)
 {
 	writel(t->time1, &emif_reg->emif_sdram_tim_1);
 	writel(t->time1_sh, &emif_reg->emif_sdram_tim_1_shdw);
@@ -67,25 +60,21 @@ int set_sdram_timings(struct sdram_timing *t)
 	writel(t->time2_sh, &emif_reg->emif_sdram_tim_2_shdw);
 	writel(t->time3, &emif_reg->emif_sdram_tim_3);
 	writel(t->time3_sh, &emif_reg->emif_sdram_tim_3_shdw);
-
-	return 0;
 }
 
 /**
  * Configure DDR PHY
  */
-int config_ddr_phy(struct ddr_phy_control *p)
+void config_ddr_phy(struct ddr_phy_control *p)
 {
 	writel(p->reg, &emif_reg->emif_ddr_phy_ctrl_1);
 	writel(p->reg_sh, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
-
-	return 0;
 }
 
 /**
  * Configure DDR CMD control registers
  */
-int config_cmd_ctrl(const struct cmd_control *cmd)
+void config_cmd_ctrl(const struct cmd_control *cmd)
 {
 	writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
 	writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce);
@@ -104,14 +93,12 @@ int config_cmd_ctrl(const struct cmd_control *cmd)
 	writel(cmd->cmd2csdelay, &ddr_reg[0]->cm2csdelay);
 	writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
 	writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
-
-	return 0;
 }
 
 /**
  * Configure DDR DATA registers
  */
-int config_ddr_data(int macrono, const struct ddr_data *data)
+void config_ddr_data(int macrono, const struct ddr_data *data)
 {
 	writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
 	writel(data->datardsratio1, &ddr_reg[macrono]->dt0rdsratio1);
@@ -131,17 +118,13 @@ int config_ddr_data(int macrono, const struct ddr_data *data)
 	writel(data->datawrsratio1, &ddr_reg[macrono]->dt0wrsratio1);
 
 	writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
-
-	return 0;
 }
 
-int config_io_ctrl(struct ddr_ioctrl *ioctrl)
+void config_io_ctrl(struct ddr_ioctrl *ioctrl)
 {
 	writel(ioctrl->cmd1ctl, &ioctrl_reg->cm0ioctl);
 	writel(ioctrl->cmd2ctl, &ioctrl_reg->cm1ioctl);
 	writel(ioctrl->cmd3ctl, &ioctrl_reg->cm2ioctl);
 	writel(ioctrl->data1ctl, &ioctrl_reg->dt0ioctl);
 	writel(ioctrl->data2ctl, &ioctrl_reg->dt1ioctl);
-
-	return 0;
 }
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index e04e970..66ab892 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -107,7 +107,6 @@ static void config_vtp(void)
 
 static void config_emif_ddr2(void)
 {
-	int ret;
 	struct sdram_config cfg;
 	struct sdram_timing tmg;
 	struct ddr_phy_control phyc;
@@ -130,18 +129,9 @@ static void config_emif_ddr2(void)
 	cfg.refresh_sh = DDR2_EMIF_SDREF;
 
 	/* Program EMIF instance */
-	ret = config_ddr_phy(&phyc);
-	if (ret < 0)
-		printf("Couldn't configure phyc\n");
-
-
-	ret = set_sdram_timings(&tmg);
-	if (ret < 0)
-		printf("Couldn't configure timings\n");
-
-	ret = config_sdram(&cfg);
-	if (ret < 0)
-		printf("Couldn't configure SDRAM\n");
+	config_ddr_phy(&phyc);
+	set_sdram_timings(&tmg);
+	config_sdram(&cfg);
 }
 
 void config_ddr(short ddr_type)
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index f755736..997480b 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -82,17 +82,17 @@ struct sdram_config {
 /**
  * Configure SDRAM
  */
-int config_sdram(struct sdram_config *cfg);
+void config_sdram(struct sdram_config *cfg);
 
 /**
  * Set SDRAM timings
  */
-int set_sdram_timings(struct sdram_timing *val);
+void set_sdram_timings(struct sdram_timing *val);
 
 /**
  * Configure DDR PHY
  */
-int config_ddr_phy(struct ddr_phy_control *cfg);
+void config_ddr_phy(struct ddr_phy_control *cfg);
 
 /**
  * This structure represents the DDR registers on AM33XX devices.
@@ -183,12 +183,12 @@ struct ddr_data {
 /**
  * Configure DDR CMD control registers
  */
-int config_cmd_ctrl(const struct cmd_control *cmd);
+void config_cmd_ctrl(const struct cmd_control *cmd);
 
 /**
  * Configure DDR DATA registers
  */
-int config_ddr_data(int data_macrono, const struct ddr_data *data);
+void config_ddr_data(int data_macrono, const struct ddr_data *data);
 
 /**
  * This structure represents the DDR io control on AM33XX devices.
@@ -217,7 +217,7 @@ struct ddr_ioctrl {
 /**
  * Configure DDR io control registers
  */
-int config_io_ctrl(struct ddr_ioctrl *ioctrl);
+void config_io_ctrl(struct ddr_ioctrl *ioctrl);
 
 struct ddr_ctrl {
 	unsigned int ddrioctrl;
-- 
1.7.9.5

[U-Boot] [PATCH 15/17] am33xx: Use emif_regs struct for storing initialization values

[Tom Rini]

Rather than defining our own structs to note what to use when
programming the EMIF and related re-use the emif_regs struct.

Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/am33xx/ddr.c             |   28 ++++++++---------
 arch/arm/cpu/armv7/am33xx/emif4.c           |   43 ++++++++-------------------
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |   38 +++--------------------
 3 files changed, 31 insertions(+), 78 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index 7ac144a..993f3da 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -42,33 +42,33 @@ static struct ddr_cmdtctrl *ioctrl_reg = {
 /**
  * Configure SDRAM
  */
-void config_sdram(struct sdram_config *cfg)
+void config_sdram(const struct emif_regs *regs)
 {
-	writel(cfg->refresh, &emif_reg->emif_sdram_ref_ctrl);
-	writel(cfg->refresh_sh, &emif_reg->emif_sdram_ref_ctrl_shdw);
-	writel(cfg->sdrcr, &emif_reg->emif_sdram_config);
+	writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
+	writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
+	writel(regs->sdram_config, &emif_reg->emif_sdram_config);
 }
 
 /**
  * Set SDRAM timings
  */
-void set_sdram_timings(struct sdram_timing *t)
+void set_sdram_timings(const struct emif_regs *regs)
 {
-	writel(t->time1, &emif_reg->emif_sdram_tim_1);
-	writel(t->time1_sh, &emif_reg->emif_sdram_tim_1_shdw);
-	writel(t->time2, &emif_reg->emif_sdram_tim_2);
-	writel(t->time2_sh, &emif_reg->emif_sdram_tim_2_shdw);
-	writel(t->time3, &emif_reg->emif_sdram_tim_3);
-	writel(t->time3_sh, &emif_reg->emif_sdram_tim_3_shdw);
+	writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1);
+	writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1_shdw);
+	writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2);
+	writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2_shdw);
+	writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3);
+	writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3_shdw);
 }
 
 /**
  * Configure DDR PHY
  */
-void config_ddr_phy(struct ddr_phy_control *p)
+void config_ddr_phy(const struct emif_regs *regs)
 {
-	writel(p->reg, &emif_reg->emif_ddr_phy_ctrl_1);
-	writel(p->reg_sh, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1);
+	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
 }
 
 /**
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 66ab892..0190ec6 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -90,6 +90,15 @@ static const struct cmd_control ddr2_cmd_ctrl_data = {
 	.cmd2iclkout = DDR2_INVERT_CLKOUT,
 };
 
+static const struct emif_regs ddr2_emif_reg_data = {
+	.sdram_config = DDR2_EMIF_SDCFG,
+	.ref_ctrl = DDR2_EMIF_SDREF,
+	.sdram_tim1 = DDR2_EMIF_TIM1,
+	.sdram_tim2 = DDR2_EMIF_TIM2,
+	.sdram_tim3 = DDR2_EMIF_TIM3,
+	.emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY,
+};
+
 static void config_vtp(void)
 {
 	writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
@@ -105,35 +114,6 @@ static void config_vtp(void)
 		;
 }
 
-static void config_emif_ddr2(void)
-{
-	struct sdram_config cfg;
-	struct sdram_timing tmg;
-	struct ddr_phy_control phyc;
-
-	/* Program EMIF0 CFG Registers */
-	phyc.reg = DDR2_EMIF_READ_LATENCY;
-	phyc.reg_sh = DDR2_EMIF_READ_LATENCY;
-	phyc.reg2 = DDR2_EMIF_READ_LATENCY;
-
-	tmg.time1 = DDR2_EMIF_TIM1;
-	tmg.time1_sh = DDR2_EMIF_TIM1;
-	tmg.time2 = DDR2_EMIF_TIM2;
-	tmg.time2_sh = DDR2_EMIF_TIM2;
-	tmg.time3 = DDR2_EMIF_TIM3;
-	tmg.time3_sh = DDR2_EMIF_TIM3;
-
-	cfg.sdrcr = DDR2_EMIF_SDCFG;
-	cfg.sdrcr2 = DDR2_EMIF_SDCFG;
-	cfg.refresh = DDR2_EMIF_SDREF;
-	cfg.refresh_sh = DDR2_EMIF_SDREF;
-
-	/* Program EMIF instance */
-	config_ddr_phy(&phyc);
-	set_sdram_timings(&tmg);
-	config_sdram(&cfg);
-}
-
 void config_ddr(short ddr_type)
 {
 	struct ddr_ioctrl ioctrl;
@@ -163,7 +143,10 @@ void config_ddr(short ddr_type)
 		/* Set CKE to be controlled by EMIF/DDR PHY */
 		writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
 
-		config_emif_ddr2();
+		/* Program EMIF instance */
+		config_ddr_phy(&ddr2_emif_reg_data);
+		set_sdram_timings(&ddr2_emif_reg_data);
+		config_sdram(&ddr2_emif_reg_data);
 	}
 }
 #endif
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 997480b..7806e1b 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -20,6 +20,7 @@
 #define _DDR_DEFS_H
 
 #include <asm/arch/hardware.h>
+#include <asm/emif.h>
 
 /* AM335X EMIF Register values */
 #define VTP_CTRL_READY		(0x1 << 5)
@@ -49,50 +50,19 @@
 #define DDR2_IOCTRL_VALUE	0x18B
 
 /**
- * Encapsulates DDR PHY control and corresponding shadow registers.
- */
-struct ddr_phy_control {
-	unsigned long	reg;
-	unsigned long	reg_sh;
-	unsigned long	reg2;
-};
-
-/**
- * Encapsulates SDRAM timing and corresponding shadow registers.
- */
-struct sdram_timing {
-	unsigned long	time1;
-	unsigned long	time1_sh;
-	unsigned long	time2;
-	unsigned long	time2_sh;
-	unsigned long	time3;
-	unsigned long	time3_sh;
-};
-
-/**
- * Encapsulates SDRAM configuration.
- * (Includes refresh control registers)  */
-struct sdram_config {
-	unsigned long	sdrcr;
-	unsigned long	sdrcr2;
-	unsigned long	refresh;
-	unsigned long	refresh_sh;
-};
-
-/**
  * Configure SDRAM
  */
-void config_sdram(struct sdram_config *cfg);
+void config_sdram(const struct emif_regs *regs);
 
 /**
  * Set SDRAM timings
  */
-void set_sdram_timings(struct sdram_timing *val);
+void set_sdram_timings(const struct emif_regs *regs);
 
 /**
  * Configure DDR PHY
  */
-void config_ddr_phy(struct ddr_phy_control *cfg);
+void config_ddr_phy(const struct emif_regs *regs);
 
 /**
  * This structure represents the DDR registers on AM33XX devices.
-- 
1.7.9.5

[U-Boot] [PATCH 16/17] am33xx: Rework config_io_ctrl slightly

[Tom Rini]

This function sets a number of related registers to the same value (the
registers in question all have the same field descriptions and are
related in operation).  Rather than defining a struct and setting the
value repeatedly, just pass in the value.

Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/am33xx/ddr.c             |   12 ++++++------
 arch/arm/cpu/armv7/am33xx/emif4.c           |   10 +---------
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |   13 +------------
 3 files changed, 8 insertions(+), 27 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index 993f3da..597d62f 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -120,11 +120,11 @@ void config_ddr_data(int macrono, const struct ddr_data *data)
 	writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
 }
 
-void config_io_ctrl(struct ddr_ioctrl *ioctrl)
+void config_io_ctrl(unsigned long val)
 {
-	writel(ioctrl->cmd1ctl, &ioctrl_reg->cm0ioctl);
-	writel(ioctrl->cmd2ctl, &ioctrl_reg->cm1ioctl);
-	writel(ioctrl->cmd3ctl, &ioctrl_reg->cm2ioctl);
-	writel(ioctrl->data1ctl, &ioctrl_reg->dt0ioctl);
-	writel(ioctrl->data2ctl, &ioctrl_reg->dt1ioctl);
+	writel(val, &ioctrl_reg->cm0ioctl);
+	writel(val, &ioctrl_reg->cm1ioctl);
+	writel(val, &ioctrl_reg->cm2ioctl);
+	writel(val, &ioctrl_reg->dt0ioctl);
+	writel(val, &ioctrl_reg->dt1ioctl);
 }
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 0190ec6..3219045 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -116,8 +116,6 @@ static void config_vtp(void)
 
 void config_ddr(short ddr_type)
 {
-	struct ddr_ioctrl ioctrl;
-
 	enable_emif_clocks();
 
 	if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
@@ -132,13 +130,7 @@ void config_ddr(short ddr_type)
 		writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
 		writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
 
-		ioctrl.cmd1ctl = DDR2_IOCTRL_VALUE;
-		ioctrl.cmd2ctl = DDR2_IOCTRL_VALUE;
-		ioctrl.cmd3ctl = DDR2_IOCTRL_VALUE;
-		ioctrl.data1ctl = DDR2_IOCTRL_VALUE;
-		ioctrl.data2ctl = DDR2_IOCTRL_VALUE;
-
-		config_io_ctrl(&ioctrl);
+		config_io_ctrl(DDR2_IOCTRL_VALUE);
 
 		/* Set CKE to be controlled by EMIF/DDR PHY */
 		writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 7806e1b..ebd3077 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -174,20 +174,9 @@ struct ddr_cmdtctrl {
 };
 
 /**
- * Encapsulates DDR CMD & DATA io control registers.
- */
-struct ddr_ioctrl {
-	unsigned long cmd1ctl;
-	unsigned long cmd2ctl;
-	unsigned long cmd3ctl;
-	unsigned long data1ctl;
-	unsigned long data2ctl;
-};
-
-/**
  * Configure DDR io control registers
  */
-void config_io_ctrl(struct ddr_ioctrl *ioctrl);
+void config_io_ctrl(unsigned long val);
 
 struct ddr_ctrl {
 	unsigned int ddrioctrl;
-- 
1.7.9.5

[U-Boot] [PATCH 17/17] am33xx: Do not touch 'ratio1' fields

[Tom Rini]

The various ratio1 fields are not documented in any of the documentation
I can find.  Removing these and testing has yielded success, so remove
the code that sets them and move their locations into the reserved
fields.

Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/am33xx/ddr.c             |   11 -----------
 arch/arm/cpu/armv7/am33xx/emif4.c           |    6 ------
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |   25 +++++++------------------
 3 files changed, 7 insertions(+), 35 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index 597d62f..59ca51f 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -101,22 +101,11 @@ void config_cmd_ctrl(const struct cmd_control *cmd)
 void config_ddr_data(int macrono, const struct ddr_data *data)
 {
 	writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
-	writel(data->datardsratio1, &ddr_reg[macrono]->dt0rdsratio1);
-
 	writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
-	writel(data->datawdsratio1, &ddr_reg[macrono]->dt0wdsratio1);
-
 	writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
-	writel(data->datawiratio1, &ddr_reg[macrono]->dt0wiratio1);
 	writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
-	writel(data->datagiratio1, &ddr_reg[macrono]->dt0giratio1);
-
 	writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
-	writel(data->datafwsratio1, &ddr_reg[macrono]->dt0fwsratio1);
-
 	writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
-	writel(data->datawrsratio1, &ddr_reg[macrono]->dt0wrsratio1);
-
 	writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
 }
 
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 3219045..ace3d26 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -51,22 +51,16 @@ void dram_init_banksize(void)
 static const struct ddr_data ddr2_data = {
 	.datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
 				|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
-	.datardsratio1 = DDR2_RD_DQS>>2,
 	.datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
 				|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
-	.datawdsratio1 = DDR2_WR_DQS>>2,
 	.datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
 				|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
-	.datawiratio1 = DDR2_PHY_WRLVL>>2,
 	.datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
 				|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
-	.datagiratio1 = DDR2_PHY_GATELVL>>2,
 	.datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
 				|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
-	.datafwsratio1 = DDR2_PHY_FIFO_WE>>2,
 	.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
 				|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
-	.datawrsratio1 = DDR2_PHY_WR_DATA>>2,
 	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index ebd3077..b37b161 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -88,25 +88,20 @@ struct ddr_regs {
 	unsigned int cm2iclkout;	/* offset 0x094 */
 	unsigned int resv3[12];
 	unsigned int dt0rdsratio0;	/* offset 0x0C8 */
-	unsigned int dt0rdsratio1;	/* offset 0x0CC */
-	unsigned int resv4[3];
+	unsigned int resv4[4];
 	unsigned int dt0wdsratio0;	/* offset 0x0DC */
-	unsigned int dt0wdsratio1;	/* offset 0x0E0 */
-	unsigned int resv5[3];
+	unsigned int resv5[4];
 	unsigned int dt0wiratio0;	/* offset 0x0F0 */
-	unsigned int dt0wiratio1;	/* offset 0x0F4 */
+	unsigned int resv6;
 	unsigned int dt0giratio0;	/* offset 0x0FC */
-	unsigned int dt0giratio1;	/* offset 0x100 */
-	unsigned int resv6[1];
+	unsigned int resv7[2];
 	unsigned int dt0fwsratio0;	/* offset 0x108 */
-	unsigned int dt0fwsratio1;	/* offset 0x10C */
-	unsigned int resv7[4];
+	unsigned int resv8[5];
 	unsigned int dt0wrsratio0;	/* offset 0x120 */
-	unsigned int dt0wrsratio1;	/* offset 0x124 */
-	unsigned int resv8[3];
+	unsigned int resv9[4];
 	unsigned int dt0rdelays0;	/* offset 0x134 */
 	unsigned int dt0dldiff0;	/* offset 0x138 */
-	unsigned int resv9[39];
+	unsigned int resv10[39];
 	unsigned int dt1rdelays0;	/* offset 0x1D8 */
 };
 
@@ -136,17 +131,11 @@ struct cmd_control {
  */
 struct ddr_data {
 	unsigned long datardsratio0;
-	unsigned long datardsratio1;
 	unsigned long datawdsratio0;
-	unsigned long datawdsratio1;
 	unsigned long datawiratio0;
-	unsigned long datawiratio1;
 	unsigned long datagiratio0;
-	unsigned long datagiratio1;
 	unsigned long datafwsratio0;
-	unsigned long datafwsratio1;
 	unsigned long datawrsratio0;
-	unsigned long datawrsratio1;
 	unsigned long datadldiff0;
 };
 
-- 
1.7.9.5

[U-Boot] [PATCH 18/17] am33xx: Correct and clean up ddr_regs struct

[Tom Rini]

The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry.
Correct this by documenting a missing register that will be used at some
point in the future (when write leveling is supported).  Further, the
cmdNcs{force,delay} fields are undocumented and we have been setting
them to zero, remove.  Next, setting of the
'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the
ddr_data entries, so program it there.  Finally, comment on how we are
configuring the DATA1 registers that correspond to the DATA0 (dt0)
registers defined in the struct.

Signed-off-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/armv7/am33xx/ddr.c             |    7 +----
 arch/arm/cpu/armv7/am33xx/emif4.c           |   10 +-------
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |   37 +++++++++++++--------------
 3 files changed, 20 insertions(+), 34 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index 59ca51f..bceed81 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -77,20 +77,14 @@ void config_ddr_phy(const struct emif_regs *regs)
 void config_cmd_ctrl(const struct cmd_control *cmd)
 {
 	writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
-	writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce);
-	writel(cmd->cmd0csdelay, &ddr_reg[0]->cm0csdelay);
 	writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
 	writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
 
 	writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
-	writel(cmd->cmd1csforce, &ddr_reg[0]->cm1csforce);
-	writel(cmd->cmd1csdelay, &ddr_reg[0]->cm1csdelay);
 	writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
 	writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
 
 	writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
-	writel(cmd->cmd2csforce, &ddr_reg[0]->cm2csforce);
-	writel(cmd->cmd2csdelay, &ddr_reg[0]->cm2csdelay);
 	writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
 	writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
 }
@@ -106,6 +100,7 @@ void config_ddr_data(int macrono, const struct ddr_data *data)
 	writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
 	writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
 	writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
+	writel(data->datauserank0delay, &ddr_reg[macrono]->dt0rdelays0);
 	writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
 }
 
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index ace3d26..3bb91d3 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -61,25 +61,20 @@ static const struct ddr_data ddr2_data = {
 				|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
 	.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
 				|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
+	.datauserank0delay = DDR2_PHY_RANK0_DELAY,
 	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 static const struct cmd_control ddr2_cmd_ctrl_data = {
 	.cmd0csratio = DDR2_RATIO,
-	.cmd0csforce = CMD_FORCE,
-	.cmd0csdelay = CMD_DELAY,
 	.cmd0dldiff = DDR2_DLL_LOCK_DIFF,
 	.cmd0iclkout = DDR2_INVERT_CLKOUT,
 
 	.cmd1csratio = DDR2_RATIO,
-	.cmd1csforce = CMD_FORCE,
-	.cmd1csdelay = CMD_DELAY,
 	.cmd1dldiff = DDR2_DLL_LOCK_DIFF,
 	.cmd1iclkout = DDR2_INVERT_CLKOUT,
 
 	.cmd2csratio = DDR2_RATIO,
-	.cmd2csforce = CMD_FORCE,
-	.cmd2csdelay = CMD_DELAY,
 	.cmd2dldiff = DDR2_DLL_LOCK_DIFF,
 	.cmd2iclkout = DDR2_INVERT_CLKOUT,
 };
@@ -121,9 +116,6 @@ void config_ddr(short ddr_type)
 		config_ddr_data(0, &ddr2_data);
 		config_ddr_data(1, &ddr2_data);
 
-		writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
-		writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
-
 		config_io_ctrl(DDR2_IOCTRL_VALUE);
 
 		/* Set CKE to be controlled by EMIF/DDR PHY */
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index b37b161..0526863 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -26,8 +26,6 @@
 #define VTP_CTRL_READY		(0x1 << 5)
 #define VTP_CTRL_ENABLE		(0x1 << 6)
 #define VTP_CTRL_START_EN	(0x1)
-#define CMD_FORCE		0x00
-#define CMD_DELAY		0x00
 #define PHY_DLL_LOCK_DIFF	0x0
 #define DDR_CKE_CTRL_NORMAL	0x1
 
@@ -66,43 +64,43 @@ void config_ddr_phy(const struct emif_regs *regs);
 
 /**
  * This structure represents the DDR registers on AM33XX devices.
+ * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
+ * correspond to DATA1 registers defined here.
  */
 struct ddr_regs {
 	unsigned int resv0[7];
 	unsigned int cm0csratio;	/* offset 0x01C */
-	unsigned int cm0csforce;	/* offset 0x020 */
-	unsigned int cm0csdelay;	/* offset 0x024 */
+	unsigned int resv1[2];
 	unsigned int cm0dldiff;		/* offset 0x028 */
 	unsigned int cm0iclkout;	/* offset 0x02C */
-	unsigned int resv1[8];
+	unsigned int resv2[8];
 	unsigned int cm1csratio;	/* offset 0x050 */
-	unsigned int cm1csforce;	/* offset 0x054 */
-	unsigned int cm1csdelay;	/* offset 0x058 */
+	unsigned int resv3[2];
 	unsigned int cm1dldiff;		/* offset 0x05C */
 	unsigned int cm1iclkout;	/* offset 0x060 */
-	unsigned int resv2[8];
+	unsigned int resv4[8];
 	unsigned int cm2csratio;	/* offset 0x084 */
-	unsigned int cm2csforce;	/* offset 0x088 */
-	unsigned int cm2csdelay;	/* offset 0x08C */
+	unsigned int resv5[2];
 	unsigned int cm2dldiff;		/* offset 0x090 */
 	unsigned int cm2iclkout;	/* offset 0x094 */
-	unsigned int resv3[12];
+	unsigned int resv6[12];
 	unsigned int dt0rdsratio0;	/* offset 0x0C8 */
-	unsigned int resv4[4];
+	unsigned int resv7[4];
 	unsigned int dt0wdsratio0;	/* offset 0x0DC */
-	unsigned int resv5[4];
+	unsigned int resv8[4];
 	unsigned int dt0wiratio0;	/* offset 0x0F0 */
-	unsigned int resv6;
+	unsigned int resv9;
+	unsigned int dt0wimode0;	/* offset 0x0F8 */
 	unsigned int dt0giratio0;	/* offset 0x0FC */
-	unsigned int resv7[2];
+	unsigned int resv10;
+	unsigned int dt0gimode0;	/* offset 0x104 */
 	unsigned int dt0fwsratio0;	/* offset 0x108 */
-	unsigned int resv8[5];
+	unsigned int resv11[4];
+	unsigned int dt0dqoffset;	/* offset 0x11C */
 	unsigned int dt0wrsratio0;	/* offset 0x120 */
-	unsigned int resv9[4];
+	unsigned int resv12[4];
 	unsigned int dt0rdelays0;	/* offset 0x134 */
 	unsigned int dt0dldiff0;	/* offset 0x138 */
-	unsigned int resv10[39];
-	unsigned int dt1rdelays0;	/* offset 0x1D8 */
 };
 
 /**
@@ -136,6 +134,7 @@ struct ddr_data {
 	unsigned long datagiratio0;
 	unsigned long datafwsratio0;
 	unsigned long datawrsratio0;
+	unsigned long datauserank0delay;
 	unsigned long datadldiff0;
 };
 
-- 
1.7.9.5

[U-Boot] [PATCH 01/17] omap3/omap4/omap5/am33xx: Use a common running_from_sdram function

[R, Sricharan]

Hi Tom,
[snip..]
> diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
> index 7f05cb5..c697e0b 100644
> --- a/arch/arm/include/asm/arch-omap5/omap.h
> +++ b/arch/arm/include/asm/arch-omap5/omap.h
> @@ -39,11 +39,6 @@
>  #define OMAP54XX_L4_WKUP_BASE  0x4Ae00000
>  #define OMAP54XX_L4_PER_BASE   0x48000000
>
> -#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
> -#define OMAP54XX_DRAM_ADDR_SPACE_END   0xFFFFFFFF
> -#define DRAM_ADDR_SPACE_START  OMAP54XX_DRAM_ADDR_SPACE_START
> -#define DRAM_ADDR_SPACE_END    OMAP54XX_DRAM_ADDR_SPACE_END
> -
  This is a problem for OMAP5, which has  a trap section at 0xFF000000
  with in the sdram boundary. OMAP5 evm board has 2GB of memory from
  0x80000000 - 0xFFFFFFFF.  Size of the trap section should not be
included in the
 total sdram size.

Thanks,
 Sricharan

[U-Boot] [PATCH 01/17] omap3/omap4/omap5/am33xx: Use a common running_from_sdram function

[Tom Rini]

On 07/31/2012 01:33 AM, R, Sricharan wrote:
> Hi Tom,
> [snip..]
>> diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
>> index 7f05cb5..c697e0b 100644
>> --- a/arch/arm/include/asm/arch-omap5/omap.h
>> +++ b/arch/arm/include/asm/arch-omap5/omap.h
>> @@ -39,11 +39,6 @@
>>  #define OMAP54XX_L4_WKUP_BASE  0x4Ae00000
>>  #define OMAP54XX_L4_PER_BASE   0x48000000
>>
>> -#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
>> -#define OMAP54XX_DRAM_ADDR_SPACE_END   0xFFFFFFFF
>> -#define DRAM_ADDR_SPACE_START  OMAP54XX_DRAM_ADDR_SPACE_START
>> -#define DRAM_ADDR_SPACE_END    OMAP54XX_DRAM_ADDR_SPACE_END
>> -
>   This is a problem for OMAP5, which has  a trap section at 0xFF000000
>   with in the sdram boundary. OMAP5 evm board has 2GB of memory from
>   0x80000000 - 0xFFFFFFFF.  Size of the trap section should not be
> included in the
>  total sdram size.

But it's not sdram size.  What happens when you're executing at the trap
section, or rather, where are you executing code from?

-- 
Tom

[U-Boot] [PATCH 01/17] omap3/omap4/omap5/am33xx: Use a common running_from_sdram function

[R, Sricharan]

Hi Tom,

On Tue, Jul 31, 2012 at 8:43 PM, Tom Rini <trini@ti.com> wrote:
> On 07/31/2012 01:33 AM, R, Sricharan wrote:
>> Hi Tom,
>> [snip..]
>>> diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
>>> index 7f05cb5..c697e0b 100644
>>> --- a/arch/arm/include/asm/arch-omap5/omap.h
>>> +++ b/arch/arm/include/asm/arch-omap5/omap.h
>>> @@ -39,11 +39,6 @@
>>>  #define OMAP54XX_L4_WKUP_BASE  0x4Ae00000
>>>  #define OMAP54XX_L4_PER_BASE   0x48000000
>>>
>>> -#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
>>> -#define OMAP54XX_DRAM_ADDR_SPACE_END   0xFFFFFFFF
>>> -#define DRAM_ADDR_SPACE_START  OMAP54XX_DRAM_ADDR_SPACE_START
>>> -#define DRAM_ADDR_SPACE_END    OMAP54XX_DRAM_ADDR_SPACE_END
>>> -
>>   This is a problem for OMAP5, which has  a trap section at 0xFF000000
>>   with in the sdram boundary. OMAP5 evm board has 2GB of memory from
>>   0x80000000 - 0xFFFFFFFF.  Size of the trap section should not be
>> included in the
>>  total sdram size.
>
> But it's not sdram size.  What happens when you're executing at the trap
> section, or rather, where are you executing code from?

   When we execute at trap section address, the system aborts.
   EMIF returns a exception. This is to catch the unmapped tiler
   entries.
    So total size of sdram size calculated should subtract the size
   of trap section if that falls with in the sdram boundary,
   as in case of omap5.  This is taken care in omap_sdram_size
   function.  But with this change the trap section will go un-noticed.

Thanks,
 Sricharan

[U-Boot] [PATCH 01/17] omap3/omap4/omap5/am33xx: Use a common running_from_sdram function

[Tom Rini]

On 07/31/2012 08:27 AM, R, Sricharan wrote:
> Hi Tom,
> 
> On Tue, Jul 31, 2012 at 8:43 PM, Tom Rini <trini@ti.com> wrote:
>> On 07/31/2012 01:33 AM, R, Sricharan wrote:
>>> Hi Tom,
>>> [snip..]
>>>> diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
>>>> index 7f05cb5..c697e0b 100644
>>>> --- a/arch/arm/include/asm/arch-omap5/omap.h
>>>> +++ b/arch/arm/include/asm/arch-omap5/omap.h
>>>> @@ -39,11 +39,6 @@
>>>>  #define OMAP54XX_L4_WKUP_BASE  0x4Ae00000
>>>>  #define OMAP54XX_L4_PER_BASE   0x48000000
>>>>
>>>> -#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
>>>> -#define OMAP54XX_DRAM_ADDR_SPACE_END   0xFFFFFFFF
>>>> -#define DRAM_ADDR_SPACE_START  OMAP54XX_DRAM_ADDR_SPACE_START
>>>> -#define DRAM_ADDR_SPACE_END    OMAP54XX_DRAM_ADDR_SPACE_END
>>>> -
>>>   This is a problem for OMAP5, which has  a trap section at 0xFF000000
>>>   with in the sdram boundary. OMAP5 evm board has 2GB of memory from
>>>   0x80000000 - 0xFFFFFFFF.  Size of the trap section should not be
>>> included in the
>>>  total sdram size.
>>
>> But it's not sdram size.  What happens when you're executing at the trap
>> section, or rather, where are you executing code from?
> 
>    When we execute at trap section address, the system aborts.
>    EMIF returns a exception. This is to catch the unmapped tiler
>    entries.
>     So total size of sdram size calculated should subtract the size
>    of trap section if that falls with in the sdram boundary,
>    as in case of omap5.  This is taken care in omap_sdram_size
>    function.  But with this change the trap section will go un-noticed.

So you're saying the problem is that 0xFF... needs to be included in
DRAM_ADDR_SPACE on omap5?

-- 
Tom

[U-Boot] [PATCH 01/17] omap3/omap4/omap5/am33xx: Use a common running_from_sdram function

[R, Sricharan]

Correct.
DRAM_ADDR_SPACE_END should be 0xFFFFFFFF for OMAP5.

Thanks,
 Sricharan

On Tue, Jul 31, 2012 at 9:12 PM, Tom Rini <trini@ti.com> wrote:
> On 07/31/2012 08:27 AM, R, Sricharan wrote:
>> Hi Tom,
>>
>> On Tue, Jul 31, 2012 at 8:43 PM, Tom Rini <trini@ti.com> wrote:
>>> On 07/31/2012 01:33 AM, R, Sricharan wrote:
>>>> Hi Tom,
>>>> [snip..]
>>>>> diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
>>>>> index 7f05cb5..c697e0b 100644
>>>>> --- a/arch/arm/include/asm/arch-omap5/omap.h
>>>>> +++ b/arch/arm/include/asm/arch-omap5/omap.h
>>>>> @@ -39,11 +39,6 @@
>>>>>  #define OMAP54XX_L4_WKUP_BASE  0x4Ae00000
>>>>>  #define OMAP54XX_L4_PER_BASE   0x48000000
>>>>>
>>>>> -#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
>>>>> -#define OMAP54XX_DRAM_ADDR_SPACE_END   0xFFFFFFFF
>>>>> -#define DRAM_ADDR_SPACE_START  OMAP54XX_DRAM_ADDR_SPACE_START
>>>>> -#define DRAM_ADDR_SPACE_END    OMAP54XX_DRAM_ADDR_SPACE_END
>>>>> -
>>>>   This is a problem for OMAP5, which has  a trap section at 0xFF000000
>>>>   with in the sdram boundary. OMAP5 evm board has 2GB of memory from
>>>>   0x80000000 - 0xFFFFFFFF.  Size of the trap section should not be
>>>> included in the
>>>>  total sdram size.
>>>
>>> But it's not sdram size.  What happens when you're executing at the trap
>>> section, or rather, where are you executing code from?
>>
>>    When we execute at trap section address, the system aborts.
>>    EMIF returns a exception. This is to catch the unmapped tiler
>>    entries.
>>     So total size of sdram size calculated should subtract the size
>>    of trap section if that falls with in the sdram boundary,
>>    as in case of omap5.  This is taken care in omap_sdram_size
>>    function.  But with this change the trap section will go un-noticed.
>
> So you're saying the problem is that 0xFF... needs to be included in
> DRAM_ADDR_SPACE on omap5?
>
> --
> Tom

[U-Boot] [PATCH 01/17] omap3/omap4/omap5/am33xx: Use a common running_from_sdram function

[Tom Rini]

On 07/31/2012 08:46 AM, R, Sricharan wrote:
> Correct.
> DRAM_ADDR_SPACE_END should be 0xFFFFFFFF for OMAP5.

OK, I will just drop this.

> 
> Thanks,
>  Sricharan
> 
> On Tue, Jul 31, 2012 at 9:12 PM, Tom Rini <trini@ti.com> wrote:
>> On 07/31/2012 08:27 AM, R, Sricharan wrote:
>>> Hi Tom,
>>>
>>> On Tue, Jul 31, 2012 at 8:43 PM, Tom Rini <trini@ti.com> wrote:
>>>> On 07/31/2012 01:33 AM, R, Sricharan wrote:
>>>>> Hi Tom,
>>>>> [snip..]
>>>>>> diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
>>>>>> index 7f05cb5..c697e0b 100644
>>>>>> --- a/arch/arm/include/asm/arch-omap5/omap.h
>>>>>> +++ b/arch/arm/include/asm/arch-omap5/omap.h
>>>>>> @@ -39,11 +39,6 @@
>>>>>>  #define OMAP54XX_L4_WKUP_BASE  0x4Ae00000
>>>>>>  #define OMAP54XX_L4_PER_BASE   0x48000000
>>>>>>
>>>>>> -#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
>>>>>> -#define OMAP54XX_DRAM_ADDR_SPACE_END   0xFFFFFFFF
>>>>>> -#define DRAM_ADDR_SPACE_START  OMAP54XX_DRAM_ADDR_SPACE_START
>>>>>> -#define DRAM_ADDR_SPACE_END    OMAP54XX_DRAM_ADDR_SPACE_END
>>>>>> -
>>>>>   This is a problem for OMAP5, which has  a trap section at 0xFF000000
>>>>>   with in the sdram boundary. OMAP5 evm board has 2GB of memory from
>>>>>   0x80000000 - 0xFFFFFFFF.  Size of the trap section should not be
>>>>> included in the
>>>>>  total sdram size.
>>>>
>>>> But it's not sdram size.  What happens when you're executing at the trap
>>>> section, or rather, where are you executing code from?
>>>
>>>    When we execute at trap section address, the system aborts.
>>>    EMIF returns a exception. This is to catch the unmapped tiler
>>>    entries.
>>>     So total size of sdram size calculated should subtract the size
>>>    of trap section if that falls with in the sdram boundary,
>>>    as in case of omap5.  This is taken care in omap_sdram_size
>>>    function.  But with this change the trap section will go un-noticed.
>>
>> So you're saying the problem is that 0xFF... needs to be included in
>> DRAM_ADDR_SPACE on omap5?
>>
>> --
>> Tom

[U-Boot] [PATCH 02/17] am335x_evm: Update config for common usage

[Tom Rini]

On Mon, Jul 30, 2012 at 09:48:48AM -0700, Tom Rini wrote:

> - Add default commands
> - Add HUSH parser
> - Make environment, malloc areas larger
> - Add ATAGS and OF_LIBFDT
> - Add defaults to boot ramdisk and MMC, use uEnv.txt
> 
> Signed-off-by: Tom Rini <trini@ti.com>

I plan to commit this with the following minor addition:

diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index e915f56..36f9152 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -48,6 +48,7 @@
 #define CONFIG_BOOTDELAY		3
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x80200000\0" \
+	"dtbaddr=0x80F80000\0" \
 	"rdaddr=0x81000000\0" \
 	"bootfile=/boot/uImage\0" \
 	"console=ttyO0,115200n8\0" \

This still leaves a ton of room between the kernel load and
ramdisk/device tree, and sets aside as much room as the PowerPC boards
have been.

-- 
Tom