[U-Boot] [PATCH v2 0/4] DaVinci DA8xx: tidy up clock IDs

[Prabhakar Lad <prabhakar.lad@ti.com>]

Hi Laurence,

On Tuesday 31 July 2012 03:00 PM, Laurence Withers wrote:
> This small series of patches tidies up the clock IDs that are used to interact
> with the PLL controllers on the DaVinci DA8xx processors.
>
> It more clearly defines the structure and meaning of the IDs and untangles some
> model-specific code that can't be shared among the family. This tidying allows
> three bugs to be identified and resolved:
>   - on the DA850, UART2's clock may come from ASYNC3, unlike the DA830;
>   - the DA830 doesn't have a DDR2/mDDR PHY, or a PLL controller for it;
>   - the DSP speed reported by bdinfo was not being initialised on the DA8xx
>     family.
     I have tested  the entire patchset on da850, da830, dm355, dm6446
     and  dm365 evm's.

     Tested-by: Prabhakar Lad <prabhakar.lad@ti.com>

     Thx,
     --Prabhakar Lad
> Laurence Withers (4):
>    DaVinci DA8xx: tidy up clock ID definition
>    DaVinci DA850: UART2 clock ID comes from ASYNC3
>    DaVinci DA8xx: replace magic number for DDR speed
>    DaVinci DA8xx: fix set_cpu_clk_info()
>
>   arch/arm/cpu/arm926ejs/davinci/cpu.c         |   22 ++++++----
>   arch/arm/include/asm/arch-davinci/hardware.h |   57 +++++++++++++++++++------
>   2 files changed, 57 insertions(+), 22 deletions(-)
>