* [U-Boot] [PATCH 00/11] Support for ST-Ericsson snowball board
@ 2012-07-31 18:59 mathieu.poirier at linaro.org
2012-07-31 18:59 ` [U-Boot] [PATCH 01/11] snowball: Add support for ux500 based " mathieu.poirier at linaro.org
` (11 more replies)
0 siblings, 12 replies; 24+ messages in thread
From: mathieu.poirier at linaro.org @ 2012-07-31 18:59 UTC (permalink / raw)
To: u-boot
From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org>
This set adds support for the ST-Ericsson u8500 based
snowball board. Doing so it moves u8500-href code around
to allow for code reuse between boards.
It was sent out during the 12.07 cycle but never received
an official ACK.
John Rigby (1):
u8500: Separating mmc config parameters from driver
Mathieu J. Poirier (10):
snowball: Add support for ux500 based snowball board
u8500: Moving prcmu to cpu directory
snowball: Adding architecture dependent initialisation
snowball: Adding CPU clock initialisation
snowball: Moving to ux500.v2 addess scheme for PRCMU access
snowball: applying power to LAN and GBF controllers
u8500: Moving processor-specific functions to cpu area.
u8500: Enabling power to MMC device on AB8500 V2
armv7: Adding cpu specific cache managmenent
snowball: Adding board specific cache cleanup routine
MAINTAINERS | 4 +
arch/arm/cpu/armv7/cpu.c | 8 +
arch/arm/cpu/armv7/u8500/Makefile | 2 +-
arch/arm/cpu/armv7/u8500/clock.c | 34 +
arch/arm/cpu/armv7/u8500/cpu.c | 192 ++++++
arch/arm/cpu/armv7/u8500/prcmu.c | 229 +++++++
arch/arm/include/asm/arch-u8500/clock.h | 5 +-
arch/arm/include/asm/arch-u8500/db8500_gpio.h | 42 ++
arch/arm/include/asm/arch-u8500/db8500_pincfg.h | 170 +++++
arch/arm/include/asm/arch-u8500/hardware.h | 33 +-
arch/arm/include/asm/arch-u8500/prcmu.h | 76 +++
arch/arm/include/asm/arch-u8500/sys_proto.h | 1 +
board/armltd/vexpress/ca9x4_ct_vxp.c | 21 +-
board/st-ericsson/snowball/Makefile | 51 ++
board/st-ericsson/snowball/db8500_pins.h | 745 +++++++++++++++++++++++
board/st-ericsson/snowball/snowball.c | 367 +++++++++++
board/st-ericsson/u8500/Makefile | 2 +-
board/st-ericsson/u8500/prcmu-fw.h | 55 --
board/st-ericsson/u8500/prcmu.c | 165 -----
board/st-ericsson/u8500/u8500_href.c | 99 +---
boards.cfg | 1 +
drivers/gpio/Makefile | 1 +
drivers/gpio/db8500_gpio.c | 225 +++++++
drivers/mmc/arm_pl180_mmci.c | 132 ++---
drivers/mmc/arm_pl180_mmci.h | 27 +-
drivers/serial/serial_pl01x.c | 2 +
include/configs/snowball.h | 268 ++++++++
27 files changed, 2566 insertions(+), 391 deletions(-)
create mode 100644 arch/arm/cpu/armv7/u8500/cpu.c
create mode 100644 arch/arm/cpu/armv7/u8500/prcmu.c
create mode 100644 arch/arm/include/asm/arch-u8500/db8500_gpio.h
create mode 100644 arch/arm/include/asm/arch-u8500/db8500_pincfg.h
create mode 100644 arch/arm/include/asm/arch-u8500/prcmu.h
create mode 100644 board/st-ericsson/snowball/Makefile
create mode 100644 board/st-ericsson/snowball/db8500_pins.h
create mode 100644 board/st-ericsson/snowball/snowball.c
delete mode 100644 board/st-ericsson/u8500/prcmu-fw.h
delete mode 100644 board/st-ericsson/u8500/prcmu.c
create mode 100644 drivers/gpio/db8500_gpio.c
create mode 100644 include/configs/snowball.h
--
1.7.5.4
^ permalink raw reply [flat|nested] 24+ messages in thread* [U-Boot] [PATCH 01/11] snowball: Add support for ux500 based snowball board 2012-07-31 18:59 [U-Boot] [PATCH 00/11] Support for ST-Ericsson snowball board mathieu.poirier at linaro.org @ 2012-07-31 18:59 ` mathieu.poirier at linaro.org 2012-08-03 14:46 ` Tom Rini 2012-08-03 15:32 ` Tom Rini 2012-07-31 18:59 ` [U-Boot] [PATCH 02/11] u8500: Moving prcmu to cpu directory mathieu.poirier at linaro.org ` (10 subsequent siblings) 11 siblings, 2 replies; 24+ messages in thread From: mathieu.poirier at linaro.org @ 2012-07-31 18:59 UTC (permalink / raw) To: u-boot From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> --- MAINTAINERS | 4 + arch/arm/include/asm/arch-u8500/db8500_gpio.h | 42 ++ arch/arm/include/asm/arch-u8500/db8500_pincfg.h | 170 +++++ board/st-ericsson/snowball/Makefile | 51 ++ board/st-ericsson/snowball/db8500_pins.h | 745 +++++++++++++++++++++++ board/st-ericsson/snowball/snowball.c | 185 ++++++ boards.cfg | 1 + drivers/gpio/Makefile | 1 + drivers/gpio/db8500_gpio.c | 225 +++++++ drivers/serial/serial_pl01x.c | 2 + include/configs/snowball.h | 258 ++++++++ 11 files changed, 1684 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-u8500/db8500_gpio.h create mode 100644 arch/arm/include/asm/arch-u8500/db8500_pincfg.h create mode 100644 board/st-ericsson/snowball/Makefile create mode 100644 board/st-ericsson/snowball/db8500_pins.h create mode 100644 board/st-ericsson/snowball/snowball.c create mode 100644 drivers/gpio/db8500_gpio.c create mode 100644 include/configs/snowball.h diff --git a/MAINTAINERS b/MAINTAINERS index fd0c65c..8a16b12 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -959,6 +959,10 @@ Vladimir Zapolskiy <vz@mleia.com> devkit3250 lpc32xx +Mathieu Poirier <mathieu.poirier@linaro.org> + + snowball ARM ARMV7 (u8500 SoC) + ------------------------------------------------------------------------- Unknown / orphaned boards: diff --git a/arch/arm/include/asm/arch-u8500/db8500_gpio.h b/arch/arm/include/asm/arch-u8500/db8500_gpio.h new file mode 100644 index 0000000..7c85a89 --- /dev/null +++ b/arch/arm/include/asm/arch-u8500/db8500_gpio.h @@ -0,0 +1,42 @@ +/* + * Structures and registers for GPIO access in the Nomadik SoC + * + * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. + * The purpose is that GPIO config found in kernel should work by simply + * copy-paste it to U-boot. + * + * Ported to U-boot by: + * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com> + * Copyright (C) 2008 STMicroelectronics + * Author: Prafulla WADASKAR <prafulla.wadaskar@st.com> + * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DB8500_GPIO_H__ +#define __DB8500_GPIO_H__ + +/* Alternate functions: function C is set in hw by setting both A and B */ +enum db8500_gpio_alt { + DB8500_GPIO_ALT_GPIO = 0, + DB8500_GPIO_ALT_A = 1, + DB8500_GPIO_ALT_B = 2, + DB8500_GPIO_ALT_C = (DB8500_GPIO_ALT_A | DB8500_GPIO_ALT_B) +}; + +enum db8500_gpio_pull { + DB8500_GPIO_PULL_NONE, + DB8500_GPIO_PULL_UP, + DB8500_GPIO_PULL_DOWN +}; + +void db8500_gpio_set_pull(unsigned gpio, enum db8500_gpio_pull pull); +void db8500_gpio_make_input(unsigned gpio); +int db8500_gpio_get_input(unsigned gpio); +void db8500_gpio_make_output(unsigned gpio, int val); +void db8500_gpio_set_output(unsigned gpio, int val); + +#endif /* __DB8500_GPIO_H__ */ diff --git a/arch/arm/include/asm/arch-u8500/db8500_pincfg.h b/arch/arm/include/asm/arch-u8500/db8500_pincfg.h new file mode 100644 index 0000000..6495701 --- /dev/null +++ b/arch/arm/include/asm/arch-u8500/db8500_pincfg.h @@ -0,0 +1,170 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. + * The purpose is that GPIO config found in kernel should work by simply + * copy-paste it to U-boot. Ported 2010 to U-boot by: + * Author: Joakim Axelsson <joakim.axelsson AT stericsson.com> + * + * License terms: GNU General Public License, version 2 + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson + * + * + * Based on arch/arm/mach-pxa/include/mach/mfp.h: + * Copyright (C) 2007 Marvell International Ltd. + * eric miao <eric.miao@marvell.com> + */ + +#ifndef __DB8500_PINCFG_H +#define __DB8500_PINCFG_H + +#include "db8500_gpio.h" + +/* + * U-boot info: + * SLPM (sleep mode) config will be ignored by U-boot but it is still + * possible to configure it in order to keep cut-n-paste compability + * with Linux kernel config. + * + * pin configurations are represented by 32-bit integers: + * + * bit 0.. 8 - Pin Number (512 Pins Maximum) + * bit 9..10 - Alternate Function Selection + * bit 11..12 - Pull up/down state + * bit 13 - Sleep mode behaviour (not used in U-boot) + * bit 14 - Direction + * bit 15 - Value (if output) + * bit 16..18 - SLPM pull up/down state (not used in U-boot) + * bit 19..20 - SLPM direction (not used in U-boot) + * bit 21..22 - SLPM Value (if output) (not used in U-boot) + * + * to facilitate the definition, the following macros are provided + * + * PIN_CFG_DEFAULT - default config (0): + * pull up/down = disabled + * sleep mode = input/wakeup + * direction = input + * value = low + * SLPM direction = same as normal + * SLPM pull = same as normal + * SLPM value = same as normal + * + * PIN_CFG - default config with alternate function + * PIN_CFG_PULL - default config with alternate function and pull up/down + */ + +/* Sleep mode */ +enum db8500_gpio_slpm { + DB8500_GPIO_SLPM_INPUT, + DB8500_GPIO_SLPM_WAKEUP_ENABLE = DB8500_GPIO_SLPM_INPUT, + DB8500_GPIO_SLPM_NOCHANGE, + DB8500_GPIO_SLPM_WAKEUP_DISABLE = DB8500_GPIO_SLPM_NOCHANGE, +}; + +#define PIN_NUM_MASK 0x1ff +#define PIN_NUM(x) ((x) & PIN_NUM_MASK) + +#define PIN_ALT_SHIFT 9 +#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT) +#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT) +#define PIN_GPIO (DB8500_GPIO_ALT_GPIO << PIN_ALT_SHIFT) +#define PIN_ALT_A (DB8500_GPIO_ALT_A << PIN_ALT_SHIFT) +#define PIN_ALT_B (DB8500_GPIO_ALT_B << PIN_ALT_SHIFT) +#define PIN_ALT_C (DB8500_GPIO_ALT_C << PIN_ALT_SHIFT) + +#define PIN_PULL_SHIFT 11 +#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT) +#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT) +#define PIN_PULL_NONE (DB8500_GPIO_PULL_NONE << PIN_PULL_SHIFT) +#define PIN_PULL_UP (DB8500_GPIO_PULL_UP << PIN_PULL_SHIFT) +#define PIN_PULL_DOWN (DB8500_GPIO_PULL_DOWN << PIN_PULL_SHIFT) + +#define PIN_SLPM_SHIFT 13 +#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) +#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) +#define PIN_SLPM_MAKE_INPUT (DB8500_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) +#define PIN_SLPM_NOCHANGE (DB8500_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) +/* These two replace the above in DB8500v2+ */ +#define PIN_SLPM_WAKEUP_ENABLE \ + (DB8500_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) +#define PIN_SLPM_WAKEUP_DISABLE \ + (DB8500_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) + +#define PIN_DIR_SHIFT 14 +#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) +#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT) +#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT) +#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT) + +#define PIN_VAL_SHIFT 15 +#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT) +#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT) +#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) +#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) + +#define PIN_SLPM_PULL_SHIFT 16 +#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL(x) \ + (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL_NONE \ + ((1 + DB8500_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL_UP \ + ((1 + DB8500_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL_DOWN \ + ((1 + DB8500_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) + +#define PIN_SLPM_DIR_SHIFT 19 +#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) +#define PIN_SLPM_DIR(x) \ + (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) +#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) +#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) + +#define PIN_SLPM_VAL_SHIFT 21 +#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) +#define PIN_SLPM_VAL(x) \ + (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) +#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) +#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) + +/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ +#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) +#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) +#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) +#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) +#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) + +#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) +#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) +#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) +#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) +#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) + +#define PIN_CFG_DEFAULT (0) + +#define PIN_CFG(num, alt) \ + (PIN_CFG_DEFAULT |\ + (PIN_NUM(num) | PIN_##alt)) + +#define PIN_CFG_INPUT(num, alt, pull) \ + (PIN_CFG_DEFAULT |\ + (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) + +#define PIN_CFG_OUTPUT(num, alt, val) \ + (PIN_CFG_DEFAULT |\ + (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) + +#define PIN_CFG_PULL(num, alt, pull) \ + ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\ + (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull)) + +/** + * db8500_gpio_config_pins - configure several pins@once + * @cfgs: array of pin configurations + * @num: number of elments in the array + * + * Configures several GPIO pins. + */ +void db8500_gpio_config_pins(unsigned long *cfgs, size_t num); + +#endif diff --git a/board/st-ericsson/snowball/Makefile b/board/st-ericsson/snowball/Makefile new file mode 100644 index 0000000..6138296 --- /dev/null +++ b/board/st-ericsson/snowball/Makefile @@ -0,0 +1,51 @@ +# +# Copyright (C) ST-Ericsson SA 2009 +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +CFLAGS += -D__RELEASE -D__STN_8500 +LIB = $(obj)lib$(BOARD).o + +COBJS := snowball.o + +#prcmu.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/st-ericsson/snowball/db8500_pins.h b/board/st-ericsson/snowball/db8500_pins.h new file mode 100644 index 0000000..e339cb8 --- /dev/null +++ b/board/st-ericsson/snowball/db8500_pins.h @@ -0,0 +1,745 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. + * The purpose is that GPIO config found in kernel should work by simply + * copy-paste it to U-boot. + * + * Ported to U-boot by: + * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com> + ** + * License terms: GNU General Public License, version 2 + * Author: Rabin Vincent <rabin.vincent@stericsson.com> + */ + +#ifndef __DB8500_PINS_H +#define __DB8500_PINS_H + +#include <asm/arch/db8500_pincfg.h> + +#define GPIO0_GPIO PIN_CFG(0, GPIO) +#define GPIO0_U0_CTSn PIN_CFG(0, ALT_A) +#define GPIO0_TRIG_OUT PIN_CFG(0, ALT_B) +#define GPIO0_IP_TDO PIN_CFG(0, ALT_C) + +#define GPIO1_GPIO PIN_CFG(1, GPIO) +#define GPIO1_U0_RTSn PIN_CFG(1, ALT_A) +#define GPIO1_TRIG_IN PIN_CFG(1, ALT_B) +#define GPIO1_IP_TDI PIN_CFG(1, ALT_C) + +#define GPIO2_GPIO PIN_CFG(2, GPIO) +#define GPIO2_U0_RXD PIN_CFG(2, ALT_A) +#define GPIO2_NONE PIN_CFG(2, ALT_B) +#define GPIO2_IP_TMS PIN_CFG(2, ALT_C) + +#define GPIO3_GPIO PIN_CFG(3, GPIO) +#define GPIO3_U0_TXD PIN_CFG(3, ALT_A) +#define GPIO3_NONE PIN_CFG(3, ALT_B) +#define GPIO3_IP_TCK PIN_CFG(3, ALT_C) + +#define GPIO4_GPIO PIN_CFG(4, GPIO) +#define GPIO4_U1_RXD PIN_CFG(4, ALT_A) +#define GPIO4_I2C4_SCL PIN_CFG_PULL(4, ALT_B, UP) +#define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C) + +#define GPIO5_GPIO PIN_CFG(5, GPIO) +#define GPIO5_U1_TXD PIN_CFG(5, ALT_A) +#define GPIO5_I2C4_SDA PIN_CFG_PULL(5, ALT_B, UP) +#define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C) + +#define GPIO6_GPIO PIN_CFG(6, GPIO) +#define GPIO6_U1_CTSn PIN_CFG(6, ALT_A) +#define GPIO6_I2C1_SCL PIN_CFG_PULL(6, ALT_B, UP) +#define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C) + +#define GPIO7_GPIO PIN_CFG(7, GPIO) +#define GPIO7_U1_RTSn PIN_CFG(7, ALT_A) +#define GPIO7_I2C1_SDA PIN_CFG_PULL(7, ALT_B, UP) +#define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C) + +#define GPIO8_GPIO PIN_CFG(8, GPIO) +#define GPIO8_IPI2C_SDA PIN_CFG_PULL(8, ALT_A, UP) +#define GPIO8_I2C2_SDA PIN_CFG_PULL(8, ALT_B, UP) + +#define GPIO9_GPIO PIN_CFG(9, GPIO) +#define GPIO9_IPI2C_SCL PIN_CFG_PULL(9, ALT_A, UP) +#define GPIO9_I2C2_SCL PIN_CFG_PULL(9, ALT_B, UP) + +#define GPIO10_GPIO PIN_CFG(10, GPIO) +#define GPIO10_IPI2C_SDA PIN_CFG_PULL(10, ALT_A, UP) +#define GPIO10_I2C2_SDA PIN_CFG_PULL(10, ALT_B, UP) +#define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C) + +#define GPIO11_GPIO PIN_CFG(11, GPIO) +#define GPIO11_IPI2C_SCL PIN_CFG_PULL(11, ALT_A, UP) +#define GPIO11_I2C2_SCL PIN_CFG_PULL(11, ALT_B, UP) +#define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C) + +#define GPIO12_GPIO PIN_CFG(12, GPIO) +#define GPIO12_MSP0_TXD PIN_CFG(12, ALT_A) +#define GPIO12_MSP0_RXD PIN_CFG(12, ALT_B) + +#define GPIO13_GPIO PIN_CFG(13, GPIO) +#define GPIO13_MSP0_TFS PIN_CFG(13, ALT_A) + +#define GPIO14_GPIO PIN_CFG(14, GPIO) +#define GPIO14_MSP0_TCK PIN_CFG(14, ALT_A) + +#define GPIO15_GPIO PIN_CFG(15, GPIO) +#define GPIO15_MSP0_RXD PIN_CFG(15, ALT_A) +#define GPIO15_MSP0_TXD PIN_CFG(15, ALT_B) + +#define GPIO16_GPIO PIN_CFG(16, GPIO) +#define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A) +#define GPIO16_I2C1_SCL PIN_CFG_PULL(16, ALT_B, UP) +#define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C) + +#define GPIO17_GPIO PIN_CFG(17, GPIO) +#define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A) +#define GPIO17_I2C1_SDA PIN_CFG_PULL(17, ALT_B, UP) +#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C) + +#define GPIO18_GPIO PIN_CFG(18, GPIO) +#define GPIO18_MC0_CMDDIR PIN_CFG(18, ALT_A) +#define GPIO18_U2_RXD PIN_CFG(18, ALT_B) +#define GPIO18_MS_IEP PIN_CFG(18, ALT_C) + +#define GPIO19_GPIO PIN_CFG(19, GPIO) +#define GPIO19_MC0_DAT0DIR PIN_CFG(19, ALT_A) +#define GPIO19_U2_TXD PIN_CFG(19, ALT_B) +#define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C) + +#define GPIO20_GPIO PIN_CFG(20, GPIO) +#define GPIO20_MC0_DAT2DIR PIN_CFG(20, ALT_A) +#define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B) +#define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C) + +#define GPIO21_GPIO PIN_CFG(21, GPIO) +#define GPIO21_MC0_DAT31DIR PIN_CFG(21, ALT_A) +#define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B) +#define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C) + +#define GPIO22_GPIO PIN_CFG(22, GPIO) +#define GPIO22_MC0_FBCLK PIN_CFG(22, ALT_A) +#define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B) +#define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C) + +#define GPIO23_GPIO PIN_CFG(23, GPIO) +#define GPIO23_MC0_CLK PIN_CFG(23, ALT_A) +#define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B) +#define GPIO23_MS_CLK PIN_CFG(23, ALT_C) + +#define GPIO24_GPIO PIN_CFG(24, GPIO) +#define GPIO24_MC0_CMD PIN_CFG(24, ALT_A) +#define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B) +#define GPIO24_MS_BS PIN_CFG(24, ALT_C) + +#define GPIO25_GPIO PIN_CFG(25, GPIO) +#define GPIO25_MC0_DAT0 PIN_CFG(25, ALT_A) +#define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B) +#define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C) + +#define GPIO26_GPIO PIN_CFG(26, GPIO) +#define GPIO26_MC0_DAT1 PIN_CFG(26, ALT_A) +#define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B) +#define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C) + +#define GPIO27_GPIO PIN_CFG(27, GPIO) +#define GPIO27_MC0_DAT2 PIN_CFG(27, ALT_A) +#define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B) +#define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C) + +#define GPIO28_GPIO PIN_CFG(28, GPIO) +#define GPIO28_MC0_DAT3 PIN_CFG(28, ALT_A) +#define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B) +#define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C) + +#define GPIO29_GPIO PIN_CFG(29, GPIO) +#define GPIO29_MC0_DAT4 PIN_CFG(29, ALT_A) +#define GPIO29_SPI3_CLK PIN_CFG(29, ALT_B) +#define GPIO29_U2_RXD PIN_CFG(29, ALT_C) + +#define GPIO30_GPIO PIN_CFG(30, GPIO) +#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A) +#define GPIO30_SPI3_RXD PIN_CFG(30, ALT_B) +#define GPIO30_U2_TXD PIN_CFG(30, ALT_C) + +#define GPIO31_GPIO PIN_CFG(31, GPIO) +#define GPIO31_MC0_DAT6 PIN_CFG(31, ALT_A) +#define GPIO31_SPI3_FRM PIN_CFG(31, ALT_B) +#define GPIO31_U2_CTSn PIN_CFG(31, ALT_C) + +#define GPIO32_GPIO PIN_CFG(32, GPIO) +#define GPIO32_MC0_DAT7 PIN_CFG(32, ALT_A) +#define GPIO32_SPI3_TXD PIN_CFG(32, ALT_B) +#define GPIO32_U2_RTSn PIN_CFG(32, ALT_C) + +#define GPIO33_GPIO PIN_CFG(33, GPIO) +#define GPIO33_MSP1_TXD PIN_CFG(33, ALT_A) +#define GPIO33_MSP1_RXD PIN_CFG(33, ALT_B) +#define GPIO33_U0_DTRn PIN_CFG(33, ALT_C) + +#define GPIO34_GPIO PIN_CFG(34, GPIO) +#define GPIO34_MSP1_TFS PIN_CFG(34, ALT_A) +#define GPIO34_NONE PIN_CFG(34, ALT_B) +#define GPIO34_U0_DCDn PIN_CFG(34, ALT_C) + +#define GPIO35_GPIO PIN_CFG(35, GPIO) +#define GPIO35_MSP1_TCK PIN_CFG(35, ALT_A) +#define GPIO35_NONE PIN_CFG(35, ALT_B) +#define GPIO35_U0_DSRn PIN_CFG(35, ALT_C) + +#define GPIO36_GPIO PIN_CFG(36, GPIO) +#define GPIO36_MSP1_RXD PIN_CFG(36, ALT_A) +#define GPIO36_MSP1_TXD PIN_CFG(36, ALT_B) +#define GPIO36_U0_RIn PIN_CFG(36, ALT_C) + +#define GPIO64_GPIO PIN_CFG(64, GPIO) +#define GPIO64_LCDB_DE PIN_CFG(64, ALT_A) +#define GPIO64_KP_O1 PIN_CFG(64, ALT_B) +#define GPIO64_IP_GPIO4 PIN_CFG(64, ALT_C) + +#define GPIO65_GPIO PIN_CFG(65, GPIO) +#define GPIO65_LCDB_HSO PIN_CFG(65, ALT_A) +#define GPIO65_KP_O0 PIN_CFG(65, ALT_B) +#define GPIO65_IP_GPIO5 PIN_CFG(65, ALT_C) + +#define GPIO66_GPIO PIN_CFG(66, GPIO) +#define GPIO66_LCDB_VSO PIN_CFG(66, ALT_A) +#define GPIO66_KP_I1 PIN_CFG(66, ALT_B) +#define GPIO66_IP_GPIO6 PIN_CFG(66, ALT_C) + +#define GPIO67_GPIO PIN_CFG(67, GPIO) +#define GPIO67_LCDB_CLK PIN_CFG(67, ALT_A) +#define GPIO67_KP_I0 PIN_CFG(67, ALT_B) +#define GPIO67_IP_GPIO7 PIN_CFG(67, ALT_C) + +#define GPIO68_GPIO PIN_CFG(68, GPIO) +#define GPIO68_LCD_VSI0 PIN_CFG(68, ALT_A) +#define GPIO68_KP_O7 PIN_CFG(68, ALT_B) +#define GPIO68_SM_CLE PIN_CFG(68, ALT_C) + +#define GPIO69_GPIO PIN_CFG(69, GPIO) +#define GPIO69_LCD_VSI1 PIN_CFG(69, ALT_A) +#define GPIO69_KP_I7 PIN_CFG(69, ALT_B) +#define GPIO69_SM_ALE PIN_CFG(69, ALT_C) + +#define GPIO70_GPIO PIN_CFG(70, GPIO) +#define GPIO70_LCD_D0 PIN_CFG(70, ALT_A) +#define GPIO70_KP_O5 PIN_CFG(70, ALT_B) +#define GPIO70_STMAPE_CLK PIN_CFG(70, ALT_C) + +#define GPIO71_GPIO PIN_CFG(71, GPIO) +#define GPIO71_LCD_D1 PIN_CFG(71, ALT_A) +#define GPIO71_KP_O4 PIN_CFG(71, ALT_B) +#define GPIO71_STMAPE_DAT3 PIN_CFG(71, ALT_C) + +#define GPIO72_GPIO PIN_CFG(72, GPIO) +#define GPIO72_LCD_D2 PIN_CFG(72, ALT_A) +#define GPIO72_KP_O3 PIN_CFG(72, ALT_B) +#define GPIO72_STMAPE_DAT2 PIN_CFG(72, ALT_C) + +#define GPIO73_GPIO PIN_CFG(73, GPIO) +#define GPIO73_LCD_D3 PIN_CFG(73, ALT_A) +#define GPIO73_KP_O2 PIN_CFG(73, ALT_B) +#define GPIO73_STMAPE_DAT1 PIN_CFG(73, ALT_C) + +#define GPIO74_GPIO PIN_CFG(74, GPIO) +#define GPIO74_LCD_D4 PIN_CFG(74, ALT_A) +#define GPIO74_KP_I5 PIN_CFG(74, ALT_B) +#define GPIO74_STMAPE_DAT0 PIN_CFG(74, ALT_C) + +#define GPIO75_GPIO PIN_CFG(75, GPIO) +#define GPIO75_LCD_D5 PIN_CFG(75, ALT_A) +#define GPIO75_KP_I4 PIN_CFG(75, ALT_B) +#define GPIO75_U2_RXD PIN_CFG(75, ALT_C) + +#define GPIO76_GPIO PIN_CFG(76, GPIO) +#define GPIO76_LCD_D6 PIN_CFG(76, ALT_A) +#define GPIO76_KP_I3 PIN_CFG(76, ALT_B) +#define GPIO76_U2_TXD PIN_CFG(76, ALT_C) + +#define GPIO77_GPIO PIN_CFG(77, GPIO) +#define GPIO77_LCD_D7 PIN_CFG(77, ALT_A) +#define GPIO77_KP_I2 PIN_CFG(77, ALT_B) +#define GPIO77_NONE PIN_CFG(77, ALT_C) + +#define GPIO78_GPIO PIN_CFG(78, GPIO) +#define GPIO78_LCD_D8 PIN_CFG(78, ALT_A) +#define GPIO78_KP_O6 PIN_CFG(78, ALT_B) +#define GPIO78_IP_GPIO2 PIN_CFG(78, ALT_C) + +#define GPIO79_GPIO PIN_CFG(79, GPIO) +#define GPIO79_LCD_D9 PIN_CFG(79, ALT_A) +#define GPIO79_KP_I6 PIN_CFG(79, ALT_B) +#define GPIO79_IP_GPIO3 PIN_CFG(79, ALT_C) + +#define GPIO80_GPIO PIN_CFG(80, GPIO) +#define GPIO80_LCD_D10 PIN_CFG(80, ALT_A) +#define GPIO80_KP_SKA0 PIN_CFG(80, ALT_B) +#define GPIO80_IP_GPIO4 PIN_CFG(80, ALT_C) + +#define GPIO81_GPIO PIN_CFG(81, GPIO) +#define GPIO81_LCD_D11 PIN_CFG(81, ALT_A) +#define GPIO81_KP_SKB0 PIN_CFG(81, ALT_B) +#define GPIO81_IP_GPIO5 PIN_CFG(81, ALT_C) + +#define GPIO82_GPIO PIN_CFG(82, GPIO) +#define GPIO82_LCD_D12 PIN_CFG(82, ALT_A) +#define GPIO82_KP_O5 PIN_CFG(82, ALT_B) + +#define GPIO83_GPIO PIN_CFG(83, GPIO) +#define GPIO83_LCD_D13 PIN_CFG(83, ALT_A) +#define GPIO83_KP_O4 PIN_CFG(83, ALT_B) + +#define GPIO84_GPIO PIN_CFG_PULL(84, GPIO, UP) +#define GPIO84_LCD_D14 PIN_CFG(84, ALT_A) +#define GPIO84_KP_I5 PIN_CFG(84, ALT_B) + +#define GPIO85_GPIO PIN_CFG(85, GPIO) +#define GPIO85_LCD_D15 PIN_CFG(85, ALT_A) +#define GPIO85_KP_I4 PIN_CFG(85, ALT_B) + +#define GPIO86_GPIO PIN_CFG(86, GPIO) +#define GPIO86_LCD_D16 PIN_CFG(86, ALT_A) +#define GPIO86_SM_ADQ0 PIN_CFG(86, ALT_B) +#define GPIO86_MC5_DAT0 PIN_CFG(86, ALT_C) + +#define GPIO87_GPIO PIN_CFG(87, GPIO) +#define GPIO87_LCD_D17 PIN_CFG(87, ALT_A) +#define GPIO87_SM_ADQ1 PIN_CFG(87, ALT_B) +#define GPIO87_MC5_DAT1 PIN_CFG(87, ALT_C) + +#define GPIO88_GPIO PIN_CFG(88, GPIO) +#define GPIO88_LCD_D18 PIN_CFG(88, ALT_A) +#define GPIO88_SM_ADQ2 PIN_CFG(88, ALT_B) +#define GPIO88_MC5_DAT2 PIN_CFG(88, ALT_C) + +#define GPIO89_GPIO PIN_CFG(89, GPIO) +#define GPIO89_LCD_D19 PIN_CFG(89, ALT_A) +#define GPIO89_SM_ADQ3 PIN_CFG(89, ALT_B) +#define GPIO89_MC5_DAT3 PIN_CFG(89, ALT_C) + +#define GPIO90_GPIO PIN_CFG(90, GPIO) +#define GPIO90_LCD_D20 PIN_CFG(90, ALT_A) +#define GPIO90_SM_ADQ4 PIN_CFG(90, ALT_B) +#define GPIO90_MC5_CMD PIN_CFG(90, ALT_C) + +#define GPIO91_GPIO PIN_CFG(91, GPIO) +#define GPIO91_LCD_D21 PIN_CFG(91, ALT_A) +#define GPIO91_SM_ADQ5 PIN_CFG(91, ALT_B) +#define GPIO91_MC5_FBCLK PIN_CFG(91, ALT_C) + +#define GPIO92_GPIO PIN_CFG(92, GPIO) +#define GPIO92_LCD_D22 PIN_CFG(92, ALT_A) +#define GPIO92_SM_ADQ6 PIN_CFG(92, ALT_B) +#define GPIO92_MC5_CLK PIN_CFG(92, ALT_C) + +#define GPIO93_GPIO PIN_CFG(93, GPIO) +#define GPIO93_LCD_D23 PIN_CFG(93, ALT_A) +#define GPIO93_SM_ADQ7 PIN_CFG(93, ALT_B) +#define GPIO93_MC5_DAT4 PIN_CFG(93, ALT_C) + +#define GPIO94_GPIO PIN_CFG(94, GPIO) +#define GPIO94_KP_O7 PIN_CFG(94, ALT_A) +#define GPIO94_SM_ADVn PIN_CFG(94, ALT_B) +#define GPIO94_MC5_DAT5 PIN_CFG(94, ALT_C) + +#define GPIO95_GPIO PIN_CFG(95, GPIO) +#define GPIO95_KP_I7 PIN_CFG(95, ALT_A) +#define GPIO95_SM_CS0n PIN_CFG(95, ALT_B) +#define GPIO95_SM_PS0n PIN_CFG(95, ALT_C) + +#define GPIO96_GPIO PIN_CFG(96, GPIO) +#define GPIO96_KP_O6 PIN_CFG(96, ALT_A) +#define GPIO96_SM_OEn PIN_CFG(96, ALT_B) +#define GPIO96_MC5_DAT6 PIN_CFG(96, ALT_C) + +#define GPIO97_GPIO PIN_CFG(97, GPIO) +#define GPIO97_KP_I6 PIN_CFG(97, ALT_A) +#define GPIO97_SM_WEn PIN_CFG(97, ALT_B) +#define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C) + +#define GPIO128_GPIO PIN_CFG(128, GPIO) +#define GPIO128_MC2_CLK PIN_CFG(128, ALT_A) +#define GPIO128_SM_CKO PIN_CFG(128, ALT_B) + +#define GPIO129_GPIO PIN_CFG(129, GPIO) +#define GPIO129_MC2_CMD PIN_CFG(129, ALT_A) +#define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B) + +#define GPIO130_GPIO PIN_CFG(130, GPIO) +#define GPIO130_MC2_FBCLK PIN_CFG(130, ALT_A) +#define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B) +#define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C) + +#define GPIO131_GPIO PIN_CFG(131, GPIO) +#define GPIO131_MC2_DAT0 PIN_CFG(131, ALT_A) +#define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B) + +#define GPIO132_GPIO PIN_CFG(132, GPIO) +#define GPIO132_MC2_DAT1 PIN_CFG(132, ALT_A) +#define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B) + +#define GPIO133_GPIO PIN_CFG(133, GPIO) +#define GPIO133_MC2_DAT2 PIN_CFG(133, ALT_A) +#define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B) + +#define GPIO134_GPIO PIN_CFG(134, GPIO) +#define GPIO134_MC2_DAT3 PIN_CFG(134, ALT_A) +#define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B) + +#define GPIO135_GPIO PIN_CFG(135, GPIO) +#define GPIO135_MC2_DAT4 PIN_CFG(135, ALT_A) +#define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B) + +#define GPIO136_GPIO PIN_CFG(136, GPIO) +#define GPIO136_MC2_DAT5 PIN_CFG(136, ALT_A) +#define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B) + +#define GPIO137_GPIO PIN_CFG(137, GPIO) +#define GPIO137_MC2_DAT6 PIN_CFG(137, ALT_A) +#define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B) + +#define GPIO138_GPIO PIN_CFG(138, GPIO) +#define GPIO138_MC2_DAT7 PIN_CFG(138, ALT_A) +#define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B) + +#define GPIO139_GPIO PIN_CFG(139, GPIO) +#define GPIO139_SSP1_RXD PIN_CFG(139, ALT_A) +#define GPIO139_SM_WAIT1n PIN_CFG(139, ALT_B) +#define GPIO139_KP_O8 PIN_CFG(139, ALT_C) + +#define GPIO140_GPIO PIN_CFG(140, GPIO) +#define GPIO140_SSP1_TXD PIN_CFG(140, ALT_A) +#define GPIO140_IP_GPIO7 PIN_CFG(140, ALT_B) +#define GPIO140_KP_SKA1 PIN_CFG(140, ALT_C) + +#define GPIO141_GPIO PIN_CFG(141, GPIO) +#define GPIO141_SSP1_CLK PIN_CFG(141, ALT_A) +#define GPIO141_IP_GPIO2 PIN_CFG(141, ALT_B) +#define GPIO141_KP_O9 PIN_CFG(141, ALT_C) + +#define GPIO142_GPIO PIN_CFG(142, GPIO) +#define GPIO142_SSP1_FRM PIN_CFG(142, ALT_A) +#define GPIO142_IP_GPIO3 PIN_CFG(142, ALT_B) +#define GPIO142_KP_SKB1 PIN_CFG(142, ALT_C) + +#define GPIO143_GPIO PIN_CFG(143, GPIO) +#define GPIO143_SSP0_CLK PIN_CFG(143, ALT_A) + +#define GPIO144_GPIO PIN_CFG(144, GPIO) +#define GPIO144_SSP0_FRM PIN_CFG(144, ALT_A) + +#define GPIO145_GPIO PIN_CFG(145, GPIO) +#define GPIO145_SSP0_RXD PIN_CFG(145, ALT_A) + +#define GPIO146_GPIO PIN_CFG(146, GPIO) +#define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A) + +#define GPIO147_GPIO PIN_CFG(147, GPIO) +#define GPIO147_I2C0_SCL PIN_CFG_PULL(147, ALT_A, UP) + +#define GPIO148_GPIO PIN_CFG(148, GPIO) +#define GPIO148_I2C0_SDA PIN_CFG_PULL(148, ALT_A, UP) + +#define GPIO149_GPIO PIN_CFG(149, GPIO) +#define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A) +#define GPIO149_SM_CS1n PIN_CFG(149, ALT_B) +#define GPIO149_SM_PS1n PIN_CFG(149, ALT_C) + +#define GPIO150_GPIO PIN_CFG(150, GPIO) +#define GPIO150_IP_GPIO1 PIN_CFG(150, ALT_A) +#define GPIO150_LCDA_CLK PIN_CFG(150, ALT_B) + +#define GPIO151_GPIO PIN_CFG(151, GPIO) +#define GPIO151_KP_SKA0 PIN_CFG(151, ALT_A) +#define GPIO151_LCD_VSI0 PIN_CFG(151, ALT_B) +#define GPIO151_KP_O8 PIN_CFG(151, ALT_C) + +#define GPIO152_GPIO PIN_CFG(152, GPIO) +#define GPIO152_KP_SKB0 PIN_CFG(152, ALT_A) +#define GPIO152_LCD_VSI1 PIN_CFG(152, ALT_B) +#define GPIO152_KP_O9 PIN_CFG(152, ALT_C) + +#define GPIO153_GPIO PIN_CFG(153, GPIO) +#define GPIO153_KP_I7 PIN_CFG_PULL(153, ALT_A, DOWN) +#define GPIO153_LCD_D24 PIN_CFG(153, ALT_B) +#define GPIO153_U2_RXD PIN_CFG(153, ALT_C) + +#define GPIO154_GPIO PIN_CFG(154, GPIO) +#define GPIO154_KP_I6 PIN_CFG_PULL(154, ALT_A, DOWN) +#define GPIO154_LCD_D25 PIN_CFG(154, ALT_B) +#define GPIO154_U2_TXD PIN_CFG(154, ALT_C) + +#define GPIO155_GPIO PIN_CFG(155, GPIO) +#define GPIO155_KP_I5 PIN_CFG_PULL(155, ALT_A, DOWN) +#define GPIO155_LCD_D26 PIN_CFG(155, ALT_B) +#define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C) + +#define GPIO156_GPIO PIN_CFG(156, GPIO) +#define GPIO156_KP_I4 PIN_CFG_PULL(156, ALT_A, DOWN) +#define GPIO156_LCD_D27 PIN_CFG(156, ALT_B) +#define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C) + +#define GPIO157_GPIO PIN_CFG(157, GPIO) +#define GPIO157_KP_O7 PIN_CFG_PULL(157, ALT_A, UP) +#define GPIO157_LCD_D28 PIN_CFG(157, ALT_B) +#define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C) + +#define GPIO158_GPIO PIN_CFG(158, GPIO) +#define GPIO158_KP_O6 PIN_CFG_PULL(158, ALT_A, UP) +#define GPIO158_LCD_D29 PIN_CFG(158, ALT_B) +#define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C) + +#define GPIO159_GPIO PIN_CFG(159, GPIO) +#define GPIO159_KP_O5 PIN_CFG_PULL(159, ALT_A, UP) +#define GPIO159_LCD_D30 PIN_CFG(159, ALT_B) +#define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C) + +#define GPIO160_GPIO PIN_CFG(160, GPIO) +#define GPIO160_KP_O4 PIN_CFG_PULL(160, ALT_A, UP) +#define GPIO160_LCD_D31 PIN_CFG(160, ALT_B) +#define GPIO160_NONE PIN_CFG(160, ALT_C) + +#define GPIO161_GPIO PIN_CFG(161, GPIO) +#define GPIO161_KP_I3 PIN_CFG_PULL(161, ALT_A, DOWN) +#define GPIO161_LCD_D32 PIN_CFG(161, ALT_B) +#define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C) + +#define GPIO162_GPIO PIN_CFG(162, GPIO) +#define GPIO162_KP_I2 PIN_CFG_PULL(162, ALT_A, DOWN) +#define GPIO162_LCD_D33 PIN_CFG(162, ALT_B) +#define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C) + +#define GPIO163_GPIO PIN_CFG(163, GPIO) +#define GPIO163_KP_I1 PIN_CFG_PULL(163, ALT_A, DOWN) +#define GPIO163_LCD_D34 PIN_CFG(163, ALT_B) +#define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C) + +#define GPIO164_GPIO PIN_CFG(164, GPIO) +#define GPIO164_KP_I0 PIN_CFG_PULL(164, ALT_A, UP) +#define GPIO164_LCD_D35 PIN_CFG(164, ALT_B) +#define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C) + +#define GPIO165_GPIO PIN_CFG(165, GPIO) +#define GPIO165_KP_O3 PIN_CFG_PULL(165, ALT_A, UP) +#define GPIO165_LCD_D36 PIN_CFG(165, ALT_B) +#define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C) + +#define GPIO166_GPIO PIN_CFG(166, GPIO) +#define GPIO166_KP_O2 PIN_CFG_PULL(166, ALT_A, UP) +#define GPIO166_LCD_D37 PIN_CFG(166, ALT_B) +#define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C) + +#define GPIO167_GPIO PIN_CFG(167, GPIO) +#define GPIO167_KP_O1 PIN_CFG_PULL(167, ALT_A, UP) +#define GPIO167_LCD_D38 PIN_CFG(167, ALT_B) +#define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C) + +#define GPIO168_GPIO PIN_CFG(168, GPIO) +#define GPIO168_KP_O0 PIN_CFG_PULL(168, ALT_A, UP) +#define GPIO168_LCD_D39 PIN_CFG(168, ALT_B) +#define GPIO168_NONE PIN_CFG(168, ALT_C) + +#define GPIO169_GPIO PIN_CFG(169, GPIO) +#define GPIO169_RF_PURn PIN_CFG(169, ALT_A) +#define GPIO169_LCDA_DE PIN_CFG(169, ALT_B) +#define GPIO169_USBSIM_PDC PIN_CFG(169, ALT_C) + +#define GPIO170_GPIO PIN_CFG(170, GPIO) +#define GPIO170_MODEM_STATE PIN_CFG(170, ALT_A) +#define GPIO170_LCDA_VSO PIN_CFG(170, ALT_B) +#define GPIO170_KP_SKA1 PIN_CFG(170, ALT_C) + +#define GPIO171_GPIO PIN_CFG(171, GPIO) +#define GPIO171_MODEM_PWREN PIN_CFG(171, ALT_A) +#define GPIO171_LCDA_HSO PIN_CFG(171, ALT_B) +#define GPIO171_KP_SKB1 PIN_CFG(171, ALT_C) + +#define GPIO192_GPIO PIN_CFG(192, GPIO) +#define GPIO192_MSP2_SCK PIN_CFG(192, ALT_A) + +#define GPIO193_GPIO PIN_CFG(193, GPIO) +#define GPIO193_MSP2_TXD PIN_CFG(193, ALT_A) + +#define GPIO194_GPIO PIN_CFG(194, GPIO) +#define GPIO194_MSP2_TCK PIN_CFG(194, ALT_A) + +#define GPIO195_GPIO PIN_CFG(195, GPIO) +#define GPIO195_MSP2_TFS PIN_CFG(195, ALT_A) + +#define GPIO196_GPIO PIN_CFG(196, GPIO) +#define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A) + +#define GPIO197_GPIO PIN_CFG(197, GPIO) +#define GPIO197_MC4_DAT3 PIN_CFG(197, ALT_A) + +#define GPIO198_GPIO PIN_CFG(198, GPIO) +#define GPIO198_MC4_DAT2 PIN_CFG(198, ALT_A) + +#define GPIO199_GPIO PIN_CFG(199, GPIO) +#define GPIO199_MC4_DAT1 PIN_CFG(199, ALT_A) + +#define GPIO200_GPIO PIN_CFG(200, GPIO) +#define GPIO200_MC4_DAT0 PIN_CFG(200, ALT_A) + +#define GPIO201_GPIO PIN_CFG(201, GPIO) +#define GPIO201_MC4_CMD PIN_CFG(201, ALT_A) + +#define GPIO202_GPIO PIN_CFG(202, GPIO) +#define GPIO202_MC4_FBCLK PIN_CFG(202, ALT_A) +#define GPIO202_PWL PIN_CFG(202, ALT_B) +#define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C) + +#define GPIO203_GPIO PIN_CFG(203, GPIO) +#define GPIO203_MC4_CLK PIN_CFG(203, ALT_A) + +#define GPIO204_GPIO PIN_CFG(204, GPIO) +#define GPIO204_MC4_DAT7 PIN_CFG(204, ALT_A) + +#define GPIO205_GPIO PIN_CFG(205, GPIO) +#define GPIO205_MC4_DAT6 PIN_CFG(205, ALT_A) + +#define GPIO206_GPIO PIN_CFG(206, GPIO) +#define GPIO206_MC4_DAT5 PIN_CFG(206, ALT_A) + +#define GPIO207_GPIO PIN_CFG(207, GPIO) +#define GPIO207_MC4_DAT4 PIN_CFG(207, ALT_A) + +#define GPIO208_GPIO PIN_CFG(208, GPIO) +#define GPIO208_MC1_CLK PIN_CFG(208, ALT_A) + +#define GPIO209_GPIO PIN_CFG(209, GPIO) +#define GPIO209_MC1_FBCLK PIN_CFG(209, ALT_A) +#define GPIO209_SPI1_CLK PIN_CFG(209, ALT_B) + +#define GPIO210_GPIO PIN_CFG(210, GPIO) +#define GPIO210_MC1_CMD PIN_CFG(210, ALT_A) + +#define GPIO211_GPIO PIN_CFG(211, GPIO) +#define GPIO211_MC1_DAT0 PIN_CFG(211, ALT_A) + +#define GPIO212_GPIO PIN_CFG(212, GPIO) +#define GPIO212_MC1_DAT1 PIN_CFG(212, ALT_A) +#define GPIO212_SPI1_FRM PIN_CFG(212, ALT_B) + +#define GPIO213_GPIO PIN_CFG(213, GPIO) +#define GPIO213_MC1_DAT2 PIN_CFG(213, ALT_A) +#define GPIO213_SPI1_TXD PIN_CFG(213, ALT_B) + +#define GPIO214_GPIO PIN_CFG(214, GPIO) +#define GPIO214_MC1_DAT3 PIN_CFG(214, ALT_A) +#define GPIO214_SPI1_RXD PIN_CFG(214, ALT_B) + +#define GPIO215_GPIO PIN_CFG(215, GPIO) +#define GPIO215_MC1_CMDDIR PIN_CFG(215, ALT_A) +#define GPIO215_MC3_DAT2DIR PIN_CFG(215, ALT_B) +#define GPIO215_CLKOUT1 PIN_CFG(215, ALT_C) + +#define GPIO216_GPIO PIN_CFG(216, GPIO) +#define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A) +#define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B) +#define GPIO216_I2C3_SDA PIN_CFG_PULL(216, ALT_C, UP) + +#define GPIO217_GPIO PIN_CFG(217, GPIO) +#define GPIO217_MC1_DAT0DIR PIN_CFG(217, ALT_A) +#define GPIO217_MC3_DAT31DIR PIN_CFG(217, ALT_B) +#define GPIO217_CLKOUT2 PIN_CFG(217, ALT_C) + +#define GPIO218_GPIO PIN_CFG(218, GPIO) +#define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A) +#define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B) +#define GPIO218_I2C3_SCL PIN_CFG_PULL(218, ALT_C, UP) + +#define GPIO219_GPIO PIN_CFG(219, GPIO) +#define GPIO219_HSIR_FLA0 PIN_CFG(219, ALT_A) +#define GPIO219_MC3_CLK PIN_CFG(219, ALT_B) + +#define GPIO220_GPIO PIN_CFG(220, GPIO) +#define GPIO220_HSIR_DAT0 PIN_CFG(220, ALT_A) +#define GPIO220_MC3_FBCLK PIN_CFG(220, ALT_B) +#define GPIO220_SPI0_CLK PIN_CFG(220, ALT_C) + +#define GPIO221_GPIO PIN_CFG(221, GPIO) +#define GPIO221_HSIR_RDY0 PIN_CFG(221, ALT_A) +#define GPIO221_MC3_CMD PIN_CFG(221, ALT_B) + +#define GPIO222_GPIO PIN_CFG(222, GPIO) +#define GPIO222_HSIT_FLA0 PIN_CFG(222, ALT_A) +#define GPIO222_MC3_DAT0 PIN_CFG(222, ALT_B) + +#define GPIO223_GPIO PIN_CFG(223, GPIO) +#define GPIO223_HSIT_DAT0 PIN_CFG(223, ALT_A) +#define GPIO223_MC3_DAT1 PIN_CFG(223, ALT_B) +#define GPIO223_SPI0_FRM PIN_CFG(223, ALT_C) + +#define GPIO224_GPIO PIN_CFG(224, GPIO) +#define GPIO224_HSIT_RDY0 PIN_CFG(224, ALT_A) +#define GPIO224_MC3_DAT2 PIN_CFG(224, ALT_B) +#define GPIO224_SPI0_TXD PIN_CFG(224, ALT_C) + +#define GPIO225_GPIO PIN_CFG(225, GPIO) +#define GPIO225_HSIT_CAWAKE0 PIN_CFG(225, ALT_A) +#define GPIO225_MC3_DAT3 PIN_CFG(225, ALT_B) +#define GPIO225_SPI0_RXD PIN_CFG(225, ALT_C) + +#define GPIO226_GPIO PIN_CFG(226, GPIO) +#define GPIO226_HSIT_ACWAKE0 PIN_CFG(226, ALT_A) +#define GPIO226_PWL PIN_CFG(226, ALT_B) +#define GPIO226_USBSIM_PDC PIN_CFG(226, ALT_C) + +#define GPIO227_GPIO PIN_CFG(227, GPIO) +#define GPIO227_CLKOUT1 PIN_CFG(227, ALT_A) + +#define GPIO228_GPIO PIN_CFG(228, GPIO) +#define GPIO228_CLKOUT2 PIN_CFG(228, ALT_A) + +#define GPIO229_GPIO PIN_CFG(229, GPIO) +#define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A) +#define GPIO229_PWL PIN_CFG(229, ALT_B) +#define GPIO229_I2C3_SDA PIN_CFG_PULL(229, ALT_C, UP) + +#define GPIO230_GPIO PIN_CFG(230, GPIO) +#define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A) +#define GPIO230_PWL PIN_CFG(230, ALT_B) +#define GPIO230_I2C3_SCL PIN_CFG_PULL(230, ALT_C, UP) + +#define GPIO256_GPIO PIN_CFG(256, GPIO) +#define GPIO256_USB_NXT PIN_CFG(256, ALT_A) + +#define GPIO257_GPIO PIN_CFG(257, GPIO) +#define GPIO257_USB_STP PIN_CFG(257, ALT_A) + +#define GPIO258_GPIO PIN_CFG(258, GPIO) +#define GPIO258_USB_XCLK PIN_CFG(258, ALT_A) +#define GPIO258_NONE PIN_CFG(258, ALT_B) +#define GPIO258_DDR_TRIG PIN_CFG(258, ALT_C) + +#define GPIO259_GPIO PIN_CFG(259, GPIO) +#define GPIO259_USB_DIR PIN_CFG(259, ALT_A) + +#define GPIO260_GPIO PIN_CFG(260, GPIO) +#define GPIO260_USB_DAT7 PIN_CFG(260, ALT_A) + +#define GPIO261_GPIO PIN_CFG(261, GPIO) +#define GPIO261_USB_DAT6 PIN_CFG(261, ALT_A) + +#define GPIO262_GPIO PIN_CFG(262, GPIO) +#define GPIO262_USB_DAT5 PIN_CFG(262, ALT_A) + +#define GPIO263_GPIO PIN_CFG(263, GPIO) +#define GPIO263_USB_DAT4 PIN_CFG(263, ALT_A) + +#define GPIO264_GPIO PIN_CFG(264, GPIO) +#define GPIO264_USB_DAT3 PIN_CFG(264, ALT_A) + +#define GPIO265_GPIO PIN_CFG(265, GPIO) +#define GPIO265_USB_DAT2 PIN_CFG(265, ALT_A) + +#define GPIO266_GPIO PIN_CFG(266, GPIO) +#define GPIO266_USB_DAT1 PIN_CFG(266, ALT_A) + +#define GPIO267_GPIO PIN_CFG(267, GPIO) +#define GPIO267_USB_DAT0 PIN_CFG(267, ALT_A) + +#endif diff --git a/board/st-ericsson/snowball/snowball.c b/board/st-ericsson/snowball/snowball.c new file mode 100644 index 0000000..a70ebb1 --- /dev/null +++ b/board/st-ericsson/snowball/snowball.c @@ -0,0 +1,185 @@ +/* + * Copyright (C) ST-Ericsson SA 2009 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <malloc.h> +#include <i2c.h> +#include <mmc.h> +#include <asm/types.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/db8500_pincfg.h> + +#include "db8500_pins.h" + +/* + * Get a global data pointer + */ +DECLARE_GLOBAL_DATA_PTR; + +/* + * Memory controller register + */ +#define DMC_BASE_ADDR 0x80156000 +#define DMC_CTL_97 (DMC_BASE_ADDR + 0x184) + +/* + * GPIO pin config common for MOP500/HREF boards + */ +unsigned long gpio_cfg_common[] = { + /* I2C */ + GPIO147_I2C0_SCL, + GPIO148_I2C0_SDA, + GPIO16_I2C1_SCL, + GPIO17_I2C1_SDA, + GPIO10_I2C2_SDA, + GPIO11_I2C2_SCL, + GPIO229_I2C3_SDA, + GPIO230_I2C3_SCL, + + /* SSP0, to AB8500 */ + GPIO143_SSP0_CLK, + GPIO144_SSP0_FRM, + GPIO145_SSP0_RXD | PIN_PULL_DOWN, + GPIO146_SSP0_TXD, + + /* MMC0 (MicroSD card) */ + GPIO18_MC0_CMDDIR | PIN_OUTPUT_HIGH, + GPIO19_MC0_DAT0DIR | PIN_OUTPUT_HIGH, + GPIO20_MC0_DAT2DIR | PIN_OUTPUT_HIGH, + GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH, + GPIO22_MC0_FBCLK | PIN_INPUT_NOPULL, + GPIO23_MC0_CLK | PIN_OUTPUT_LOW, + GPIO24_MC0_CMD | PIN_INPUT_PULLUP, + GPIO25_MC0_DAT0 | PIN_INPUT_PULLUP, + GPIO26_MC0_DAT1 | PIN_INPUT_PULLUP, + GPIO27_MC0_DAT2 | PIN_INPUT_PULLUP, + GPIO28_MC0_DAT3 | PIN_INPUT_PULLUP, + + /* MMC4 (On-board eMMC) */ + GPIO197_MC4_DAT3 | PIN_INPUT_PULLUP, + GPIO198_MC4_DAT2 | PIN_INPUT_PULLUP, + GPIO199_MC4_DAT1 | PIN_INPUT_PULLUP, + GPIO200_MC4_DAT0 | PIN_INPUT_PULLUP, + GPIO201_MC4_CMD | PIN_INPUT_PULLUP, + GPIO202_MC4_FBCLK | PIN_INPUT_NOPULL, + GPIO203_MC4_CLK | PIN_OUTPUT_LOW, + GPIO204_MC4_DAT7 | PIN_INPUT_PULLUP, + GPIO205_MC4_DAT6 | PIN_INPUT_PULLUP, + GPIO206_MC4_DAT5 | PIN_INPUT_PULLUP, + GPIO207_MC4_DAT4 | PIN_INPUT_PULLUP, + + /* UART2, console */ + GPIO29_U2_RXD | PIN_INPUT_PULLUP, + GPIO30_U2_TXD | PIN_OUTPUT_HIGH, + GPIO31_U2_CTSn | PIN_INPUT_PULLUP, + GPIO32_U2_RTSn | PIN_OUTPUT_HIGH, + + /* + * USB, pin 256-267 USB, Is probably already setup correctly from + * BootROM/boot stages, but we don't trust that and set it up anyway + */ + GPIO256_USB_NXT, + GPIO257_USB_STP, + GPIO258_USB_XCLK, + GPIO259_USB_DIR, + GPIO260_USB_DAT7, + GPIO261_USB_DAT6, + GPIO262_USB_DAT5, + GPIO263_USB_DAT4, + GPIO264_USB_DAT3, + GPIO265_USB_DAT2, + GPIO266_USB_DAT1, + GPIO267_USB_DAT0, +}; + +unsigned long gpio_cfg_snowball[] = { + /* MMC0 (MicroSD card) */ + GPIO217_GPIO | PIN_OUTPUT_HIGH, /* MMC_EN */ + GPIO218_GPIO | PIN_INPUT_NOPULL, /* MMC_CD */ + GPIO228_GPIO | PIN_OUTPUT_HIGH, /* SD_SEL */ + + /* eMMC */ + GPIO167_GPIO | PIN_OUTPUT_HIGH, /* RSTn_MLC */ + + /* LAN */ + GPIO131_SM_ADQ8, + GPIO132_SM_ADQ9, + GPIO133_SM_ADQ10, + GPIO134_SM_ADQ11, + GPIO135_SM_ADQ12, + GPIO136_SM_ADQ13, + GPIO137_SM_ADQ14, + GPIO138_SM_ADQ15, + + /* RSTn_LAN */ + GPIO141_GPIO | PIN_OUTPUT_HIGH, +}; + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init(void) +{ + /* + * Setup board (bd) and board-info (bi). + * bi_arch_number: Unique id for this board. It will passed in r1 to + * Linux startup code and is the machine_id. + * bi_boot_params: Where this board expects params. + */ + gd->bd->bi_arch_number = MACH_TYPE_SNOWBALL; + gd->bd->bi_boot_params = 0x00000100; + + /* Configure GPIO pins needed by U-boot */ + db8500_gpio_config_pins(gpio_cfg_common, ARRAY_SIZE(gpio_cfg_common)); + + db8500_gpio_config_pins(gpio_cfg_snowball, + ARRAY_SIZE(gpio_cfg_snowball)); + + return 0; +} + +int dram_init(void) +{ + uint32_t unused_cols_rows; + unsigned int nrows; + unsigned int ncols; + + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->ram_size = PHYS_SDRAM_SIZE_1; + + /* + * Assumption: 2 CS active, both CS have same layout. + * 15 rows max, 11 cols max (controller spec). + * memory chip has 8 banks, I/O width 32 bit. + * The correct way would be to read MR#8: I/O width and density, + * but this requires locking against the PRCMU firmware. + * Simplified approach: + * Read number of unused rows and columns from mem controller. + * size = nCS x 2^(rows+cols) x nbanks x buswidth_bytes + */ + unused_cols_rows = readl(DMC_CTL_97); + nrows = 15 - (unused_cols_rows & 0x07); + ncols = 11 - ((unused_cols_rows & 0x0700) >> 8); + gd->ram_size = gd->bd->bi_dram[0].size = + 2 * (1 << (nrows + ncols)) * 8 * 4; + + return 0; +} diff --git a/boards.cfg b/boards.cfg index 2d36d83..ba3e30c 100644 --- a/boards.cfg +++ b/boards.cfg @@ -256,6 +256,7 @@ seaboard arm armv7 seaboard nvidia ventana arm armv7 ventana nvidia tegra2 whistler arm armv7 whistler nvidia tegra2 u8500_href arm armv7 u8500 st-ericsson u8500 +snowball arm armv7 snowball st-ericsson u8500 actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 32a2474..1a7412f 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -40,6 +40,7 @@ COBJS-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o +COBJS-$(CONFIG_DB8500_GPIO) += db8500_gpio.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/gpio/db8500_gpio.c b/drivers/gpio/db8500_gpio.c new file mode 100644 index 0000000..5a2fa12 --- /dev/null +++ b/drivers/gpio/db8500_gpio.c @@ -0,0 +1,225 @@ +/* + * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. + * The purpose is that GPIO config found in kernel should work by simply + * copy-paste it to U-boot. + * + * Original Linux authors: + * Copyright (C) 2008,2009 STMicroelectronics + * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> + * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> + * + * Ported to U-boot by: + * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <common.h> +#include <asm/io.h> + +#include <asm/arch/db8500_gpio.h> +#include <asm/arch/db8500_pincfg.h> + +/* + * Macros to work with IO space + * Not actually used? + */ +#define __iomem +#define IO_ADDR(x) (void *) (x) + +/* + * The GPIO module in the db8500 Systems-on-Chip is an + * AMBA device, managing 32 pins and alternate functions. The logic block + * is currently only used in the db8500. + */ + +#define GPIO_TOTAL_PINS 268 +#define GPIO_PINS_PER_BLOCK 32 +#define GPIO_BLOCKS_COUNT (GPIO_TOTAL_PINS/GPIO_PINS_PER_BLOCK + 1) +#define GPIO_BLOCK(pin) (((pin + GPIO_PINS_PER_BLOCK) >> 5) - 1) +#define GPIO_PIN_WITHIN_BLOCK(pin) ((pin)%(GPIO_PINS_PER_BLOCK)) + +/* Register in the logic block */ +#define DB8500_GPIO_DAT 0x00 +#define DB8500_GPIO_DATS 0x04 +#define DB8500_GPIO_DATC 0x08 +#define DB8500_GPIO_PDIS 0x0c +#define DB8500_GPIO_DIR 0x10 +#define DB8500_GPIO_DIRS 0x14 +#define DB8500_GPIO_DIRC 0x18 +#define DB8500_GPIO_SLPC 0x1c +#define DB8500_GPIO_AFSLA 0x20 +#define DB8500_GPIO_AFSLB 0x24 + +#define DB8500_GPIO_RIMSC 0x40 +#define DB8500_GPIO_FIMSC 0x44 +#define DB8500_GPIO_IS 0x48 +#define DB8500_GPIO_IC 0x4c +#define DB8500_GPIO_RWIMSC 0x50 +#define DB8500_GPIO_FWIMSC 0x54 +#define DB8500_GPIO_WKS 0x58 + +static void __iomem *get_gpio_addr(unsigned gpio) +{ + /* Our list of GPIO chips */ + static void __iomem *gpio_addrs[GPIO_BLOCKS_COUNT] = { + IO_ADDR(CFG_GPIO_0_BASE), + IO_ADDR(CFG_GPIO_1_BASE), + IO_ADDR(CFG_GPIO_2_BASE), + IO_ADDR(CFG_GPIO_3_BASE), + IO_ADDR(CFG_GPIO_4_BASE), + IO_ADDR(CFG_GPIO_5_BASE), + IO_ADDR(CFG_GPIO_6_BASE), + IO_ADDR(CFG_GPIO_7_BASE), + IO_ADDR(CFG_GPIO_8_BASE) + }; + + return gpio_addrs[GPIO_BLOCK(gpio)]; +} + +static unsigned get_gpio_offset(unsigned gpio) +{ + return GPIO_PIN_WITHIN_BLOCK(gpio); +} + +/* Can only be called from config_pin. Don't configure alt-mode directly */ +static void gpio_set_mode(unsigned gpio, enum db8500_gpio_alt mode) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + u32 bit = 1 << offset; + u32 afunc, bfunc; + + afunc = readl(addr + DB8500_GPIO_AFSLA) & ~bit; + bfunc = readl(addr + DB8500_GPIO_AFSLB) & ~bit; + if (mode & DB8500_GPIO_ALT_A) + afunc |= bit; + if (mode & DB8500_GPIO_ALT_B) + bfunc |= bit; + writel(afunc, addr + DB8500_GPIO_AFSLA); + writel(bfunc, addr + DB8500_GPIO_AFSLB); +} + +/** + * db8500_gpio_set_pull() - enable/disable pull up/down on a gpio + * @gpio: pin number + * @pull: one of DB8500_GPIO_PULL_DOWN, DB8500_GPIO_PULL_UP, + * and DB8500_GPIO_PULL_NONE + * + * Enables/disables pull up/down on a specified pin. This only takes effect if + * the pin is configured as an input (either explicitly or by the alternate + * function). + * + * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is + * configured as an input. Otherwise, due to the way the controller registers + * work, this function will change the value output on the pin. + */ +void db8500_gpio_set_pull(unsigned gpio, enum db8500_gpio_pull pull) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + u32 bit = 1 << offset; + u32 pdis; + + pdis = readl(addr + DB8500_GPIO_PDIS); + if (pull == DB8500_GPIO_PULL_NONE) + pdis |= bit; + else + pdis &= ~bit; + writel(pdis, addr + DB8500_GPIO_PDIS); + + if (pull == DB8500_GPIO_PULL_UP) + writel(bit, addr + DB8500_GPIO_DATS); + else if (pull == DB8500_GPIO_PULL_DOWN) + writel(bit, addr + DB8500_GPIO_DATC); +} + +void db8500_gpio_make_input(unsigned gpio) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + + writel(1 << offset, addr + DB8500_GPIO_DIRC); +} + +int db8500_gpio_get_input(unsigned gpio) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + u32 bit = 1 << offset; + + printf("db8500_gpio_get_input gpio=%u addr=%p offset=%u bit=%#x\n", + gpio, addr, offset, bit); + + return (readl(addr + DB8500_GPIO_DAT) & bit) != 0; +} + +void db8500_gpio_make_output(unsigned gpio, int val) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + + writel(1 << offset, addr + DB8500_GPIO_DIRS); + db8500_gpio_set_output(gpio, val); +} + +void db8500_gpio_set_output(unsigned gpio, int val) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + + if (val) + writel(1 << offset, addr + DB8500_GPIO_DATS); + else + writel(1 << offset, addr + DB8500_GPIO_DATC); +} + +/** + * config_pin - configure a pin's mux attributes + * @cfg: pin confguration + * + * Configures a pin's mode (alternate function or GPIO), its pull up status, + * and its sleep mode based on the specified configuration. The @cfg is + * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These + * are constructed using, and can be further enhanced with, the macros in + * plat/pincfg.h. + * + * If a pin's mode is set to GPIO, it is configured as an input to avoid + * side-effects. The gpio can be manipulated later using standard GPIO API + * calls. + */ +static void config_pin(unsigned long cfg) +{ + int pin = PIN_NUM(cfg); + int pull = PIN_PULL(cfg); + int af = PIN_ALT(cfg); + int output = PIN_DIR(cfg); + int val = PIN_VAL(cfg); + + if (output) + db8500_gpio_make_output(pin, val); + else { + db8500_gpio_make_input(pin); + db8500_gpio_set_pull(pin, pull); + } + + gpio_set_mode(pin, af); +} + +/** + * db8500_config_pins - configure several pins at once + * @cfgs: array of pin configurations + * @num: number of elments in the array + * + * Configures several pins using config_pin(). Refer to that function for + * further information. + */ +void db8500_gpio_config_pins(unsigned long *cfgs, size_t num) +{ + size_t i; + + for (i = 0; i < num; i++) + config_pin(cfgs[i]); +} diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index ed581ae..d4c5137 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -156,6 +156,8 @@ int serial_init (void) writel(lcr, ®s->fr); writel(lcr, ®s->pl011_rlcr); + /* lcrh needs to be set again for change to be effective */ + writel(lcr, ®s->pl011_lcrh); } #endif /* Finally, enable the UART */ diff --git a/include/configs/snowball.h b/include/configs/snowball.h new file mode 100644 index 0000000..6af46a0 --- /dev/null +++ b/include/configs/snowball.h @@ -0,0 +1,258 @@ +/* + * Copyright (C) ST-Ericsson SA 2009 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * #define DEBUG 1 + */ + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SNOWBALL +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_U8500 +#define CONFIG_L2_OFF + +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF +#define CONFIG_SYS_HZ 1000 /* must be 1000 */ + +/*----------------------------------------------------------------------- + * Size of environment and malloc() pool + */ +/* + * If you use U-Boot as crash kernel, make sure that it does not overwrite + * information saved by kexec during panic. Kexec expects the start + * address of the executable 32K above "crashkernel" address. + */ +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (8*1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */ + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV +#define CONFIG_ENV_OFFSET 0x0118000 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* SLOT2: eMMC */ + +/* + * PL011 Configuration + */ +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_SERIAL_RLCR +#define CONFIG_PL011_SERIAL_FLUSH_ON_INIT + +/* + * U8500 UART registers base for 3 serial devices + */ +#define CFG_UART0_BASE 0x80120000 +#define CFG_UART1_BASE 0x80121000 +#define CFG_UART2_BASE 0x80007000 +#define CFG_SERIAL0 CFG_UART0_BASE +#define CFG_SERIAL1 CFG_UART1_BASE +#define CFG_SERIAL2 CFG_UART2_BASE +#define CONFIG_PL011_CLOCK 38400000 +#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \ + (void *)CFG_SERIAL2 } +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Devices and file systems + */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION + +/* + * Commands + */ +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_BDI +#define CONFIG_CMD_IMI +#define CONFIG_CMD_MISC +#define CONFIG_CMD_RUN +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_CONSOLE +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_SOURCE + +#ifndef CONFIG_BOOTDELAY +#define CONFIG_BOOTDELAY 1 +#endif +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ +"mmc dev 1; " \ + "if run loadbootscript; " \ + "then run bootscript; " \ + "else " \ + "if run mmcload; " \ + "then run mmcboot; " \ + "else " \ + "mmc dev 0; " \ + "if run emmcloadbootscript; " \ + "then run bootscript; " \ + "else " \ + "if run emmcload; " \ + "then run emmcboot; " \ + "else " \ + "echo No media to boot from; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "fi; " + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr=0x00100000\0" \ + "console=ttyAMA2,115200n8\0" \ + "loadbootscript=fatload mmc 1:1 ${loadaddr} boot.scr\0" \ + "emmcloadbootscript=fatload mmc 0:2 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript " \ + "from mmc ...; source ${loadaddr}\0" \ + "memargs256=mem=96M at 0 mem_modem=32M at 96M mem=32M at 128M " \ + "hwmem=22M at 160M pmem_hwb=42M at 182M mem_mali=32 at 224M\0" \ + "memargs512=mem=96M at 0 mem_modem=32M at 96M hwmem=32M at 128M " \ + "mem=64M at 160M mem_mali=32M at 224M " \ + "pmem_hwb=128M at 256M mem=128M at 384M\0" \ + "memargs1024=mem=128M at 0 mali.mali_mem=32M at 128M " \ + "hwmem=168M at M160M mem=48M at 328M " \ + "mem_issw=1M at 383M mem=640M at 384M\0" \ + "memargs=setenv bootargs ${bootargs} ${memargs1024}\0" \ + "emmcload=fatload mmc 0:2 ${loadaddr} uImage\0" \ + "mmcload=fatload mmc 1:1 ${loadaddr} uImage\0" \ + "commonargs=setenv bootargs console=${console} " \ + "vmalloc=300M\0" \ + "emmcargs=setenv bootargs ${bootargs} " \ + "root=/dev/mmcblk0p3 " \ + "rootwait\0" \ + "addcons=setenv bootargs ${bootargs} " \ + "console=${console}\0" \ + "emmcboot=echo Booting from eMMC ...; " \ + "run commonargs emmcargs memargs; " \ + "bootm ${loadaddr}\0" \ + "mmcargs=setenv bootargs ${bootargs} " \ + "root=/dev/mmcblk1p2 " \ + "rootwait earlyprintk\0" \ + "mmcboot=echo Booting from external MMC ...; " \ + "run commonargs mmcargs memargs; " \ + "bootm ${loadaddr}\0" \ + "fdt_high=0x2BC00000\0" \ + "stdout=serial,usbtty\0" \ + "stdin=serial,usbtty\0" \ + "stderr=serial,usbtty\0" + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "U8500 $ " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 + +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_SETUP_MEMORY_TAGS 2 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */ +#define PHYS_SDRAM_SIZE_1 0x10000000 /* 256 MB */ + +/* + * additions for new relocation code + */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET + +/* landing address before relocation */ +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0x0 +#endif + +/* + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/* + * base register values for U8500 + */ +#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock */ + + +/* + * U8500 GPIO register base for 9 banks + */ +#define CONFIG_DB8500_GPIO +#define CFG_GPIO_0_BASE 0x8012E000 +#define CFG_GPIO_1_BASE 0x8012E080 +#define CFG_GPIO_2_BASE 0x8000E000 +#define CFG_GPIO_3_BASE 0x8000E080 +#define CFG_GPIO_4_BASE 0x8000E100 +#define CFG_GPIO_5_BASE 0x8000E180 +#define CFG_GPIO_6_BASE 0x8011E000 +#define CFG_GPIO_7_BASE 0x8011E080 +#define CFG_GPIO_8_BASE 0xA03FE000 + +#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */ + +#endif /* __CONFIG_H */ -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 01/11] snowball: Add support for ux500 based snowball board 2012-07-31 18:59 ` [U-Boot] [PATCH 01/11] snowball: Add support for ux500 based " mathieu.poirier at linaro.org @ 2012-08-03 14:46 ` Tom Rini 2012-08-03 19:32 ` Mathieu Poirier 2012-08-03 15:32 ` Tom Rini 1 sibling, 1 reply; 24+ messages in thread From: Tom Rini @ 2012-08-03 14:46 UTC (permalink / raw) To: u-boot On Tue, Jul 31, 2012 at 12:59:23PM -0600, mathieu.poirier at linaro.org wrote: > From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org> > > Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> > Signed-off-by: John Rigby <john.rigby@linaro.org> [snip] > +++ b/board/st-ericsson/snowball/Makefile [snip] > +#prcmu.o Drop please. [snip] > +++ b/board/st-ericsson/snowball/snowball.c > +int dram_init(void) > +{ > + uint32_t unused_cols_rows; > + unsigned int nrows; > + unsigned int ncols; > + > + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; > + gd->ram_size = PHYS_SDRAM_SIZE_1; > + > + /* > + * Assumption: 2 CS active, both CS have same layout. > + * 15 rows max, 11 cols max (controller spec). > + * memory chip has 8 banks, I/O width 32 bit. > + * The correct way would be to read MR#8: I/O width and density, > + * but this requires locking against the PRCMU firmware. > + * Simplified approach: > + * Read number of unused rows and columns from mem controller. > + * size = nCS x 2^(rows+cols) x nbanks x buswidth_bytes > + */ > + unused_cols_rows = readl(DMC_CTL_97); > + nrows = 15 - (unused_cols_rows & 0x07); > + ncols = 11 - ((unused_cols_rows & 0x0700) >> 8); > + gd->ram_size = gd->bd->bi_dram[0].size = > + 2 * (1 << (nrows + ncols)) * 8 * 4; Please use get_mem_size(CONFIG_SYS_SDRAM_BASE, possible-max-size) (and defining CONFIG_SYS_MAX_RAM_SIZE is common convention) instead of all the above. [snip] > +++ b/drivers/gpio/db8500_gpio.c [snip] > +/* > + * Macros to work with IO space > + * Not actually used? > + */ > +#define __iomem <linux/compiler.h> provides this for us, please use that instead. -- Tom ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 01/11] snowball: Add support for ux500 based snowball board 2012-08-03 14:46 ` Tom Rini @ 2012-08-03 19:32 ` Mathieu Poirier 2012-08-03 19:45 ` Tom Rini 0 siblings, 1 reply; 24+ messages in thread From: Mathieu Poirier @ 2012-08-03 19:32 UTC (permalink / raw) To: u-boot Thanks for the review - see my comments below. Mathieu. On 12-08-03 08:46 AM, Tom Rini wrote: > On Tue, Jul 31, 2012 at 12:59:23PM -0600, mathieu.poirier at linaro.org wrote: > >> From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org> >> >> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> >> Signed-off-by: John Rigby <john.rigby@linaro.org> > [snip] >> +++ b/board/st-ericsson/snowball/Makefile > [snip] >> +#prcmu.o > > Drop please. > > [snip] >> +++ b/board/st-ericsson/snowball/snowball.c >> +int dram_init(void) >> +{ >> + uint32_t unused_cols_rows; >> + unsigned int nrows; >> + unsigned int ncols; >> + >> + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; >> + gd->ram_size = PHYS_SDRAM_SIZE_1; >> + >> + /* >> + * Assumption: 2 CS active, both CS have same layout. >> + * 15 rows max, 11 cols max (controller spec). >> + * memory chip has 8 banks, I/O width 32 bit. >> + * The correct way would be to read MR#8: I/O width and density, >> + * but this requires locking against the PRCMU firmware. >> + * Simplified approach: >> + * Read number of unused rows and columns from mem controller. >> + * size = nCS x 2^(rows+cols) x nbanks x buswidth_bytes >> + */ >> + unused_cols_rows = readl(DMC_CTL_97); >> + nrows = 15 - (unused_cols_rows & 0x07); >> + ncols = 11 - ((unused_cols_rows & 0x0700) >> 8); >> + gd->ram_size = gd->bd->bi_dram[0].size = >> + 2 * (1 << (nrows + ncols)) * 8 * 4; > > Please use get_mem_size(CONFIG_SYS_SDRAM_BASE, possible-max-size) (and > defining CONFIG_SYS_MAX_RAM_SIZE is common convention) instead of all > the above. > Is 'get_mem_size' supposed to be an existing API ? I grep'ed for it in the code to no avail. > [snip] >> +++ b/drivers/gpio/db8500_gpio.c > [snip] >> +/* >> + * Macros to work with IO space >> + * Not actually used? >> + */ >> +#define __iomem > > <linux/compiler.h> provides this for us, please use that instead. > ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 01/11] snowball: Add support for ux500 based snowball board 2012-08-03 19:32 ` Mathieu Poirier @ 2012-08-03 19:45 ` Tom Rini 0 siblings, 0 replies; 24+ messages in thread From: Tom Rini @ 2012-08-03 19:45 UTC (permalink / raw) To: u-boot On 08/03/2012 12:32 PM, Mathieu Poirier wrote: > Thanks for the review - see my comments below. > > Mathieu. > > On 12-08-03 08:46 AM, Tom Rini wrote: >> On Tue, Jul 31, 2012 at 12:59:23PM -0600, mathieu.poirier at linaro.org wrote: >> >>> From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org> >>> >>> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> >>> Signed-off-by: John Rigby <john.rigby@linaro.org> >> [snip] >>> +++ b/board/st-ericsson/snowball/Makefile >> [snip] >>> +#prcmu.o >> >> Drop please. >> >> [snip] >>> +++ b/board/st-ericsson/snowball/snowball.c >>> +int dram_init(void) >>> +{ >>> + uint32_t unused_cols_rows; >>> + unsigned int nrows; >>> + unsigned int ncols; >>> + >>> + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; >>> + gd->ram_size = PHYS_SDRAM_SIZE_1; >>> + >>> + /* >>> + * Assumption: 2 CS active, both CS have same layout. >>> + * 15 rows max, 11 cols max (controller spec). >>> + * memory chip has 8 banks, I/O width 32 bit. >>> + * The correct way would be to read MR#8: I/O width and density, >>> + * but this requires locking against the PRCMU firmware. >>> + * Simplified approach: >>> + * Read number of unused rows and columns from mem controller. >>> + * size = nCS x 2^(rows+cols) x nbanks x buswidth_bytes >>> + */ >>> + unused_cols_rows = readl(DMC_CTL_97); >>> + nrows = 15 - (unused_cols_rows & 0x07); >>> + ncols = 11 - ((unused_cols_rows & 0x0700) >> 8); >>> + gd->ram_size = gd->bd->bi_dram[0].size = >>> + 2 * (1 << (nrows + ncols)) * 8 * 4; >> >> Please use get_mem_size(CONFIG_SYS_SDRAM_BASE, possible-max-size) (and >> defining CONFIG_SYS_MAX_RAM_SIZE is common convention) instead of all >> the above. >> > > Is 'get_mem_size' supposed to be an existing API ? I grep'ed for it in > the code to no avail. Arg, sorry, mental error. get_ram_size is the right one. -- Tom ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 01/11] snowball: Add support for ux500 based snowball board 2012-07-31 18:59 ` [U-Boot] [PATCH 01/11] snowball: Add support for ux500 based " mathieu.poirier at linaro.org 2012-08-03 14:46 ` Tom Rini @ 2012-08-03 15:32 ` Tom Rini 1 sibling, 0 replies; 24+ messages in thread From: Tom Rini @ 2012-08-03 15:32 UTC (permalink / raw) To: u-boot On Tue, Jul 31, 2012 at 12:59:23PM -0600, mathieu.poirier at linaro.org wrote: > From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org> > > Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> > Signed-off-by: John Rigby <john.rigby@linaro.org> [snip] > +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } [snip] > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " Both of these aren't needed now, as well. Sorry / thanks! -- Tom ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 02/11] u8500: Moving prcmu to cpu directory 2012-07-31 18:59 [U-Boot] [PATCH 00/11] Support for ST-Ericsson snowball board mathieu.poirier at linaro.org 2012-07-31 18:59 ` [U-Boot] [PATCH 01/11] snowball: Add support for ux500 based " mathieu.poirier at linaro.org @ 2012-07-31 18:59 ` mathieu.poirier at linaro.org 2012-07-31 18:59 ` [U-Boot] [PATCH 03/11] snowball: Adding architecture dependent initialisation mathieu.poirier at linaro.org ` (9 subsequent siblings) 11 siblings, 0 replies; 24+ messages in thread From: mathieu.poirier at linaro.org @ 2012-07-31 18:59 UTC (permalink / raw) To: u-boot From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org> This is to allow the prcmu functions to be used by multiple u8500-based processors. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> --- arch/arm/cpu/armv7/u8500/Makefile | 2 +- arch/arm/cpu/armv7/u8500/prcmu.c | 164 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-u8500/prcmu.h | 55 ++++++++++ board/st-ericsson/u8500/Makefile | 2 +- board/st-ericsson/u8500/prcmu-fw.h | 55 ---------- board/st-ericsson/u8500/prcmu.c | 165 ------------------------------- board/st-ericsson/u8500/u8500_href.c | 2 +- 7 files changed, 222 insertions(+), 223 deletions(-) create mode 100644 arch/arm/cpu/armv7/u8500/prcmu.c create mode 100644 arch/arm/include/asm/arch-u8500/prcmu.h delete mode 100644 board/st-ericsson/u8500/prcmu-fw.h delete mode 100644 board/st-ericsson/u8500/prcmu.c diff --git a/arch/arm/cpu/armv7/u8500/Makefile b/arch/arm/cpu/armv7/u8500/Makefile index 270aa40..77accde 100644 --- a/arch/arm/cpu/armv7/u8500/Makefile +++ b/arch/arm/cpu/armv7/u8500/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS = timer.o clock.o +COBJS = timer.o clock.o prcmu.o SOBJS = lowlevel.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/arch/arm/cpu/armv7/u8500/prcmu.c b/arch/arm/cpu/armv7/u8500/prcmu.c new file mode 100644 index 0000000..b256d27 --- /dev/null +++ b/arch/arm/cpu/armv7/u8500/prcmu.c @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2009 ST-Ericsson SA + * + * Adapted from the Linux version: + * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + */ + +/* + * NOTE: This currently does not support the I2C workaround access method. + */ + +#include <common.h> +#include <config.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/types.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/prcmu.h> + +/* CPU mailbox registers */ +#define PRCM_MBOX_CPU_VAL (U8500_PRCMU_BASE + 0x0fc) +#define PRCM_MBOX_CPU_SET (U8500_PRCMU_BASE + 0x100) +#define PRCM_MBOX_CPU_CLR (U8500_PRCMU_BASE + 0x104) + +static int prcmu_is_ready(void) +{ + int ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE; + if (!ready) + printf("PRCMU firmware not ready\n"); + return ready; +} + +static int _wait_for_req_complete(int num) +{ + int timeout = 1000; + + /* checking any already on-going transaction */ + while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout) + timeout--; + + timeout = 1000; + + /* Set an interrupt to XP70 */ + writel(1 << num, PRCM_MBOX_CPU_SET); + + while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout) + timeout--; + + if (!timeout) { + printf("PRCMU operation timed out\n"); + return -1; + } + + return 0; +} + +/** + * prcmu_i2c_read - PRCMU - 4500 communication using PRCMU I2C + * @reg: - db8500 register bank to be accessed + * @slave: - db8500 register to be accessed + * Returns: ACK_MB5 value containing the status + */ +int prcmu_i2c_read(u8 reg, u16 slave) +{ + uint8_t i2c_status; + uint8_t i2c_val; + + if (!prcmu_is_ready()) + return -1; + + debug("\nprcmu_4500_i2c_read:bank=%x;reg=%x;\n", + reg, slave); + + /* prepare the data for mailbox 5 */ + writeb((reg << 1) | I2CREAD, PRCM_REQ_MB5_I2COPTYPE_REG); + writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS); + writeb(slave, PRCM_REQ_MB5_I2CSLAVE); + writeb(0, PRCM_REQ_MB5_I2CVAL); + + _wait_for_req_complete(REQ_MB5); + + /* retrieve values */ + debug("ack-mb5:transfer status = %x\n", + readb(PRCM_ACK_MB5_STATUS)); + debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1); + debug("ack-mb5:slave_add = %x\n", + readb(PRCM_ACK_MB5_SLAVE)); + debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL)); + + i2c_status = readb(PRCM_ACK_MB5_STATUS); + i2c_val = readb(PRCM_ACK_MB5_VAL); + + if (i2c_status == I2C_RD_OK) + return i2c_val; + else { + + printf("prcmu_i2c_read:read return status= %d\n", + i2c_status); + return -1; + } + +} + +/** + * prcmu_i2c_write - PRCMU-db8500 communication using PRCMU I2C + * @reg: - db8500 register bank to be accessed + * @slave: - db800 register to be written to + * @reg_data: - the data to write + * Returns: ACK_MB5 value containing the status + */ +int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data) +{ + uint8_t i2c_status; + + if (!prcmu_is_ready()) + return -1; + + debug("\nprcmu_4500_i2c_write:bank=%x;reg=%x;\n", + reg, slave); + + /* prepare the data for mailbox 5 */ + writeb((reg << 1) | I2CWRITE, PRCM_REQ_MB5_I2COPTYPE_REG); + writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS); + writeb(slave, PRCM_REQ_MB5_I2CSLAVE); + writeb(reg_data, PRCM_REQ_MB5_I2CVAL); + + debug("\ncpu_is_u8500v11\n"); + _wait_for_req_complete(REQ_MB5); + + /* retrieve values */ + debug("ack-mb5:transfer status = %x\n", + readb(PRCM_ACK_MB5_STATUS)); + debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1); + debug("ack-mb5:slave_add = %x\n", + readb(PRCM_ACK_MB5_SLAVE)); + debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL)); + + i2c_status = readb(PRCM_ACK_MB5_STATUS); + debug("\ni2c_status = %x\n", i2c_status); + if (i2c_status == I2C_WR_OK) + return 0; + else { + printf("ape-i2c: i2c_status : 0x%x\n", i2c_status); + return -1; + } +} diff --git a/arch/arm/include/asm/arch-u8500/prcmu.h b/arch/arm/include/asm/arch-u8500/prcmu.h new file mode 100644 index 0000000..0836983 --- /dev/null +++ b/arch/arm/include/asm/arch-u8500/prcmu.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2009 ST-Ericsson SA + * + * Copied from the Linux version: + * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef __MACH_PRCMU_FW_V1_H +#define __MACH_PRCMU_FW_V1_H + +#define AP_EXECUTE 2 +#define I2CREAD 1 +#define I2C_WR_OK 1 +#define I2C_RD_OK 2 +#define I2CWRITE 0 + +#define _PRCMU_TCDM_BASE U8500_PRCMU_TCDM_BASE +#define PRCM_XP70_CUR_PWR_STATE (_PRCMU_TCDM_BASE + 0xFFC) /* 4 BYTES */ + +#define PRCM_REQ_MB5 (_PRCMU_TCDM_BASE + 0xE44) /* 4 bytes */ +#define PRCM_ACK_MB5 (_PRCMU_TCDM_BASE + 0xDF4) /* 4 bytes */ + +/* Mailbox 5 Requests */ +#define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0) +#define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1) +#define PRCM_REQ_MB5_I2CSLAVE (PRCM_REQ_MB5 + 0x2) +#define PRCM_REQ_MB5_I2CVAL (PRCM_REQ_MB5 + 0x3) + +/* Mailbox 5 ACKs */ +#define PRCM_ACK_MB5_STATUS (PRCM_ACK_MB5 + 0x1) +#define PRCM_ACK_MB5_SLAVE (PRCM_ACK_MB5 + 0x2) +#define PRCM_ACK_MB5_VAL (PRCM_ACK_MB5 + 0x3) + +#define LOW_POWER_WAKEUP 1 +#define EXE_WAKEUP 0 + +#define REQ_MB5 5 + +extern int prcmu_i2c_read(u8 reg, u16 slave); +extern int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data); + +#endif /* __MACH_PRCMU_FW_V1_H */ diff --git a/board/st-ericsson/u8500/Makefile b/board/st-ericsson/u8500/Makefile index 4091a42..4ea2212 100644 --- a/board/st-ericsson/u8500/Makefile +++ b/board/st-ericsson/u8500/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk CFLAGS += -D__RELEASE -D__STN_8500 LIB = $(obj)lib$(BOARD).o -COBJS := u8500_href.o gpio.o prcmu.o +COBJS := u8500_href.o gpio.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/st-ericsson/u8500/prcmu-fw.h b/board/st-ericsson/u8500/prcmu-fw.h deleted file mode 100644 index 0836983..0000000 --- a/board/st-ericsson/u8500/prcmu-fw.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (C) 2009 ST-Ericsson SA - * - * Copied from the Linux version: - * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#ifndef __MACH_PRCMU_FW_V1_H -#define __MACH_PRCMU_FW_V1_H - -#define AP_EXECUTE 2 -#define I2CREAD 1 -#define I2C_WR_OK 1 -#define I2C_RD_OK 2 -#define I2CWRITE 0 - -#define _PRCMU_TCDM_BASE U8500_PRCMU_TCDM_BASE -#define PRCM_XP70_CUR_PWR_STATE (_PRCMU_TCDM_BASE + 0xFFC) /* 4 BYTES */ - -#define PRCM_REQ_MB5 (_PRCMU_TCDM_BASE + 0xE44) /* 4 bytes */ -#define PRCM_ACK_MB5 (_PRCMU_TCDM_BASE + 0xDF4) /* 4 bytes */ - -/* Mailbox 5 Requests */ -#define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0) -#define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1) -#define PRCM_REQ_MB5_I2CSLAVE (PRCM_REQ_MB5 + 0x2) -#define PRCM_REQ_MB5_I2CVAL (PRCM_REQ_MB5 + 0x3) - -/* Mailbox 5 ACKs */ -#define PRCM_ACK_MB5_STATUS (PRCM_ACK_MB5 + 0x1) -#define PRCM_ACK_MB5_SLAVE (PRCM_ACK_MB5 + 0x2) -#define PRCM_ACK_MB5_VAL (PRCM_ACK_MB5 + 0x3) - -#define LOW_POWER_WAKEUP 1 -#define EXE_WAKEUP 0 - -#define REQ_MB5 5 - -extern int prcmu_i2c_read(u8 reg, u16 slave); -extern int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data); - -#endif /* __MACH_PRCMU_FW_V1_H */ diff --git a/board/st-ericsson/u8500/prcmu.c b/board/st-ericsson/u8500/prcmu.c deleted file mode 100644 index 6f9302f..0000000 --- a/board/st-ericsson/u8500/prcmu.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright (C) 2009 ST-Ericsson SA - * - * Adapted from the Linux version: - * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - */ - -/* - * NOTE: This currently does not support the I2C workaround access method. - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/types.h> -#include <asm/io.h> -#include <asm/errno.h> - -#include "prcmu-fw.h" - -/* CPU mailbox registers */ -#define PRCM_MBOX_CPU_VAL (U8500_PRCMU_BASE + 0x0fc) -#define PRCM_MBOX_CPU_SET (U8500_PRCMU_BASE + 0x100) -#define PRCM_MBOX_CPU_CLR (U8500_PRCMU_BASE + 0x104) - -static int prcmu_is_ready(void) -{ - int ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE; - if (!ready) - printf("PRCMU firmware not ready\n"); - return ready; -} - -static int _wait_for_req_complete(int num) -{ - int timeout = 1000; - - /* checking any already on-going transaction */ - while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout--) - ; - - timeout = 1000; - - /* Set an interrupt to XP70 */ - writel(1 << num, PRCM_MBOX_CPU_SET); - - while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout--) - ; - - if (!timeout) { - printf("PRCMU operation timed out\n"); - return -1; - } - - return 0; -} - -/** - * prcmu_i2c_read - PRCMU - 4500 communication using PRCMU I2C - * @reg: - db8500 register bank to be accessed - * @slave: - db8500 register to be accessed - * Returns: ACK_MB5 value containing the status - */ -int prcmu_i2c_read(u8 reg, u16 slave) -{ - uint8_t i2c_status; - uint8_t i2c_val; - - if (!prcmu_is_ready()) - return -1; - - debug("\nprcmu_4500_i2c_read:bank=%x;reg=%x;\n", - reg, slave); - - /* prepare the data for mailbox 5 */ - writeb((reg << 1) | I2CREAD, PRCM_REQ_MB5_I2COPTYPE_REG); - writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS); - writeb(slave, PRCM_REQ_MB5_I2CSLAVE); - writeb(0, PRCM_REQ_MB5_I2CVAL); - - _wait_for_req_complete(REQ_MB5); - - /* retrieve values */ - debug("ack-mb5:transfer status = %x\n", - readb(PRCM_ACK_MB5_STATUS)); - debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1); - debug("ack-mb5:slave_add = %x\n", - readb(PRCM_ACK_MB5_SLAVE)); - debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL)); - - i2c_status = readb(PRCM_ACK_MB5_STATUS); - i2c_val = readb(PRCM_ACK_MB5_VAL); - - if (i2c_status == I2C_RD_OK) - return i2c_val; - else { - - printf("prcmu_i2c_read:read return status= %d\n", - i2c_status); - return -1; - } - -} - -/** - * prcmu_i2c_write - PRCMU-db8500 communication using PRCMU I2C - * @reg: - db8500 register bank to be accessed - * @slave: - db800 register to be written to - * @reg_data: - the data to write - * Returns: ACK_MB5 value containing the status - */ -int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data) -{ - uint8_t i2c_status; - - if (!prcmu_is_ready()) - return -1; - - debug("\nprcmu_4500_i2c_write:bank=%x;reg=%x;\n", - reg, slave); - - /* prepare the data for mailbox 5 */ - writeb((reg << 1) | I2CWRITE, PRCM_REQ_MB5_I2COPTYPE_REG); - writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS); - writeb(slave, PRCM_REQ_MB5_I2CSLAVE); - writeb(reg_data, PRCM_REQ_MB5_I2CVAL); - - debug("\ncpu_is_u8500v11\n"); - _wait_for_req_complete(REQ_MB5); - - /* retrieve values */ - debug("ack-mb5:transfer status = %x\n", - readb(PRCM_ACK_MB5_STATUS)); - debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1); - debug("ack-mb5:slave_add = %x\n", - readb(PRCM_ACK_MB5_SLAVE)); - debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL)); - - i2c_status = readb(PRCM_ACK_MB5_STATUS); - debug("\ni2c_status = %x\n", i2c_status); - if (i2c_status == I2C_WR_OK) - return 0; - else { - printf("ape-i2c: i2c_status : 0x%x\n", i2c_status); - return -1; - } -} diff --git a/board/st-ericsson/u8500/u8500_href.c b/board/st-ericsson/u8500/u8500_href.c index 5f85fdc..6e3fc87 100644 --- a/board/st-ericsson/u8500/u8500_href.c +++ b/board/st-ericsson/u8500/u8500_href.c @@ -27,7 +27,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #ifdef CONFIG_MMC -#include "prcmu-fw.h" +#include <asm/arch/prcmu.h> #include "../../../drivers/mmc/arm_pl180_mmci.h" #endif -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 03/11] snowball: Adding architecture dependent initialisation 2012-07-31 18:59 [U-Boot] [PATCH 00/11] Support for ST-Ericsson snowball board mathieu.poirier at linaro.org 2012-07-31 18:59 ` [U-Boot] [PATCH 01/11] snowball: Add support for ux500 based " mathieu.poirier at linaro.org 2012-07-31 18:59 ` [U-Boot] [PATCH 02/11] u8500: Moving prcmu to cpu directory mathieu.poirier at linaro.org @ 2012-07-31 18:59 ` mathieu.poirier at linaro.org 2012-07-31 18:59 ` [U-Boot] [PATCH 04/11] snowball: Adding CPU clock initialisation mathieu.poirier at linaro.org ` (8 subsequent siblings) 11 siblings, 0 replies; 24+ messages in thread From: mathieu.poirier at linaro.org @ 2012-07-31 18:59 UTC (permalink / raw) To: u-boot From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org> Enabling timers and clocks in PRCMU and cleaning up mailbox. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> --- arch/arm/cpu/armv7/u8500/Makefile | 2 +- arch/arm/cpu/armv7/u8500/cpu.c | 41 +++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/u8500/prcmu.c | 30 ++++++++++++++++++++++ arch/arm/include/asm/arch-u8500/prcmu.h | 24 ++++++++++++++---- board/st-ericsson/u8500/u8500_href.c | 2 +- include/configs/snowball.h | 1 + 6 files changed, 93 insertions(+), 7 deletions(-) create mode 100644 arch/arm/cpu/armv7/u8500/cpu.c diff --git a/arch/arm/cpu/armv7/u8500/Makefile b/arch/arm/cpu/armv7/u8500/Makefile index 77accde..ce8af96 100644 --- a/arch/arm/cpu/armv7/u8500/Makefile +++ b/arch/arm/cpu/armv7/u8500/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS = timer.o clock.o prcmu.o +COBJS = timer.o clock.o prcmu.o cpu.o SOBJS = lowlevel.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/arch/arm/cpu/armv7/u8500/cpu.c b/arch/arm/cpu/armv7/u8500/cpu.c new file mode 100644 index 0000000..04f4b19 --- /dev/null +++ b/arch/arm/cpu/armv7/u8500/cpu.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2012 Linaro Limited + * Mathieu Poirier <mathieu.poirier@linaro.org> + * + * Based on original code from Joakim Axelsson at ST-Ericsson + * (C) Copyright 2010 ST-Ericsson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/prcmu.h> + +#ifdef CONFIG_ARCH_CPU_INIT +/* + * SOC specific cpu init + */ +int arch_cpu_init(void) +{ + db8500_prcmu_init(); + + return 0; +} +#endif /* CONFIG_ARCH_CPU_INIT */ diff --git a/arch/arm/cpu/armv7/u8500/prcmu.c b/arch/arm/cpu/armv7/u8500/prcmu.c index b256d27..4918bbc 100644 --- a/arch/arm/cpu/armv7/u8500/prcmu.c +++ b/arch/arm/cpu/armv7/u8500/prcmu.c @@ -40,6 +40,8 @@ #define PRCM_MBOX_CPU_SET (U8500_PRCMU_BASE + 0x100) #define PRCM_MBOX_CPU_CLR (U8500_PRCMU_BASE + 0x104) +#define I2C_MBOX_BIT (1 << 5) + static int prcmu_is_ready(void) { int ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE; @@ -162,3 +164,31 @@ int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data) return -1; } } + +void u8500_prcmu_enable(u32 *reg) +{ + writel(readl(reg) | (1 << 8), reg); +} + +void db8500_prcmu_init(void) +{ + /* Enable timers */ + writel(1 << 17, PRCM_TCR); + + u8500_prcmu_enable((u32 *)PRCM_PER1CLK_MGT_REG); + u8500_prcmu_enable((u32 *)PRCM_PER2CLK_MGT_REG); + u8500_prcmu_enable((u32 *)PRCM_PER3CLK_MGT_REG); + /* PER4CLK does not exist */ + u8500_prcmu_enable((u32 *)PRCM_PER5CLK_MGT_REG); + u8500_prcmu_enable((u32 *)PRCM_PER6CLK_MGT_REG); + /* Only exists in ED but is always ok to write to */ + u8500_prcmu_enable((u32 *)PRCM_PER7CLK_MGT_REG); + + u8500_prcmu_enable((u32 *)PRCM_UARTCLK_MGT_REG); + u8500_prcmu_enable((u32 *)PRCM_I2CCLK_MGT_REG); + + u8500_prcmu_enable((u32 *)PRCM_SDMMCCLK_MGT_REG); + + /* Clean up the mailbox interrupts after pre-u-boot code. */ + writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR); +} diff --git a/arch/arm/include/asm/arch-u8500/prcmu.h b/arch/arm/include/asm/arch-u8500/prcmu.h index 0836983..1fd4d2a 100644 --- a/arch/arm/include/asm/arch-u8500/prcmu.h +++ b/arch/arm/include/asm/arch-u8500/prcmu.h @@ -27,12 +27,23 @@ #define I2C_RD_OK 2 #define I2CWRITE 0 -#define _PRCMU_TCDM_BASE U8500_PRCMU_TCDM_BASE -#define PRCM_XP70_CUR_PWR_STATE (_PRCMU_TCDM_BASE + 0xFFC) /* 4 BYTES */ - -#define PRCM_REQ_MB5 (_PRCMU_TCDM_BASE + 0xE44) /* 4 bytes */ -#define PRCM_ACK_MB5 (_PRCMU_TCDM_BASE + 0xDF4) /* 4 bytes */ +#define PRCMU_BASE U8500_PRCMU_BASE +#define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018) +#define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C) +#define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020) +#define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024) +#define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C) +#define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030) +#define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034) +#define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038) +#define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C) +#define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040) +#define PRCM_ARM_IT1_CLEAR (PRCMU_BASE + 0x48C) +#define PRCM_TCR (PRCMU_BASE + 0x1C8) +#define PRCM_REQ_MB5 (PRCMU_BASE + 0xE44) +#define PRCM_ACK_MB5 (PRCMU_BASE + 0xDF4) +#define PRCM_XP70_CUR_PWR_STATE (PRCMU_BASE + 0xFFC) /* Mailbox 5 Requests */ #define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0) #define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1) @@ -52,4 +63,7 @@ extern int prcmu_i2c_read(u8 reg, u16 slave); extern int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data); +void u8500_prcmu_enable(u32 *reg); +void db8500_prcmu_init(void); + #endif /* __MACH_PRCMU_FW_V1_H */ diff --git a/board/st-ericsson/u8500/u8500_href.c b/board/st-ericsson/u8500/u8500_href.c index 6e3fc87..fe72684 100644 --- a/board/st-ericsson/u8500/u8500_href.c +++ b/board/st-ericsson/u8500/u8500_href.c @@ -26,8 +26,8 @@ #include <asm/arch/gpio.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> -#ifdef CONFIG_MMC #include <asm/arch/prcmu.h> +#ifdef CONFIG_MMC #include "../../../drivers/mmc/arm_pl180_mmci.h" #endif diff --git a/include/configs/snowball.h b/include/configs/snowball.h index 6af46a0..bb8970b 100644 --- a/include/configs/snowball.h +++ b/include/configs/snowball.h @@ -31,6 +31,7 @@ #define CONFIG_SNOWBALL #define CONFIG_SYS_ICACHE_OFF #define CONFIG_SYS_DCACHE_OFF +#define CONFIG_ARCH_CPU_INIT /* * High Level Configuration Options -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 04/11] snowball: Adding CPU clock initialisation 2012-07-31 18:59 [U-Boot] [PATCH 00/11] Support for ST-Ericsson snowball board mathieu.poirier at linaro.org ` (2 preceding siblings ...) 2012-07-31 18:59 ` [U-Boot] [PATCH 03/11] snowball: Adding architecture dependent initialisation mathieu.poirier at linaro.org @ 2012-07-31 18:59 ` mathieu.poirier at linaro.org 2012-07-31 18:59 ` [U-Boot] [PATCH 05/11] snowball: Moving to ux500.v2 addess scheme for PRCMU access mathieu.poirier at linaro.org ` (7 subsequent siblings) 11 siblings, 0 replies; 24+ messages in thread From: mathieu.poirier at linaro.org @ 2012-07-31 18:59 UTC (permalink / raw) To: u-boot From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> --- arch/arm/cpu/armv7/u8500/clock.c | 34 +++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/u8500/cpu.c | 2 + arch/arm/include/asm/arch-u8500/clock.h | 5 +--- 3 files changed, 37 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/u8500/clock.c b/arch/arm/cpu/armv7/u8500/clock.c index 9e3b873..fcfd61a 100644 --- a/arch/arm/cpu/armv7/u8500/clock.c +++ b/arch/arm/cpu/armv7/u8500/clock.c @@ -54,3 +54,37 @@ void u8500_clock_enable(int periph, int cluster, int kern) if (cluster != -1) writel(1 << cluster, &clkrst->pcken); } + +void db8500_clocks_init(void) +{ + /* + * Enable all clocks. This is u-boot, we can enable it all. There is no + * powersave in u-boot. + */ + + u8500_clock_enable(1, 9, -1); /* GPIO0 */ + u8500_clock_enable(2, 11, -1);/* GPIO1 */ + u8500_clock_enable(3, 8, -1); /* GPIO2 */ + u8500_clock_enable(5, 1, -1); /* GPIO3 */ + u8500_clock_enable(3, 6, 6); /* UART2 */ + u8500_clock_enable(3, 3, 3); /* I2C0 */ + u8500_clock_enable(1, 5, 5); /* SDI0 */ + u8500_clock_enable(2, 4, 2); /* SDI4 */ + u8500_clock_enable(6, 6, -1); /* MTU0 */ + u8500_clock_enable(3, 4, 4); /* SDI2 */ + + /* + * Enabling clocks for all devices which are AMBA devices in the + * kernel. Otherwise they will not get probe()'d because the + * peripheral ID register will not be powered. + */ + + /* XXX: some of these differ between ED/V1 */ + + u8500_clock_enable(1, 1, 1); /* UART1 */ + u8500_clock_enable(1, 0, 0); /* UART0 */ + u8500_clock_enable(3, 2, 2); /* SSP1 */ + u8500_clock_enable(3, 1, 1); /* SSP0 */ + u8500_clock_enable(2, 8, -1); /* SPI0 */ + u8500_clock_enable(2, 5, 3); /* MSP2 */ +} diff --git a/arch/arm/cpu/armv7/u8500/cpu.c b/arch/arm/cpu/armv7/u8500/cpu.c index 04f4b19..fece201 100644 --- a/arch/arm/cpu/armv7/u8500/cpu.c +++ b/arch/arm/cpu/armv7/u8500/cpu.c @@ -27,6 +27,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/prcmu.h> +#include <asm/arch/clock.h> #ifdef CONFIG_ARCH_CPU_INIT /* @@ -35,6 +36,7 @@ int arch_cpu_init(void) { db8500_prcmu_init(); + db8500_clocks_init(); return 0; } diff --git a/arch/arm/include/asm/arch-u8500/clock.h b/arch/arm/include/asm/arch-u8500/clock.h index b00ab0d..2a14784 100644 --- a/arch/arm/include/asm/arch-u8500/clock.h +++ b/arch/arm/include/asm/arch-u8500/clock.h @@ -64,9 +64,6 @@ struct prcmu { extern void u8500_clock_enable(int periph, int kern, int cluster); -static inline void u8500_prcmu_enable(unsigned int *reg) -{ - writel(readl(reg) | (1 << 8), reg); -} +void db8500_clocks_init(void); #endif /* __ASM_ARCH_CLOCK */ -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 05/11] snowball: Moving to ux500.v2 addess scheme for PRCMU access 2012-07-31 18:59 [U-Boot] [PATCH 00/11] Support for ST-Ericsson snowball board mathieu.poirier at linaro.org ` (3 preceding siblings ...) 2012-07-31 18:59 ` [U-Boot] [PATCH 04/11] snowball: Adding CPU clock initialisation mathieu.poirier at linaro.org @ 2012-07-31 18:59 ` mathieu.poirier at linaro.org 2012-07-31 18:59 ` [U-Boot] [PATCH 06/11] snowball: applying power to LAN and GBF controllers mathieu.poirier at linaro.org ` (6 subsequent siblings) 11 siblings, 0 replies; 24+ messages in thread From: mathieu.poirier at linaro.org @ 2012-07-31 18:59 UTC (permalink / raw) To: u-boot From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org> Addresses between ux500.v1 and ux500.v2 have changed slightly, hence mandating a review of the PRCMU access methods. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> --- arch/arm/cpu/armv7/u8500/prcmu.c | 91 +++++++++++++++++++--------- arch/arm/include/asm/arch-u8500/hardware.h | 2 +- arch/arm/include/asm/arch-u8500/prcmu.h | 10 ++- 3 files changed, 71 insertions(+), 32 deletions(-) diff --git a/arch/arm/cpu/armv7/u8500/prcmu.c b/arch/arm/cpu/armv7/u8500/prcmu.c index 4918bbc..934428f 100644 --- a/arch/arm/cpu/armv7/u8500/prcmu.c +++ b/arch/arm/cpu/armv7/u8500/prcmu.c @@ -36,9 +36,10 @@ #include <asm/arch/prcmu.h> /* CPU mailbox registers */ -#define PRCM_MBOX_CPU_VAL (U8500_PRCMU_BASE + 0x0fc) -#define PRCM_MBOX_CPU_SET (U8500_PRCMU_BASE + 0x100) -#define PRCM_MBOX_CPU_CLR (U8500_PRCMU_BASE + 0x104) +#define PRCMU_I2C_WRITE(slave) \ + (((slave) << 1) | I2CWRITE | (1 << 6)) +#define PRCMU_I2C_READ(slave) \ + (((slave) << 1) | I2CREAD | (1 << 6)) #define I2C_MBOX_BIT (1 << 5) @@ -50,26 +51,39 @@ static int prcmu_is_ready(void) return ready; } -static int _wait_for_req_complete(int num) +static int wait_for_i2c_mbx_rdy(void) { - int timeout = 1000; + int timeout = 10000; - /* checking any already on-going transaction */ - while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout) + if (readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) { + printf("prcmu: warning i2c mailbox was not acked\n"); + /* clear mailbox 5 ack irq */ + writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR); + } + + /* check any already on-going transaction */ + while ((readl(PRCM_MBOX_CPU_VAL) & I2C_MBOX_BIT) && timeout) timeout--; - timeout = 1000; + if (timeout == 0) + return -1; + + return 0; +} + +static int wait_for_i2c_req_done(void) +{ + int timeout = 10000; /* Set an interrupt to XP70 */ - writel(1 << num, PRCM_MBOX_CPU_SET); + writel(I2C_MBOX_BIT, PRCM_MBOX_CPU_SET); - while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout) + /* wait for mailbox 5 (i2c) ack */ + while (!(readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) && timeout) timeout--; - if (!timeout) { - printf("PRCMU operation timed out\n"); + if (timeout == 0) return -1; - } return 0; } @@ -84,6 +98,7 @@ int prcmu_i2c_read(u8 reg, u16 slave) { uint8_t i2c_status; uint8_t i2c_val; + int ret; if (!prcmu_is_ready()) return -1; @@ -91,13 +106,23 @@ int prcmu_i2c_read(u8 reg, u16 slave) debug("\nprcmu_4500_i2c_read:bank=%x;reg=%x;\n", reg, slave); + ret = wait_for_i2c_mbx_rdy(); + if (ret) { + printf("prcmu_i2c_read: mailbox became not ready\n"); + return ret; + } + /* prepare the data for mailbox 5 */ - writeb((reg << 1) | I2CREAD, PRCM_REQ_MB5_I2COPTYPE_REG); + writeb(PRCMU_I2C_READ(reg), PRCM_REQ_MB5_I2COPTYPE_REG); writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS); writeb(slave, PRCM_REQ_MB5_I2CSLAVE); writeb(0, PRCM_REQ_MB5_I2CVAL); - _wait_for_req_complete(REQ_MB5); + ret = wait_for_i2c_req_done(); + if (ret) { + printf("prcmu_i2c_read: mailbox request timed out\n"); + return ret; + } /* retrieve values */ debug("ack-mb5:transfer status = %x\n", @@ -109,16 +134,14 @@ int prcmu_i2c_read(u8 reg, u16 slave) i2c_status = readb(PRCM_ACK_MB5_STATUS); i2c_val = readb(PRCM_ACK_MB5_VAL); + /* clear mailbox 5 ack irq */ + writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR); if (i2c_status == I2C_RD_OK) return i2c_val; - else { - - printf("prcmu_i2c_read:read return status= %d\n", - i2c_status); - return -1; - } + printf("prcmu_i2c_read:read return status= %d\n", i2c_status); + return -1; } /** @@ -131,6 +154,7 @@ int prcmu_i2c_read(u8 reg, u16 slave) int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data) { uint8_t i2c_status; + int ret; if (!prcmu_is_ready()) return -1; @@ -138,14 +162,23 @@ int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data) debug("\nprcmu_4500_i2c_write:bank=%x;reg=%x;\n", reg, slave); + ret = wait_for_i2c_mbx_rdy(); + if (ret) { + printf("prcmu_i2c_write: mailbox became not ready\n"); + return ret; + } + /* prepare the data for mailbox 5 */ - writeb((reg << 1) | I2CWRITE, PRCM_REQ_MB5_I2COPTYPE_REG); + writeb(PRCMU_I2C_WRITE(reg), PRCM_REQ_MB5_I2COPTYPE_REG); writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS); writeb(slave, PRCM_REQ_MB5_I2CSLAVE); writeb(reg_data, PRCM_REQ_MB5_I2CVAL); - debug("\ncpu_is_u8500v11\n"); - _wait_for_req_complete(REQ_MB5); + ret = wait_for_i2c_req_done(); + if (ret) { + printf("prcmu_i2c_write: mailbox request timed out\n"); + return ret; + } /* retrieve values */ debug("ack-mb5:transfer status = %x\n", @@ -157,12 +190,14 @@ int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data) i2c_status = readb(PRCM_ACK_MB5_STATUS); debug("\ni2c_status = %x\n", i2c_status); + /* clear mailbox 5 ack irq */ + writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR); + if (i2c_status == I2C_WR_OK) return 0; - else { - printf("ape-i2c: i2c_status : 0x%x\n", i2c_status); - return -1; - } + + printf("%s: i2c_status : 0x%x\n", __func__, i2c_status); + return -1; } void u8500_prcmu_enable(u32 *reg) diff --git a/arch/arm/include/asm/arch-u8500/hardware.h b/arch/arm/include/asm/arch-u8500/hardware.h index 6bb95ec..9208880 100644 --- a/arch/arm/include/asm/arch-u8500/hardware.h +++ b/arch/arm/include/asm/arch-u8500/hardware.h @@ -62,7 +62,7 @@ /* Per4 */ #define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) -#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x0f000) +#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x06800) /* Per3 */ #define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000) diff --git a/arch/arm/include/asm/arch-u8500/prcmu.h b/arch/arm/include/asm/arch-u8500/prcmu.h index 1fd4d2a..9862eb3 100644 --- a/arch/arm/include/asm/arch-u8500/prcmu.h +++ b/arch/arm/include/asm/arch-u8500/prcmu.h @@ -28,6 +28,7 @@ #define I2CWRITE 0 #define PRCMU_BASE U8500_PRCMU_BASE +#define PRCMU_BASE_TCDM U8500_PRCMU_TCDM_BASE #define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018) #define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C) #define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020) @@ -38,12 +39,15 @@ #define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038) #define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C) #define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040) +#define PRCM_MBOX_CPU_VAL (PRCMU_BASE + 0x0FC) +#define PRCM_MBOX_CPU_SET (PRCMU_BASE + 0x100) #define PRCM_ARM_IT1_CLEAR (PRCMU_BASE + 0x48C) +#define PRCM_ARM_IT1_VAL (PRCMU_BASE + 0x494) #define PRCM_TCR (PRCMU_BASE + 0x1C8) -#define PRCM_REQ_MB5 (PRCMU_BASE + 0xE44) -#define PRCM_ACK_MB5 (PRCMU_BASE + 0xDF4) -#define PRCM_XP70_CUR_PWR_STATE (PRCMU_BASE + 0xFFC) +#define PRCM_REQ_MB5 (PRCMU_BASE_TCDM + 0xE44) +#define PRCM_ACK_MB5 (PRCMU_BASE_TCDM + 0xDF4) +#define PRCM_XP70_CUR_PWR_STATE (PRCMU_BASE_TCDM + 0xFFC) /* Mailbox 5 Requests */ #define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0) #define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1) -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 06/11] snowball: applying power to LAN and GBF controllers 2012-07-31 18:59 [U-Boot] [PATCH 00/11] Support for ST-Ericsson snowball board mathieu.poirier at linaro.org ` (4 preceding siblings ...) 2012-07-31 18:59 ` [U-Boot] [PATCH 05/11] snowball: Moving to ux500.v2 addess scheme for PRCMU access mathieu.poirier at linaro.org @ 2012-07-31 18:59 ` mathieu.poirier at linaro.org 2012-07-31 18:59 ` [U-Boot] [PATCH 07/11] u8500: Moving processor-specific functions to cpu area mathieu.poirier at linaro.org ` (5 subsequent siblings) 11 siblings, 0 replies; 24+ messages in thread From: mathieu.poirier at linaro.org @ 2012-07-31 18:59 UTC (permalink / raw) To: u-boot From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org> LAN and GBF need to be powered explicitely, doing so with interface to AB8500 companion chip. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> --- arch/arm/include/asm/arch-u8500/hardware.h | 11 +++- arch/arm/include/asm/arch-u8500/prcmu.h | 7 ++- board/st-ericsson/snowball/snowball.c | 87 ++++++++++++++++++++++++++++ include/configs/snowball.h | 1 + 4 files changed, 103 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch-u8500/hardware.h b/arch/arm/include/asm/arch-u8500/hardware.h index 9208880..8044ac3 100644 --- a/arch/arm/include/asm/arch-u8500/hardware.h +++ b/arch/arm/include/asm/arch-u8500/hardware.h @@ -62,7 +62,7 @@ /* Per4 */ #define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) -#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x06800) +#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) /* Per3 */ #define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000) @@ -80,4 +80,13 @@ #define U8500_BOOTROM_BASE 0x9001f000 #define U8500_BOOTROM_ASIC_ID_OFFSET 0x0ff4 +/* AB8500 specifics */ +#define AB8500_MISC 0x0010 +#define AB8500_GPIO_SEL2_REG 0x1001 +#define AB8500_GPIO_DIR2_REG 0x1011 +#define AB8500_GPIO_DIR4_REG 0x1013 +#define AB8500_GPIO_SEL4_REG 0x1003 +#define AB8500_GPIO_OUT2_REG 0x1021 +#define AB8500_GPIO_OUT4_REG 0x1023 + #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-u8500/prcmu.h b/arch/arm/include/asm/arch-u8500/prcmu.h index 9862eb3..e9dcc93 100644 --- a/arch/arm/include/asm/arch-u8500/prcmu.h +++ b/arch/arm/include/asm/arch-u8500/prcmu.h @@ -64,8 +64,11 @@ #define REQ_MB5 5 -extern int prcmu_i2c_read(u8 reg, u16 slave); -extern int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data); +#define ab8500_read prcmu_i2c_read +#define ab8500_write prcmu_i2c_write + +int prcmu_i2c_read(u8 reg, u16 slave); +int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data); void u8500_prcmu_enable(u32 *reg); void db8500_prcmu_init(void); diff --git a/board/st-ericsson/snowball/snowball.c b/board/st-ericsson/snowball/snowball.c index a70ebb1..7959ab8 100644 --- a/board/st-ericsson/snowball/snowball.c +++ b/board/st-ericsson/snowball/snowball.c @@ -25,6 +25,8 @@ #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/db8500_pincfg.h> +#include <asm/arch/prcmu.h> +#include <asm/arch/hardware.h> #include "db8500_pins.h" @@ -183,3 +185,88 @@ int dram_init(void) return 0; } + +static int raise_ab8500_gpio16(void) +{ + int ret; + + /* selection */ + ret = ab8500_read(AB8500_MISC, AB8500_GPIO_SEL2_REG); + if (ret < 0) + goto out; + + ret |= 0x80; + ret = ab8500_write(AB8500_MISC, AB8500_GPIO_SEL2_REG, ret); + if (ret < 0) + goto out; + + /* direction */ + ret = ab8500_read(AB8500_MISC, AB8500_GPIO_DIR2_REG); + if (ret < 0) + goto out; + + ret |= 0x80; + ret = ab8500_write(AB8500_MISC, AB8500_GPIO_DIR2_REG, ret); + if (ret < 0) + goto out; + + /* out */ + ret = ab8500_read(AB8500_MISC, AB8500_GPIO_OUT2_REG); + if (ret < 0) + goto out; + + ret |= 0x80; + ret = ab8500_write(AB8500_MISC, AB8500_GPIO_OUT2_REG, ret); + +out: + return ret; +} + +static int raise_ab8500_gpio26(void) +{ + int ret; + + /* selection */ + ret = ab8500_read(AB8500_MISC, AB8500_GPIO_DIR4_REG); + if (ret < 0) + goto out; + + ret |= 0x2; + ret = ab8500_write(AB8500_MISC, AB8500_GPIO_DIR4_REG, ret); + if (ret < 0) + goto out; + + /* out */ + ret = ab8500_read(AB8500_MISC, AB8500_GPIO_OUT4_REG); + if (ret < 0) + goto out; + + ret |= 0x2; + ret = ab8500_write(AB8500_MISC, AB8500_GPIO_OUT4_REG, ret); + +out: + return ret; +} + +int board_late_init(void) +{ + /* enable 3V3 for LAN controller */ + if (raise_ab8500_gpio26() >= 0) { + /* Turn on FSMC device */ + writel(0x1, 0x8000f000); + writel(0x1, 0x8000f008); + + /* setup FSMC for LAN controler */ + writel(0x305b, 0x80000000); + + /* run at the highest possible speed */ + writel(0x01010210, 0x80000004); + } else + printf("error: can't raise GPIO26\n"); + + /* enable 3v6 for GBF chip */ + if ((raise_ab8500_gpio16() < 0)) + printf("error: cant' raise GPIO16\n"); + + return 0; +} diff --git a/include/configs/snowball.h b/include/configs/snowball.h index bb8970b..e9de790 100644 --- a/include/configs/snowball.h +++ b/include/configs/snowball.h @@ -32,6 +32,7 @@ #define CONFIG_SYS_ICACHE_OFF #define CONFIG_SYS_DCACHE_OFF #define CONFIG_ARCH_CPU_INIT +#define CONFIG_BOARD_LATE_INIT /* * High Level Configuration Options -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 07/11] u8500: Moving processor-specific functions to cpu area. 2012-07-31 18:59 [U-Boot] [PATCH 00/11] Support for ST-Ericsson snowball board mathieu.poirier at linaro.org ` (5 preceding siblings ...) 2012-07-31 18:59 ` [U-Boot] [PATCH 06/11] snowball: applying power to LAN and GBF controllers mathieu.poirier at linaro.org @ 2012-07-31 18:59 ` mathieu.poirier at linaro.org 2012-08-10 16:08 ` Tom Rini 2012-07-31 18:59 ` [U-Boot] [PATCH 08/11] u8500: Enabling power to MMC device on AB8500 V2 mathieu.poirier at linaro.org ` (4 subsequent siblings) 11 siblings, 1 reply; 24+ messages in thread From: mathieu.poirier at linaro.org @ 2012-07-31 18:59 UTC (permalink / raw) To: u-boot From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org> Functions such as providing power to the MMC device and reading the processor version register should be in the cpu area for access by multiple u8500-based boards. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> --- arch/arm/cpu/armv7/u8500/cpu.c | 86 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-u8500/sys_proto.h | 1 + board/st-ericsson/u8500/u8500_href.c | 75 +----------------------- 3 files changed, 88 insertions(+), 74 deletions(-) diff --git a/arch/arm/cpu/armv7/u8500/cpu.c b/arch/arm/cpu/armv7/u8500/cpu.c index fece201..593199c 100644 --- a/arch/arm/cpu/armv7/u8500/cpu.c +++ b/arch/arm/cpu/armv7/u8500/cpu.c @@ -28,6 +28,30 @@ #include <asm/io.h> #include <asm/arch/prcmu.h> #include <asm/arch/clock.h> +#include <asm/arch/hardware.h> + +#include <asm/arch/hardware.h> + +#define CPUID_DB8500V1 0x411fc091 +#define CPUID_DB8500V2 0x412fc091 +#define ASICID_DB8500V11 0x008500A1 + +static unsigned int read_asicid(void) +{ + unsigned int *address = (void *)U8500_BOOTROM_BASE + + U8500_BOOTROM_ASIC_ID_OFFSET; + return readl(address); +} + +static int cpu_is_u8500v11(void) +{ + return read_asicid() == ASICID_DB8500V11; +} + +static int cpu_is_u8500v2(void) +{ + return read_cpuid() == CPUID_DB8500V2; +} #ifdef CONFIG_ARCH_CPU_INIT /* @@ -41,3 +65,65 @@ int arch_cpu_init(void) return 0; } #endif /* CONFIG_ARCH_CPU_INIT */ + +#ifdef CONFIG_MMC + +#define LDO_VAUX3_MASK 0x3 +#define LDO_VAUX3_ENABLE 0x1 +#define VAUX3_VOLTAGE_2_9V 0xd + +#define AB8500_REGU_CTRL2 0x4 +#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A +#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421 + +int u8500_mmc_power_init(void) +{ + int ret; + int val; + + if (!cpu_is_u8500v11()) + return 0; + + /* + * On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD + * card to work. This is done by enabling the regulators in the AB8500 + * via PRCMU I2C transactions. + * + * This code is derived from the handling of AB8500_LDO_VAUX3 in + * ab8500_ldo_enable() and ab8500_ldo_disable() in Linux. + * + * Turn off and delay is required to have it work across soft reboots. + */ + + ret = prcmu_i2c_read(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG); + if (ret < 0) + goto out; + + val = ret; + + /* Turn off */ + ret = prcmu_i2c_write(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG, + val & ~LDO_VAUX3_MASK); + if (ret < 0) + goto out; + + udelay(10 * 1000); + + /* Set the voltage to 2.9V */ + ret = prcmu_i2c_write(AB8500_REGU_CTRL2, + AB8500_REGU_VRF1VAUX3_SEL_REG, + VAUX3_VOLTAGE_2_9V); + if (ret < 0) + goto out; + + val = val & ~LDO_VAUX3_MASK; + val = val | LDO_VAUX3_ENABLE; + + /* Turn on the supply */ + ret = prcmu_i2c_write(AB8500_REGU_CTRL2, + AB8500_REGU_VRF1VAUX3_REGU_REG, val); + +out: + return ret; +} +#endif /* CONFIG_MMC */ diff --git a/arch/arm/include/asm/arch-u8500/sys_proto.h b/arch/arm/include/asm/arch-u8500/sys_proto.h index bac5e79..a8ef9e5 100644 --- a/arch/arm/include/asm/arch-u8500/sys_proto.h +++ b/arch/arm/include/asm/arch-u8500/sys_proto.h @@ -23,5 +23,6 @@ #define _SYS_PROTO_H_ void gpio_init(void); +int u8500_mmc_power_init(void); #endif /* _SYS_PROTO_H_ */ diff --git a/board/st-ericsson/u8500/u8500_href.c b/board/st-ericsson/u8500/u8500_href.c index fe72684..e75f8b4 100644 --- a/board/st-ericsson/u8500/u8500_href.c +++ b/board/st-ericsson/u8500/u8500_href.c @@ -139,18 +139,6 @@ void show_boot_progress(int progress) } #endif -static unsigned int read_asicid(void) -{ - unsigned int *address = (void *)U8500_BOOTROM_BASE - + U8500_BOOTROM_ASIC_ID_OFFSET; - return readl(address); -} - -int cpu_is_u8500v11(void) -{ - return read_asicid() == 0x008500A1; -} - /* * Miscellaneous platform dependent initialisations */ @@ -227,67 +215,6 @@ unsigned int addr_vall_arr[] = { }; #ifdef CONFIG_BOARD_LATE_INIT -#ifdef CONFIG_MMC - -#define LDO_VAUX3_MASK 0x3 -#define LDO_VAUX3_ENABLE 0x1 -#define VAUX3_VOLTAGE_2_9V 0xd - -#define AB8500_REGU_CTRL2 0x4 -#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A -#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421 - -static int hrefplus_mmc_power_init(void) -{ - int ret; - int val; - - if (!cpu_is_u8500v11()) - return 0; - - /* - * On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD - * card to work. This is done by enabling the regulators in the AB8500 - * via PRCMU I2C transactions. - * - * This code is derived from the handling of AB8500_LDO_VAUX3 in - * ab8500_ldo_enable() and ab8500_ldo_disable() in Linux. - * - * Turn off and delay is required to have it work across soft reboots. - */ - - ret = prcmu_i2c_read(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG); - if (ret < 0) - goto out; - - val = ret; - - /* Turn off */ - ret = prcmu_i2c_write(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG, - val & ~LDO_VAUX3_MASK); - if (ret < 0) - goto out; - - udelay(10 * 1000); - - /* Set the voltage to 2.9V */ - ret = prcmu_i2c_write(AB8500_REGU_CTRL2, - AB8500_REGU_VRF1VAUX3_SEL_REG, - VAUX3_VOLTAGE_2_9V); - if (ret < 0) - goto out; - - val = val & ~LDO_VAUX3_MASK; - val = val | LDO_VAUX3_ENABLE; - - /* Turn on the supply */ - ret = prcmu_i2c_write(AB8500_REGU_CTRL2, - AB8500_REGU_VRF1VAUX3_REGU_REG, val); - -out: - return ret; -} -#endif /* * called after all initialisation were done, but before the generic * mmc_initialize(). @@ -314,7 +241,7 @@ int board_late_init(void) setenv("board_id", "1"); } #ifdef CONFIG_MMC - hrefplus_mmc_power_init(); + u8500_mmc_power_init(); /* * config extended GPIO pins for level shifter and -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 07/11] u8500: Moving processor-specific functions to cpu area. 2012-07-31 18:59 ` [U-Boot] [PATCH 07/11] u8500: Moving processor-specific functions to cpu area mathieu.poirier at linaro.org @ 2012-08-10 16:08 ` Tom Rini 0 siblings, 0 replies; 24+ messages in thread From: Tom Rini @ 2012-08-10 16:08 UTC (permalink / raw) To: u-boot On Tue, Jul 31, 2012 at 12:59:29PM -0600, mathieu.poirier at linaro.org wrote: > From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org> > > Functions such as providing power to the MMC device and reading > the processor version register should be in the cpu area for > access by multiple u8500-based boards. > > Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> > Signed-off-by: John Rigby <john.rigby@linaro.org> [snip] > +static int cpu_is_u8500v2(void) > +{ > + return read_cpuid() == CPUID_DB8500V2; > +} This isn't used yet, so causes a new warning. I'm moving this (and the define) to the next patch, where they are used. With that change and my Signed-off-by, applied to u-boot-staging/trini at ti.com -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20120810/0d46b656/attachment.pgp> ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 08/11] u8500: Enabling power to MMC device on AB8500 V2 2012-07-31 18:59 [U-Boot] [PATCH 00/11] Support for ST-Ericsson snowball board mathieu.poirier at linaro.org ` (6 preceding siblings ...) 2012-07-31 18:59 ` [U-Boot] [PATCH 07/11] u8500: Moving processor-specific functions to cpu area mathieu.poirier at linaro.org @ 2012-07-31 18:59 ` mathieu.poirier at linaro.org 2012-08-10 16:08 ` Tom Rini 2012-07-31 18:59 ` [U-Boot] [PATCH 09/11] u8500: Separating mmc config parameters from driver mathieu.poirier at linaro.org ` (3 subsequent siblings) 11 siblings, 1 reply; 24+ messages in thread From: mathieu.poirier at linaro.org @ 2012-07-31 18:59 UTC (permalink / raw) To: u-boot From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org> Register mapping has changed on power control chip between the first and second revision. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> --- arch/arm/cpu/armv7/u8500/cpu.c | 89 ++++++++++++++++++++-------- arch/arm/include/asm/arch-u8500/hardware.h | 22 ++++++- board/st-ericsson/snowball/snowball.c | 5 ++ 3 files changed, 88 insertions(+), 28 deletions(-) diff --git a/arch/arm/cpu/armv7/u8500/cpu.c b/arch/arm/cpu/armv7/u8500/cpu.c index 593199c..02bb332 100644 --- a/arch/arm/cpu/armv7/u8500/cpu.c +++ b/arch/arm/cpu/armv7/u8500/cpu.c @@ -36,11 +36,19 @@ #define CPUID_DB8500V2 0x412fc091 #define ASICID_DB8500V11 0x008500A1 -static unsigned int read_asicid(void) +static unsigned int read_asicid(void); + +static inline unsigned int read_cpuid(void) { - unsigned int *address = (void *)U8500_BOOTROM_BASE - + U8500_BOOTROM_ASIC_ID_OFFSET; - return readl(address); + unsigned int val; + + /* Main ID register (MIDR) */ + asm("mrc p15, 0, %0, c0, c0, 0" + : "=r" (val) + : + : "cc"); + + return val; } static int cpu_is_u8500v11(void) @@ -53,6 +61,18 @@ static int cpu_is_u8500v2(void) return read_cpuid() == CPUID_DB8500V2; } +static unsigned int read_asicid(void) +{ + unsigned int *address; + + if (cpu_is_u8500v2()) + address = (void *) U8500_ASIC_ID_LOC_V2; + else + address = (void *) U8500_ASIC_ID_LOC_ED_V1; + + return readl(address); +} + #ifdef CONFIG_ARCH_CPU_INIT /* * SOC specific cpu init @@ -68,22 +88,22 @@ int arch_cpu_init(void) #ifdef CONFIG_MMC -#define LDO_VAUX3_MASK 0x3 -#define LDO_VAUX3_ENABLE 0x1 -#define VAUX3_VOLTAGE_2_9V 0xd - -#define AB8500_REGU_CTRL2 0x4 -#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A -#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421 - int u8500_mmc_power_init(void) { int ret; - int val; + int enable, voltage; + int ab8500_revision; - if (!cpu_is_u8500v11()) + if (!cpu_is_u8500v11() && !cpu_is_u8500v2()) return 0; + /* Get AB8500 revision */ + ret = ab8500_read(AB8500_MISC, AB8500_REV_REG); + if (ret < 0) + goto out; + + ab8500_revision = ret; + /* * On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD * card to work. This is done by enabling the regulators in the AB8500 @@ -95,33 +115,50 @@ int u8500_mmc_power_init(void) * Turn off and delay is required to have it work across soft reboots. */ - ret = prcmu_i2c_read(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG); + /* Turn off (read-modify-write) */ + ret = ab8500_read(AB8500_REGU_CTRL2, + AB8500_REGU_VRF1VAUX3_REGU_REG); if (ret < 0) goto out; - val = ret; + enable = ret; /* Turn off */ - ret = prcmu_i2c_write(AB8500_REGU_CTRL2, AB8500_REGU_VRF1VAUX3_REGU_REG, - val & ~LDO_VAUX3_MASK); + ret = ab8500_write(AB8500_REGU_CTRL2, + AB8500_REGU_VRF1VAUX3_REGU_REG, + enable & ~LDO_VAUX3_ENABLE_MASK); if (ret < 0) goto out; udelay(10 * 1000); - /* Set the voltage to 2.9V */ - ret = prcmu_i2c_write(AB8500_REGU_CTRL2, - AB8500_REGU_VRF1VAUX3_SEL_REG, - VAUX3_VOLTAGE_2_9V); + /* Set the voltage to 2.91 V or 2.9 V without overriding VRF1 value */ + ret = ab8500_read(AB8500_REGU_CTRL2, + AB8500_REGU_VRF1VAUX3_SEL_REG); if (ret < 0) goto out; - val = val & ~LDO_VAUX3_MASK; - val = val | LDO_VAUX3_ENABLE; + voltage = ret; + + if (ab8500_revision < 0x20) { + voltage &= ~LDO_VAUX3_SEL_MASK; + voltage |= LDO_VAUX3_SEL_2V9; + } else { + voltage &= ~LDO_VAUX3_V2_SEL_MASK; + voltage |= LDO_VAUX3_V2_SEL_2V91; + } + + ret = ab8500_write(AB8500_REGU_CTRL2, + AB8500_REGU_VRF1VAUX3_SEL_REG, voltage); + if (ret < 0) + goto out; /* Turn on the supply */ - ret = prcmu_i2c_write(AB8500_REGU_CTRL2, - AB8500_REGU_VRF1VAUX3_REGU_REG, val); + enable &= ~LDO_VAUX3_ENABLE_MASK; + enable |= LDO_VAUX3_ENABLE_VAL; + + ret = ab8500_write(AB8500_REGU_CTRL2, + AB8500_REGU_VRF1VAUX3_REGU_REG, enable); out: return ret; diff --git a/arch/arm/include/asm/arch-u8500/hardware.h b/arch/arm/include/asm/arch-u8500/hardware.h index 8044ac3..ee03419 100644 --- a/arch/arm/include/asm/arch-u8500/hardware.h +++ b/arch/arm/include/asm/arch-u8500/hardware.h @@ -77,11 +77,21 @@ #define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000) /* Last page of Boot ROM */ -#define U8500_BOOTROM_BASE 0x9001f000 -#define U8500_BOOTROM_ASIC_ID_OFFSET 0x0ff4 +#define U8500_BOOTROM_BASE 0x90000000 +#define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOTROM_BASE + 0x1FFF4) +#define U8500_ASIC_ID_LOC_V2 (U8500_BOOTROM_BASE + 0x1DBF4) /* AB8500 specifics */ + +/* address bank */ +#define AB8500_REGU_CTRL2 0x0004 #define AB8500_MISC 0x0010 + +/* registers */ +#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A +#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421 +#define AB8500_REV_REG 0x1080 + #define AB8500_GPIO_SEL2_REG 0x1001 #define AB8500_GPIO_DIR2_REG 0x1011 #define AB8500_GPIO_DIR4_REG 0x1013 @@ -89,4 +99,12 @@ #define AB8500_GPIO_OUT2_REG 0x1021 #define AB8500_GPIO_OUT4_REG 0x1023 +#define LDO_VAUX3_ENABLE_MASK 0x3 +#define LDO_VAUX3_ENABLE_VAL 0x1 +#define LDO_VAUX3_SEL_MASK 0xf +#define LDO_VAUX3_SEL_2V9 0xd +#define LDO_VAUX3_V2_SEL_MASK 0x7 +#define LDO_VAUX3_V2_SEL_2V91 0x7 + + #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/board/st-ericsson/snowball/snowball.c b/board/st-ericsson/snowball/snowball.c index 7959ab8..32c343f 100644 --- a/board/st-ericsson/snowball/snowball.c +++ b/board/st-ericsson/snowball/snowball.c @@ -27,6 +27,7 @@ #include <asm/arch/db8500_pincfg.h> #include <asm/arch/prcmu.h> #include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> #include "db8500_pins.h" @@ -268,5 +269,9 @@ int board_late_init(void) if ((raise_ab8500_gpio16() < 0)) printf("error: cant' raise GPIO16\n"); +#ifdef CONFIG_MMC + u8500_mmc_power_init(); +#endif /* CONFIG_MMC */ + return 0; } -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 08/11] u8500: Enabling power to MMC device on AB8500 V2 2012-07-31 18:59 ` [U-Boot] [PATCH 08/11] u8500: Enabling power to MMC device on AB8500 V2 mathieu.poirier at linaro.org @ 2012-08-10 16:08 ` Tom Rini 0 siblings, 0 replies; 24+ messages in thread From: Tom Rini @ 2012-08-10 16:08 UTC (permalink / raw) To: u-boot On Tue, Jul 31, 2012 at 12:59:30PM -0600, mathieu.poirier at linaro.org wrote: > From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org> > > Register mapping has changed on power control chip between > the first and second revision. > > Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> > Signed-off-by: John Rigby <john.rigby@linaro.org> I've added in the cpu_is_u8500v2 from the previous patch in the series here, added my Signed-off-by and merged to u-boot-staging/trini at ti.com, thanks! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20120810/943cb53a/attachment.pgp> ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 09/11] u8500: Separating mmc config parameters from driver 2012-07-31 18:59 [U-Boot] [PATCH 00/11] Support for ST-Ericsson snowball board mathieu.poirier at linaro.org ` (7 preceding siblings ...) 2012-07-31 18:59 ` [U-Boot] [PATCH 08/11] u8500: Enabling power to MMC device on AB8500 V2 mathieu.poirier at linaro.org @ 2012-07-31 18:59 ` mathieu.poirier at linaro.org 2012-08-10 16:08 ` Tom Rini 2012-07-31 18:59 ` [U-Boot] [PATCH 10/11] armv7: Adding cpu specific cache managmenent mathieu.poirier at linaro.org ` (2 subsequent siblings) 11 siblings, 1 reply; 24+ messages in thread From: mathieu.poirier at linaro.org @ 2012-07-31 18:59 UTC (permalink / raw) To: u-boot From: John Rigby <john.rigby@linaro.org> Configuration in vexpress and u8500.v1 is different from what is needed in u8500.v2. As such, card configuration specifics need to reside in the board file rather than the driver. Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> --- board/armltd/vexpress/ca9x4_ct_vxp.c | 21 +++++- board/st-ericsson/snowball/snowball.c | 92 ++++++++++++++++++++++- board/st-ericsson/u8500/u8500_href.c | 22 +++++- drivers/mmc/arm_pl180_mmci.c | 132 +++++++++++++-------------------- drivers/mmc/arm_pl180_mmci.h | 27 ++++++- include/configs/snowball.h | 8 ++ 6 files changed, 214 insertions(+), 88 deletions(-) diff --git a/board/armltd/vexpress/ca9x4_ct_vxp.c b/board/armltd/vexpress/ca9x4_ct_vxp.c index 0b36d12..d5e109e 100644 --- a/board/armltd/vexpress/ca9x4_ct_vxp.c +++ b/board/armltd/vexpress/ca9x4_ct_vxp.c @@ -33,6 +33,8 @@ * MA 02111-1307 USA */ #include <common.h> +#include <malloc.h> +#include <errno.h> #include <netdev.h> #include <asm/io.h> #include <asm/arch/systimer.h> @@ -90,8 +92,25 @@ int board_eth_init(bd_t *bis) int cpu_mmc_init(bd_t *bis) { int rc = 0; + (void) bis; #ifdef CONFIG_ARM_PL180_MMCI - rc = arm_pl180_mmci_init(); + struct pl180_mmc_host *host; + + host = malloc(sizeof(struct pl180_mmc_host)); + if (!host) + return -ENOMEM; + memset(host, 0, sizeof(*host)); + + strcpy(host->name, "MMC"); + host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE; + host->pwr_init = INIT_PWR; + host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN; + host->voltages = VOLTAGE_WINDOW_MMC; + host->caps = 0; + host->clock_in = ARM_MCLK; + host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1)); + host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ; + rc = arm_pl180_mmci_init(host); #endif return rc; } diff --git a/board/st-ericsson/snowball/snowball.c b/board/st-ericsson/snowball/snowball.c index 32c343f..7a52de6 100644 --- a/board/st-ericsson/snowball/snowball.c +++ b/board/st-ericsson/snowball/snowball.c @@ -29,6 +29,9 @@ #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> +#ifdef CONFIG_MMC +#include "../../../drivers/mmc/arm_pl180_mmci.h" +#endif #include "db8500_pins.h" /* @@ -269,9 +272,96 @@ int board_late_init(void) if ((raise_ab8500_gpio16() < 0)) printf("error: cant' raise GPIO16\n"); + return 0; +} + #ifdef CONFIG_MMC +/* + * emmc_host_init - initialize the emmc controller. + * Configure GPIO settings, set initial clock and power for emmc slot. + * Initialize mmc struct and register with mmc framework. + */ +static int emmc_host_init(void) +{ + struct pl180_mmc_host *host; + + host = malloc(sizeof(struct pl180_mmc_host)); + if (!host) + return -ENOMEM; + memset(host, 0, sizeof(*host)); + + host->base = (struct sdi_registers *)CFG_EMMC_BASE; + host->pwr_init = SDI_PWR_OPD | SDI_PWR_PWRCTRL_ON; + host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V2 | + SDI_CLKCR_CLKEN | SDI_CLKCR_HWFC_EN; + strcpy(host->name, "EMMC"); + host->caps = MMC_MODE_8BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz; + host->voltages = VOLTAGE_WINDOW_MMC; + host->clock_min = ARM_MCLK / (2 + SDI_CLKCR_CLKDIV_INIT_V2); + host->clock_max = ARM_MCLK / 2; + host->clock_in = ARM_MCLK; + host->version2 = 1; + + return arm_pl180_mmci_init(host); +} + +/* + * mmc_host_init - initialize the external mmc controller. + * Configure GPIO settings, set initial clock and power for mmc slot. + * Initialize mmc struct and register with mmc framework. + */ +static int mmc_host_init(void) +{ + struct pl180_mmc_host *host; + u32 sdi_u32; + + host = malloc(sizeof(struct pl180_mmc_host)); + if (!host) + return -ENOMEM; + memset(host, 0, sizeof(*host)); + + host->base = (struct sdi_registers *)CFG_MMC_BASE; + sdi_u32 = 0xBF; + writel(sdi_u32, &host->base->power); + host->pwr_init = 0xBF; + host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V2 | + SDI_CLKCR_CLKEN | SDI_CLKCR_HWFC_EN; + strcpy(host->name, "MMC"); + host->caps = MMC_MODE_8BIT; + host->b_max = 0; + host->voltages = VOLTAGE_WINDOW_SD; + host->clock_min = ARM_MCLK / (2 + SDI_CLKCR_CLKDIV_INIT_V2); + host->clock_max = ARM_MCLK / 2; + host->clock_in = ARM_MCLK; + host->version2 = 1; + + return arm_pl180_mmci_init(host); +} + +/* + * board_mmc_init - initialize all the mmc/sd host controllers. + * Called by generic mmc framework. + */ +int board_mmc_init(bd_t *bis) +{ + int error; + + (void) bis; + + error = emmc_host_init(); + if (error) { + printf("emmc_host_init() %d\n", error); + return -1; + } + u8500_mmc_power_init(); -#endif /* CONFIG_MMC */ + + error = mmc_host_init(); + if (error) { + printf("mmc_host_init() %d\n", error); + return -1; + } return 0; } +#endif /* CONFIG_MMC */ diff --git a/board/st-ericsson/u8500/u8500_href.c b/board/st-ericsson/u8500/u8500_href.c index e75f8b4..f06120c 100644 --- a/board/st-ericsson/u8500/u8500_href.c +++ b/board/st-ericsson/u8500/u8500_href.c @@ -18,6 +18,7 @@ #include <config.h> #include <common.h> +#include <malloc.h> #include <i2c.h> #include <asm/types.h> #include <asm/io.h> @@ -375,12 +376,27 @@ static int u8500_mmci_board_init(void) int board_mmc_init(bd_t *bd) { + struct pl180_mmc_host *host; + if (u8500_mmci_board_init()) return -ENODEV; - if (arm_pl180_mmci_init()) - return -ENODEV; - return 0; + host = malloc(sizeof(struct pl180_mmc_host)); + if (!host) + return -ENOMEM; + memset(host, 0, sizeof(*host)); + + strcpy(host->name, "MMC"); + host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE; + host->pwr_init = INIT_PWR; + host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN; + host->voltages = VOLTAGE_WINDOW_MMC; + host->caps = 0; + host->clock_in = ARM_MCLK; + host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1)); + host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ; + + return arm_pl180_mmci_init(host); } #endif diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c index 09d443e..2966520 100644 --- a/drivers/mmc/arm_pl180_mmci.c +++ b/drivers/mmc/arm_pl180_mmci.c @@ -32,14 +32,10 @@ #include "arm_pl180_mmci.h" #include <malloc.h> -struct mmc_host { - struct sdi_registers *base; -}; - static int wait_for_command_end(struct mmc *dev, struct mmc_cmd *cmd) { u32 hoststatus, statusmask; - struct mmc_host *host = dev->priv; + struct pl180_mmc_host *host = dev->priv; statusmask = SDI_STA_CTIMEOUT | SDI_STA_CCRCFAIL; if ((cmd->resp_type & MMC_RSP_PRESENT)) @@ -53,8 +49,8 @@ static int wait_for_command_end(struct mmc *dev, struct mmc_cmd *cmd) writel(statusmask, &host->base->status_clear); if (hoststatus & SDI_STA_CTIMEOUT) { - printf("CMD%d time out\n", cmd->cmdidx); - return -ETIMEDOUT; + debug("CMD%d time out\n", cmd->cmdidx); + return TIMEOUT; } else if ((hoststatus & SDI_STA_CCRCFAIL) && (cmd->flags & MMC_RSP_CRC)) { printf("CMD%d CRC error\n", cmd->cmdidx); @@ -80,7 +76,8 @@ static int do_command(struct mmc *dev, struct mmc_cmd *cmd) { int result; u32 sdi_cmd = 0; - struct mmc_host *host = dev->priv; + struct pl180_mmc_host *host = dev->priv; + u32 lap = 0; sdi_cmd = ((cmd->cmdidx & SDI_CMD_CMDINDEX_MASK) | SDI_CMD_CPSMEN); @@ -112,7 +109,7 @@ static int read_bytes(struct mmc *dev, u32 *dest, u32 blkcount, u32 blksize) { u32 *tempbuff = dest; u64 xfercount = blkcount * blksize; - struct mmc_host *host = dev->priv; + struct pl180_mmc_host *host = dev->priv; u32 status, status_err; debug("read_bytes: blkcount=%u blksize=%u\n", blkcount, blksize); @@ -168,7 +165,7 @@ static int write_bytes(struct mmc *dev, u32 *src, u32 blkcount, u32 blksize) u32 *tempbuff = src; int i; u64 xfercount = blkcount * blksize; - struct mmc_host *host = dev->priv; + struct pl180_mmc_host *host = dev->priv; u32 status, status_err; debug("write_bytes: blkcount=%u blksize=%u\n", blkcount, blksize); @@ -227,14 +224,19 @@ static int do_data_transfer(struct mmc *dev, struct mmc_data *data) { int error = -ETIMEDOUT; - struct mmc_host *host = dev->priv; + struct pl180_mmc_host *host = dev->priv; u32 blksz = 0; u32 data_ctrl = 0; u32 data_len = (u32) (data->blocks * data->blocksize); - blksz = (ffs(data->blocksize) - 1); - data_ctrl |= ((blksz << 4) & SDI_DCTRL_DBLKSIZE_MASK); - data_ctrl |= SDI_DCTRL_DTEN; + if (!host->version2) { + blksz = (ffs(data->blocksize) - 1); + data_ctrl |= ((blksz << 4) & SDI_DCTRL_DBLKSIZE_MASK); + } else { + blksz = data->blocksize; + data_ctrl |= (blksz << SDI_DCTRL_DBLOCKSIZE_V2_SHIFT); + } + data_ctrl |= SDI_DCTRL_DTEN | SDI_DCTRL_BUSYMODE; writel(SDI_DTIMER_DEFAULT, &host->base->datatimer); writel(data_len, &host->base->datalength); @@ -257,7 +259,7 @@ static int do_data_transfer(struct mmc *dev, writel(data_ctrl, &host->base->datactrl); error = write_bytes(dev, (u32 *)data->src, (u32)data->blocks, - (u32)data->blocksize); + (u32)data->blocksize); } return error; @@ -280,17 +282,16 @@ static int host_request(struct mmc *dev, /* MMC uses open drain drivers in the enumeration phase */ static int mmc_host_reset(struct mmc *dev) { - struct mmc_host *host = dev->priv; - u32 sdi_u32 = SDI_PWR_OPD | SDI_PWR_PWRCTRL_ON; + struct pl180_mmc_host *host = dev->priv; - writel(sdi_u32, &host->base->power); + writel(host->pwr_init, &host->base->power); return 0; } static void host_set_ios(struct mmc *dev) { - struct mmc_host *host = dev->priv; + struct pl180_mmc_host *host = dev->priv; u32 sdi_clkcr; sdi_clkcr = readl(&host->base->clock); @@ -298,15 +299,26 @@ static void host_set_ios(struct mmc *dev) /* Ramp up the clock rate */ if (dev->clock) { u32 clkdiv = 0; + u32 tmp_clock; - if (dev->clock >= dev->f_max) + if (dev->clock >= dev->f_max) { + clkdiv = 0; dev->clock = dev->f_max; + } else { + clkdiv = (host->clock_in / dev->clock) - 2; + } - clkdiv = ((ARM_MCLK / dev->clock) / 2) - 1; + tmp_clock = host->clock_in / (clkdiv + 2); + while (tmp_clock > dev->clock) { + clkdiv++; + tmp_clock = host->clock_in / (clkdiv + 2); + } if (clkdiv > SDI_CLKCR_CLKDIV_MASK) clkdiv = SDI_CLKCR_CLKDIV_MASK; + tmp_clock = host->clock_in / (clkdiv + 2); + dev->clock = tmp_clock; sdi_clkcr &= ~(SDI_CLKCR_CLKDIV_MASK); sdi_clkcr |= clkdiv; } @@ -322,8 +334,11 @@ static void host_set_ios(struct mmc *dev) case 4: buswidth |= SDI_CLKCR_WIDBUS_4; break; + case 8: + buswidth |= SDI_CLKCR_WIDBUS_8; + break; default: - printf("Invalid bus width\n"); + printf("Invalid bus width: %d\n", dev->bus_width); break; } sdi_clkcr &= ~(SDI_CLKCR_WIDBUS_MASK); @@ -334,83 +349,40 @@ static void host_set_ios(struct mmc *dev) udelay(CLK_CHANGE_DELAY); } -struct mmc *alloc_mmc_struct(void) -{ - struct mmc_host *host = NULL; - struct mmc *mmc_device = NULL; - - host = malloc(sizeof(struct mmc_host)); - if (!host) - return NULL; - - mmc_device = malloc(sizeof(struct mmc)); - if (!mmc_device) - goto err; - - mmc_device->priv = host; - return mmc_device; - -err: - free(host); - return NULL; -} - /* * mmc_host_init - initialize the mmc controller. * Set initial clock and power for mmc slot. * Initialize mmc struct and register with mmc framework. */ -static int arm_pl180_mmci_host_init(struct mmc *dev) +int arm_pl180_mmci_init(struct pl180_mmc_host *host) { - struct mmc_host *host = dev->priv; + struct mmc *dev; u32 sdi_u32; - host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE; + dev = malloc(sizeof(struct mmc)); + if (!dev) + return -ENOMEM; - /* Initially set power-on, full voltage & MMCI read */ - sdi_u32 = INIT_PWR; - writel(sdi_u32, &host->base->power); + memset(dev, 0, sizeof(struct mmc)); + dev->priv = host; - /* setting clk freq 505KHz */ - sdi_u32 = SDI_CLKCR_CLKDIV_INIT | SDI_CLKCR_CLKEN; - writel(sdi_u32, &host->base->clock); + writel(host->pwr_init, &host->base->power); + writel(host->clkdiv_init, &host->base->clock); udelay(CLK_CHANGE_DELAY); /* Disable mmc interrupts */ sdi_u32 = readl(&host->base->mask0) & ~SDI_MASK0_MASK; writel(sdi_u32, &host->base->mask0); - - sprintf(dev->name, "MMC"); - dev->clock = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT + 1)); + strncpy(dev->name, host->name, sizeof(dev->name)); dev->send_cmd = host_request; dev->set_ios = host_set_ios; dev->init = mmc_host_reset; dev->getcd = NULL; - dev->host_caps = 0; - dev->voltages = VOLTAGE_WINDOW_MMC; - dev->f_min = dev->clock; - dev->f_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ; - - return 0; -} - -int arm_pl180_mmci_init(void) -{ - int error; - struct mmc *dev; - - dev = alloc_mmc_struct(); - if (!dev) - return -1; - - error = arm_pl180_mmci_host_init(dev); - if (error) { - printf("mmci_host_init error - %d\n", error); - return -1; - } - - dev->b_max = 0; - + dev->host_caps = host->caps; + dev->voltages = host->voltages; + dev->f_min = host->clock_min; + dev->f_max = host->clock_max; + dev->b_max = host->b_max; mmc_register(dev); debug("registered mmc interface number is:%d\n", dev->block_dev.dev); diff --git a/drivers/mmc/arm_pl180_mmci.h b/drivers/mmc/arm_pl180_mmci.h index 42fbe3e..06709ed 100644 --- a/drivers/mmc/arm_pl180_mmci.h +++ b/drivers/mmc/arm_pl180_mmci.h @@ -26,8 +26,6 @@ #ifndef __ARM_PL180_MMCI_H__ #define __ARM_PL180_MMCI_H__ -int arm_pl180_mmci_init(void); - #define COMMAND_REG_DELAY 300 #define DATA_REG_DELAY 1000 #define CLK_CHANGE_DELAY 2000 @@ -59,8 +57,13 @@ int arm_pl180_mmci_init(void); #define SDI_CLKCR_WIDBUS_MASK 0x00001800 #define SDI_CLKCR_WIDBUS_1 0x00000000 #define SDI_CLKCR_WIDBUS_4 0x00000800 +/* V2 only */ +#define SDI_CLKCR_WIDBUS_8 0x00001000 +#define SDI_CLKCR_NEDGE 0x00002000 +#define SDI_CLKCR_HWFC_EN 0x00004000 -#define SDI_CLKCR_CLKDIV_INIT 0x000000C6 /* MCLK/(2*(0xC6+1)) => 505KHz */ +#define SDI_CLKCR_CLKDIV_INIT_V1 0x000000C6 /* MCLK/(2*(0xC6+1)) => 505KHz */ +#define SDI_CLKCR_CLKDIV_INIT_V2 0x000000FD /* SDI command register bits */ #define SDI_CMD_CMDINDEX_MASK 0x000000FF @@ -144,6 +147,8 @@ int arm_pl180_mmci_init(void); #define SDI_DCTRL_DBOOTMODEEN 0x00002000 #define SDI_DCTRL_BUSYMODE 0x00004000 #define SDI_DCTRL_DDR_MODE 0x00008000 +#define SDI_DCTRL_DBLOCKSIZE_V2_MASK 0x7fff0000 +#define SDI_DCTRL_DBLOCKSIZE_V2_SHIFT 16 #define SDI_FIFO_BURST_SIZE 8 @@ -180,4 +185,20 @@ struct sdi_registers { u32 pcell_id3; /* 0xFFC*/ }; +struct pl180_mmc_host { + struct sdi_registers *base; + char name[32]; + unsigned int b_max; + unsigned int voltages; + unsigned int caps; + unsigned int clock_in; + unsigned int clock_min; + unsigned int clock_max; + unsigned int clkdiv_init; + unsigned int pwr_init; + int version2; +}; + +int arm_pl180_mmci_init(struct pl180_mmc_host *); + #endif diff --git a/include/configs/snowball.h b/include/configs/snowball.h index e9de790..4d25f33 100644 --- a/include/configs/snowball.h +++ b/include/configs/snowball.h @@ -231,6 +231,14 @@ #endif /* + * MMC related configs + */ +#define CONFIG_ARM_PL180_MMCI +#define MMC_BLOCK_SIZE 512 +#define CFG_EMMC_BASE 0x80114000 +#define CFG_MMC_BASE 0x80126000 + +/* * FLASH and environment organization */ #define CONFIG_SYS_NO_FLASH -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 09/11] u8500: Separating mmc config parameters from driver 2012-07-31 18:59 ` [U-Boot] [PATCH 09/11] u8500: Separating mmc config parameters from driver mathieu.poirier at linaro.org @ 2012-08-10 16:08 ` Tom Rini 0 siblings, 0 replies; 24+ messages in thread From: Tom Rini @ 2012-08-10 16:08 UTC (permalink / raw) To: u-boot On Tue, Jul 31, 2012 at 12:59:31PM -0600, mathieu.poirier at linaro.org wrote: > From: John Rigby <john.rigby@linaro.org> > > Configuration in vexpress and u8500.v1 is different from what > is needed in u8500.v2. As such, card configuration specifics need > to reside in the board file rather than the driver. > > Signed-off-by: John Rigby <john.rigby@linaro.org> > Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> [snip] > diff --git a/board/st-ericsson/snowball/snowball.c b/board/st-ericsson/snowball/snowball.c > index 32c343f..7a52de6 100644 > --- a/board/st-ericsson/snowball/snowball.c > +++ b/board/st-ericsson/snowball/snowball.c [snip] > @@ -80,7 +76,8 @@ static int do_command(struct mmc *dev, struct mmc_cmd *cmd) > { > int result; > u32 sdi_cmd = 0; > - struct mmc_host *host = dev->priv; > + struct pl180_mmc_host *host = dev->priv; > + u32 lap = 0; lap is unused. Removing. This patch has been applied to u-boot-staging/trini at ti.com with the above change and a Signed-off-by from me. -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20120810/cecc63fb/attachment.pgp> ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 10/11] armv7: Adding cpu specific cache managmenent 2012-07-31 18:59 [U-Boot] [PATCH 00/11] Support for ST-Ericsson snowball board mathieu.poirier at linaro.org ` (8 preceding siblings ...) 2012-07-31 18:59 ` [U-Boot] [PATCH 09/11] u8500: Separating mmc config parameters from driver mathieu.poirier at linaro.org @ 2012-07-31 18:59 ` mathieu.poirier at linaro.org 2012-07-31 18:59 ` [U-Boot] [PATCH 11/11] snowball: Adding board specific cache cleanup routine mathieu.poirier at linaro.org 2012-08-10 16:08 ` [U-Boot] [PATCH 00/11] Support for ST-Ericsson snowball board Tom Rini 11 siblings, 0 replies; 24+ messages in thread From: mathieu.poirier at linaro.org @ 2012-07-31 18:59 UTC (permalink / raw) To: u-boot From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org> Some CPU (i.e u8500) need more cache management before launching the Linux kernel. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> --- arch/arm/cpu/armv7/cpu.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index c6fa8ef..f01989f 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -36,6 +36,7 @@ #include <asm/system.h> #include <asm/cache.h> #include <asm/armv7.h> +#include <linux/compiler.h> void save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3) { @@ -44,6 +45,8 @@ void save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3) void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) __attribute__((weak, alias("save_boot_params_default"))); +void __weak cpu_cache_initialization(void){} + int cleanup_before_linux(void) { /* @@ -81,5 +84,10 @@ int cleanup_before_linux(void) */ invalidate_dcache_all(); + /* + * Some CPU need more cache attention before starting the kernel. + */ + cpu_cache_initialization(); + return 0; } -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 11/11] snowball: Adding board specific cache cleanup routine 2012-07-31 18:59 [U-Boot] [PATCH 00/11] Support for ST-Ericsson snowball board mathieu.poirier at linaro.org ` (9 preceding siblings ...) 2012-07-31 18:59 ` [U-Boot] [PATCH 10/11] armv7: Adding cpu specific cache managmenent mathieu.poirier at linaro.org @ 2012-07-31 18:59 ` mathieu.poirier at linaro.org 2012-08-10 16:08 ` [U-Boot] [PATCH 00/11] Support for ST-Ericsson snowball board Tom Rini 11 siblings, 0 replies; 24+ messages in thread From: mathieu.poirier at linaro.org @ 2012-07-31 18:59 UTC (permalink / raw) To: u-boot From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org> Following ARM's reference manuel for initializing the cache - the kernel won't boot otherwise. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> --- arch/arm/cpu/armv7/u8500/cpu.c | 26 ++++++++++++++++++++++++++ 1 files changed, 26 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/u8500/cpu.c b/arch/arm/cpu/armv7/u8500/cpu.c index 02bb332..6f95c30 100644 --- a/arch/arm/cpu/armv7/u8500/cpu.c +++ b/arch/arm/cpu/armv7/u8500/cpu.c @@ -36,6 +36,14 @@ #define CPUID_DB8500V2 0x412fc091 #define ASICID_DB8500V11 0x008500A1 +#define CACHE_CONTR_BASE 0xA0412000 +/* Cache controller register offsets + * as found in ARM's technical reference manual + */ +#define CACHE_INVAL_BY_WAY (CACHE_CONTR_BASE + 0x77C) +#define CACHE_LOCKDOWN_BY_D (CACHE_CONTR_BASE + 0X900) +#define CACHE_LOCKDOWN_BY_I (CACHE_CONTR_BASE + 0X904) + static unsigned int read_asicid(void); static inline unsigned int read_cpuid(void) @@ -73,6 +81,24 @@ static unsigned int read_asicid(void) return readl(address); } +void cpu_cache_initialization(void) +{ + unsigned int value; + /* invalidate all cache entries */ + writel(0xFFFF, CACHE_INVAL_BY_WAY); + + /* ways are set to '0' when they are totally + * cleaned and invalidated + */ + do { + value = readl(CACHE_INVAL_BY_WAY); + } while (value & 0xFF); + + /* Invalidate register 9 D and I lockdown */ + writel(0xFF, CACHE_LOCKDOWN_BY_D); + writel(0xFF, CACHE_LOCKDOWN_BY_I); +} + #ifdef CONFIG_ARCH_CPU_INIT /* * SOC specific cpu init -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 00/11] Support for ST-Ericsson snowball board 2012-07-31 18:59 [U-Boot] [PATCH 00/11] Support for ST-Ericsson snowball board mathieu.poirier at linaro.org ` (10 preceding siblings ...) 2012-07-31 18:59 ` [U-Boot] [PATCH 11/11] snowball: Adding board specific cache cleanup routine mathieu.poirier at linaro.org @ 2012-08-10 16:08 ` Tom Rini 11 siblings, 0 replies; 24+ messages in thread From: Tom Rini @ 2012-08-10 16:08 UTC (permalink / raw) To: u-boot On Tue, Jul 31, 2012 at 12:59:22PM -0600, mathieu.poirier at linaro.org wrote: > From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org> > > This set adds support for the ST-Ericsson u8500 based > snowball board. Doing so it moves u8500-href code around > to allow for code reuse between boards. > > It was sent out during the 12.07 cycle but never received > an official ACK. > > John Rigby (1): > u8500: Separating mmc config parameters from driver > > Mathieu J. Poirier (10): > snowball: Add support for ux500 based snowball board > u8500: Moving prcmu to cpu directory > snowball: Adding architecture dependent initialisation > snowball: Adding CPU clock initialisation > snowball: Moving to ux500.v2 addess scheme for PRCMU access > snowball: applying power to LAN and GBF controllers > u8500: Moving processor-specific functions to cpu area. > u8500: Enabling power to MMC device on AB8500 V2 > armv7: Adding cpu specific cache managmenent > snowball: Adding board specific cache cleanup routine > > MAINTAINERS | 4 + > arch/arm/cpu/armv7/cpu.c | 8 + > arch/arm/cpu/armv7/u8500/Makefile | 2 +- > arch/arm/cpu/armv7/u8500/clock.c | 34 + > arch/arm/cpu/armv7/u8500/cpu.c | 192 ++++++ > arch/arm/cpu/armv7/u8500/prcmu.c | 229 +++++++ > arch/arm/include/asm/arch-u8500/clock.h | 5 +- > arch/arm/include/asm/arch-u8500/db8500_gpio.h | 42 ++ > arch/arm/include/asm/arch-u8500/db8500_pincfg.h | 170 +++++ > arch/arm/include/asm/arch-u8500/hardware.h | 33 +- > arch/arm/include/asm/arch-u8500/prcmu.h | 76 +++ > arch/arm/include/asm/arch-u8500/sys_proto.h | 1 + > board/armltd/vexpress/ca9x4_ct_vxp.c | 21 +- > board/st-ericsson/snowball/Makefile | 51 ++ > board/st-ericsson/snowball/db8500_pins.h | 745 +++++++++++++++++++++++ > board/st-ericsson/snowball/snowball.c | 367 +++++++++++ > board/st-ericsson/u8500/Makefile | 2 +- > board/st-ericsson/u8500/prcmu-fw.h | 55 -- > board/st-ericsson/u8500/prcmu.c | 165 ----- > board/st-ericsson/u8500/u8500_href.c | 99 +--- > boards.cfg | 1 + > drivers/gpio/Makefile | 1 + > drivers/gpio/db8500_gpio.c | 225 +++++++ > drivers/mmc/arm_pl180_mmci.c | 132 ++--- > drivers/mmc/arm_pl180_mmci.h | 27 +- > drivers/serial/serial_pl01x.c | 2 + > include/configs/snowball.h | 268 ++++++++ > 27 files changed, 2566 insertions(+), 391 deletions(-) > create mode 100644 arch/arm/cpu/armv7/u8500/cpu.c > create mode 100644 arch/arm/cpu/armv7/u8500/prcmu.c > create mode 100644 arch/arm/include/asm/arch-u8500/db8500_gpio.h > create mode 100644 arch/arm/include/asm/arch-u8500/db8500_pincfg.h > create mode 100644 arch/arm/include/asm/arch-u8500/prcmu.h > create mode 100644 board/st-ericsson/snowball/Makefile > create mode 100644 board/st-ericsson/snowball/db8500_pins.h > create mode 100644 board/st-ericsson/snowball/snowball.c > delete mode 100644 board/st-ericsson/u8500/prcmu-fw.h > delete mode 100644 board/st-ericsson/u8500/prcmu.c > create mode 100644 drivers/gpio/db8500_gpio.c > create mode 100644 include/configs/snowball.h With a few very minor changes that I've sent to the list, I've applied this to u-boot-staging/trini at ti.com, thanks for your patience! -- Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20120810/fe882ba2/attachment.pgp> ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 00/11] support for ST-Ericsson snowball board @ 2012-06-18 16:35 mathieu.poirier at linaro.org 2012-06-18 16:35 ` [U-Boot] [PATCH 01/11] snowball: Add support for ux500 based " mathieu.poirier at linaro.org 0 siblings, 1 reply; 24+ messages in thread From: mathieu.poirier at linaro.org @ 2012-06-18 16:35 UTC (permalink / raw) To: u-boot From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org> This set adds support for the ST-Ericsson u8500 based snowball board. Doing so it moves u8500-href code around to allow for code reuse. John Rigby (1): u8500: Separating mmc config parameters from driver Mathieu J. Poirier (10): snowball: Add support for ux500 based snowball board u8500: Moving prcmu to cpu directory snowball: Adding architecture dependent initialisation snowball: Adding CPU clock initialisation snowball: Moving to ux500.v2 addess scheme for PRCMU access snowball: applying power to LAN and GBF controllers u8500: Moving processor-specific functions to cpu area. u8500: Enabling power to MMC device on AB8500 V2 armv7: Adding cpu specific cache managmenent snowball: Adding board specific cache cleanup routine arch/arm/cpu/armv7/cpu.c | 9 + arch/arm/cpu/armv7/u8500/Makefile | 2 +- arch/arm/cpu/armv7/u8500/clock.c | 34 + arch/arm/cpu/armv7/u8500/cpu.c | 175 ++++++ arch/arm/cpu/armv7/u8500/prcmu.c | 229 +++++++ arch/arm/include/asm/arch-u8500/clock.h | 5 +- arch/arm/include/asm/arch-u8500/db8500_gpio.h | 42 ++ arch/arm/include/asm/arch-u8500/db8500_pincfg.h | 172 ++++++ arch/arm/include/asm/arch-u8500/hardware.h | 33 +- arch/arm/include/asm/arch-u8500/prcmu.h | 76 +++ arch/arm/include/asm/arch-u8500/sys_proto.h | 1 + board/armltd/vexpress/ca9x4_ct_vxp.c | 21 +- board/st-ericsson/snowball/Makefile | 51 ++ board/st-ericsson/snowball/db8500_pins.h | 745 +++++++++++++++++++++++ board/st-ericsson/snowball/snowball.c | 367 +++++++++++ board/st-ericsson/u8500/Makefile | 2 +- board/st-ericsson/u8500/prcmu-fw.h | 55 -- board/st-ericsson/u8500/prcmu.c | 165 ----- board/st-ericsson/u8500/u8500_href.c | 99 +--- boards.cfg | 1 + drivers/gpio/Makefile | 1 + drivers/gpio/db8500_gpio.c | 225 +++++++ drivers/mmc/arm_pl180_mmci.c | 132 ++--- drivers/mmc/arm_pl180_mmci.h | 27 +- drivers/serial/serial_pl01x.c | 2 + include/configs/snowball.h | 283 +++++++++ 26 files changed, 2563 insertions(+), 391 deletions(-) create mode 100644 arch/arm/cpu/armv7/u8500/cpu.c create mode 100644 arch/arm/cpu/armv7/u8500/prcmu.c create mode 100644 arch/arm/include/asm/arch-u8500/db8500_gpio.h create mode 100644 arch/arm/include/asm/arch-u8500/db8500_pincfg.h create mode 100644 arch/arm/include/asm/arch-u8500/prcmu.h create mode 100644 board/st-ericsson/snowball/Makefile create mode 100644 board/st-ericsson/snowball/db8500_pins.h create mode 100644 board/st-ericsson/snowball/snowball.c delete mode 100644 board/st-ericsson/u8500/prcmu-fw.h delete mode 100644 board/st-ericsson/u8500/prcmu.c create mode 100644 drivers/gpio/db8500_gpio.c create mode 100644 include/configs/snowball.h -- 1.7.5.4 ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 01/11] snowball: Add support for ux500 based snowball board 2012-06-18 16:35 [U-Boot] [PATCH 00/11] support " mathieu.poirier at linaro.org @ 2012-06-18 16:35 ` mathieu.poirier at linaro.org 2012-06-18 17:59 ` Tom Rini 0 siblings, 1 reply; 24+ messages in thread From: mathieu.poirier at linaro.org @ 2012-06-18 16:35 UTC (permalink / raw) To: u-boot From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> --- arch/arm/include/asm/arch-u8500/db8500_gpio.h | 42 ++ arch/arm/include/asm/arch-u8500/db8500_pincfg.h | 172 ++++++ board/st-ericsson/snowball/Makefile | 51 ++ board/st-ericsson/snowball/db8500_pins.h | 745 +++++++++++++++++++++++ board/st-ericsson/snowball/snowball.c | 185 ++++++ boards.cfg | 1 + drivers/gpio/Makefile | 1 + drivers/gpio/db8500_gpio.c | 225 +++++++ drivers/serial/serial_pl01x.c | 2 + include/configs/snowball.h | 274 +++++++++ 10 files changed, 1698 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-u8500/db8500_gpio.h b/arch/arm/include/asm/arch-u8500/db8500_gpio.h new file mode 100644 index 0000000..7c85a89 --- /dev/null +++ b/arch/arm/include/asm/arch-u8500/db8500_gpio.h @@ -0,0 +1,42 @@ +/* + * Structures and registers for GPIO access in the Nomadik SoC + * + * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. + * The purpose is that GPIO config found in kernel should work by simply + * copy-paste it to U-boot. + * + * Ported to U-boot by: + * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com> + * Copyright (C) 2008 STMicroelectronics + * Author: Prafulla WADASKAR <prafulla.wadaskar@st.com> + * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DB8500_GPIO_H__ +#define __DB8500_GPIO_H__ + +/* Alternate functions: function C is set in hw by setting both A and B */ +enum db8500_gpio_alt { + DB8500_GPIO_ALT_GPIO = 0, + DB8500_GPIO_ALT_A = 1, + DB8500_GPIO_ALT_B = 2, + DB8500_GPIO_ALT_C = (DB8500_GPIO_ALT_A | DB8500_GPIO_ALT_B) +}; + +enum db8500_gpio_pull { + DB8500_GPIO_PULL_NONE, + DB8500_GPIO_PULL_UP, + DB8500_GPIO_PULL_DOWN +}; + +void db8500_gpio_set_pull(unsigned gpio, enum db8500_gpio_pull pull); +void db8500_gpio_make_input(unsigned gpio); +int db8500_gpio_get_input(unsigned gpio); +void db8500_gpio_make_output(unsigned gpio, int val); +void db8500_gpio_set_output(unsigned gpio, int val); + +#endif /* __DB8500_GPIO_H__ */ diff --git a/arch/arm/include/asm/arch-u8500/db8500_pincfg.h b/arch/arm/include/asm/arch-u8500/db8500_pincfg.h new file mode 100644 index 0000000..137377d --- /dev/null +++ b/arch/arm/include/asm/arch-u8500/db8500_pincfg.h @@ -0,0 +1,172 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. + * The purpose is that GPIO config found in kernel should work by simply + * copy-paste it to U-boot. Ported 2010 to U-boot by: + * Author: Joakim Axelsson <joakim.axelsson AT stericsson.com> + * + * License terms: GNU General Public License, version 2 + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson + * + * + * Based on arch/arm/mach-pxa/include/mach/mfp.h: + * Copyright (C) 2007 Marvell International Ltd. + * eric miao <eric.miao@marvell.com> + */ + +#ifndef __DB8500_PINCFG_H +#define __DB8500_PINCFG_H + +#include "db8500_gpio.h" + +/* + * U-boot info: + * SLPM (sleep mode) config will be ignored by U-boot but it is still + * possible to configure it in order to keep cut-n-paste compability + * with Linux kernel config. + * + * pin configurations are represented by 32-bit integers: + * + * bit 0.. 8 - Pin Number (512 Pins Maximum) + * bit 9..10 - Alternate Function Selection + * bit 11..12 - Pull up/down state + * bit 13 - Sleep mode behaviour (not used in U-boot) + * bit 14 - Direction + * bit 15 - Value (if output) + * bit 16..18 - SLPM pull up/down state (not used in U-boot) + * bit 19..20 - SLPM direction (not used in U-boot) + * bit 21..22 - SLPM Value (if output) (not used in U-boot) + * + * to facilitate the definition, the following macros are provided + * + * PIN_CFG_DEFAULT - default config (0): + * pull up/down = disabled + * sleep mode = input/wakeup + * direction = input + * value = low + * SLPM direction = same as normal + * SLPM pull = same as normal + * SLPM value = same as normal + * + * PIN_CFG - default config with alternate function + * PIN_CFG_PULL - default config with alternate function and pull up/down + */ + +typedef unsigned long pin_cfg_t; + +/* Sleep mode */ +enum db8500_gpio_slpm { + DB8500_GPIO_SLPM_INPUT, + DB8500_GPIO_SLPM_WAKEUP_ENABLE = DB8500_GPIO_SLPM_INPUT, + DB8500_GPIO_SLPM_NOCHANGE, + DB8500_GPIO_SLPM_WAKEUP_DISABLE = DB8500_GPIO_SLPM_NOCHANGE, +}; + +#define PIN_NUM_MASK 0x1ff +#define PIN_NUM(x) ((x) & PIN_NUM_MASK) + +#define PIN_ALT_SHIFT 9 +#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT) +#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT) +#define PIN_GPIO (DB8500_GPIO_ALT_GPIO << PIN_ALT_SHIFT) +#define PIN_ALT_A (DB8500_GPIO_ALT_A << PIN_ALT_SHIFT) +#define PIN_ALT_B (DB8500_GPIO_ALT_B << PIN_ALT_SHIFT) +#define PIN_ALT_C (DB8500_GPIO_ALT_C << PIN_ALT_SHIFT) + +#define PIN_PULL_SHIFT 11 +#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT) +#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT) +#define PIN_PULL_NONE (DB8500_GPIO_PULL_NONE << PIN_PULL_SHIFT) +#define PIN_PULL_UP (DB8500_GPIO_PULL_UP << PIN_PULL_SHIFT) +#define PIN_PULL_DOWN (DB8500_GPIO_PULL_DOWN << PIN_PULL_SHIFT) + +#define PIN_SLPM_SHIFT 13 +#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) +#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) +#define PIN_SLPM_MAKE_INPUT (DB8500_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) +#define PIN_SLPM_NOCHANGE (DB8500_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) +/* These two replace the above in DB8500v2+ */ +#define PIN_SLPM_WAKEUP_ENABLE \ + (DB8500_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) +#define PIN_SLPM_WAKEUP_DISABLE \ + (DB8500_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) + +#define PIN_DIR_SHIFT 14 +#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) +#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT) +#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT) +#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT) + +#define PIN_VAL_SHIFT 15 +#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT) +#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT) +#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) +#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) + +#define PIN_SLPM_PULL_SHIFT 16 +#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL(x) \ + (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL_NONE \ + ((1 + DB8500_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL_UP \ + ((1 + DB8500_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL_DOWN \ + ((1 + DB8500_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) + +#define PIN_SLPM_DIR_SHIFT 19 +#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) +#define PIN_SLPM_DIR(x) \ + (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) +#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) +#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) + +#define PIN_SLPM_VAL_SHIFT 21 +#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) +#define PIN_SLPM_VAL(x) \ + (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) +#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) +#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) + +/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ +#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) +#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) +#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) +#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) +#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) + +#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) +#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) +#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) +#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) +#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) + +#define PIN_CFG_DEFAULT (0) + +#define PIN_CFG(num, alt) \ + (PIN_CFG_DEFAULT |\ + (PIN_NUM(num) | PIN_##alt)) + +#define PIN_CFG_INPUT(num, alt, pull) \ + (PIN_CFG_DEFAULT |\ + (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) + +#define PIN_CFG_OUTPUT(num, alt, val) \ + (PIN_CFG_DEFAULT |\ + (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) + +#define PIN_CFG_PULL(num, alt, pull) \ + ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\ + (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull)) + +/** + * db8500_gpio_config_pins - configure several pins@once + * @cfgs: array of pin configurations + * @num: number of elments in the array + * + * Configures several GPIO pins. + */ +void db8500_gpio_config_pins(pin_cfg_t *cfgs, size_t num); + +#endif diff --git a/board/st-ericsson/snowball/Makefile b/board/st-ericsson/snowball/Makefile new file mode 100644 index 0000000..6138296 --- /dev/null +++ b/board/st-ericsson/snowball/Makefile @@ -0,0 +1,51 @@ +# +# Copyright (C) ST-Ericsson SA 2009 +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +CFLAGS += -D__RELEASE -D__STN_8500 +LIB = $(obj)lib$(BOARD).o + +COBJS := snowball.o + +#prcmu.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/st-ericsson/snowball/db8500_pins.h b/board/st-ericsson/snowball/db8500_pins.h new file mode 100644 index 0000000..e339cb8 --- /dev/null +++ b/board/st-ericsson/snowball/db8500_pins.h @@ -0,0 +1,745 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. + * The purpose is that GPIO config found in kernel should work by simply + * copy-paste it to U-boot. + * + * Ported to U-boot by: + * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com> + ** + * License terms: GNU General Public License, version 2 + * Author: Rabin Vincent <rabin.vincent@stericsson.com> + */ + +#ifndef __DB8500_PINS_H +#define __DB8500_PINS_H + +#include <asm/arch/db8500_pincfg.h> + +#define GPIO0_GPIO PIN_CFG(0, GPIO) +#define GPIO0_U0_CTSn PIN_CFG(0, ALT_A) +#define GPIO0_TRIG_OUT PIN_CFG(0, ALT_B) +#define GPIO0_IP_TDO PIN_CFG(0, ALT_C) + +#define GPIO1_GPIO PIN_CFG(1, GPIO) +#define GPIO1_U0_RTSn PIN_CFG(1, ALT_A) +#define GPIO1_TRIG_IN PIN_CFG(1, ALT_B) +#define GPIO1_IP_TDI PIN_CFG(1, ALT_C) + +#define GPIO2_GPIO PIN_CFG(2, GPIO) +#define GPIO2_U0_RXD PIN_CFG(2, ALT_A) +#define GPIO2_NONE PIN_CFG(2, ALT_B) +#define GPIO2_IP_TMS PIN_CFG(2, ALT_C) + +#define GPIO3_GPIO PIN_CFG(3, GPIO) +#define GPIO3_U0_TXD PIN_CFG(3, ALT_A) +#define GPIO3_NONE PIN_CFG(3, ALT_B) +#define GPIO3_IP_TCK PIN_CFG(3, ALT_C) + +#define GPIO4_GPIO PIN_CFG(4, GPIO) +#define GPIO4_U1_RXD PIN_CFG(4, ALT_A) +#define GPIO4_I2C4_SCL PIN_CFG_PULL(4, ALT_B, UP) +#define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C) + +#define GPIO5_GPIO PIN_CFG(5, GPIO) +#define GPIO5_U1_TXD PIN_CFG(5, ALT_A) +#define GPIO5_I2C4_SDA PIN_CFG_PULL(5, ALT_B, UP) +#define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C) + +#define GPIO6_GPIO PIN_CFG(6, GPIO) +#define GPIO6_U1_CTSn PIN_CFG(6, ALT_A) +#define GPIO6_I2C1_SCL PIN_CFG_PULL(6, ALT_B, UP) +#define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C) + +#define GPIO7_GPIO PIN_CFG(7, GPIO) +#define GPIO7_U1_RTSn PIN_CFG(7, ALT_A) +#define GPIO7_I2C1_SDA PIN_CFG_PULL(7, ALT_B, UP) +#define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C) + +#define GPIO8_GPIO PIN_CFG(8, GPIO) +#define GPIO8_IPI2C_SDA PIN_CFG_PULL(8, ALT_A, UP) +#define GPIO8_I2C2_SDA PIN_CFG_PULL(8, ALT_B, UP) + +#define GPIO9_GPIO PIN_CFG(9, GPIO) +#define GPIO9_IPI2C_SCL PIN_CFG_PULL(9, ALT_A, UP) +#define GPIO9_I2C2_SCL PIN_CFG_PULL(9, ALT_B, UP) + +#define GPIO10_GPIO PIN_CFG(10, GPIO) +#define GPIO10_IPI2C_SDA PIN_CFG_PULL(10, ALT_A, UP) +#define GPIO10_I2C2_SDA PIN_CFG_PULL(10, ALT_B, UP) +#define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C) + +#define GPIO11_GPIO PIN_CFG(11, GPIO) +#define GPIO11_IPI2C_SCL PIN_CFG_PULL(11, ALT_A, UP) +#define GPIO11_I2C2_SCL PIN_CFG_PULL(11, ALT_B, UP) +#define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C) + +#define GPIO12_GPIO PIN_CFG(12, GPIO) +#define GPIO12_MSP0_TXD PIN_CFG(12, ALT_A) +#define GPIO12_MSP0_RXD PIN_CFG(12, ALT_B) + +#define GPIO13_GPIO PIN_CFG(13, GPIO) +#define GPIO13_MSP0_TFS PIN_CFG(13, ALT_A) + +#define GPIO14_GPIO PIN_CFG(14, GPIO) +#define GPIO14_MSP0_TCK PIN_CFG(14, ALT_A) + +#define GPIO15_GPIO PIN_CFG(15, GPIO) +#define GPIO15_MSP0_RXD PIN_CFG(15, ALT_A) +#define GPIO15_MSP0_TXD PIN_CFG(15, ALT_B) + +#define GPIO16_GPIO PIN_CFG(16, GPIO) +#define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A) +#define GPIO16_I2C1_SCL PIN_CFG_PULL(16, ALT_B, UP) +#define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C) + +#define GPIO17_GPIO PIN_CFG(17, GPIO) +#define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A) +#define GPIO17_I2C1_SDA PIN_CFG_PULL(17, ALT_B, UP) +#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C) + +#define GPIO18_GPIO PIN_CFG(18, GPIO) +#define GPIO18_MC0_CMDDIR PIN_CFG(18, ALT_A) +#define GPIO18_U2_RXD PIN_CFG(18, ALT_B) +#define GPIO18_MS_IEP PIN_CFG(18, ALT_C) + +#define GPIO19_GPIO PIN_CFG(19, GPIO) +#define GPIO19_MC0_DAT0DIR PIN_CFG(19, ALT_A) +#define GPIO19_U2_TXD PIN_CFG(19, ALT_B) +#define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C) + +#define GPIO20_GPIO PIN_CFG(20, GPIO) +#define GPIO20_MC0_DAT2DIR PIN_CFG(20, ALT_A) +#define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B) +#define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C) + +#define GPIO21_GPIO PIN_CFG(21, GPIO) +#define GPIO21_MC0_DAT31DIR PIN_CFG(21, ALT_A) +#define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B) +#define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C) + +#define GPIO22_GPIO PIN_CFG(22, GPIO) +#define GPIO22_MC0_FBCLK PIN_CFG(22, ALT_A) +#define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B) +#define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C) + +#define GPIO23_GPIO PIN_CFG(23, GPIO) +#define GPIO23_MC0_CLK PIN_CFG(23, ALT_A) +#define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B) +#define GPIO23_MS_CLK PIN_CFG(23, ALT_C) + +#define GPIO24_GPIO PIN_CFG(24, GPIO) +#define GPIO24_MC0_CMD PIN_CFG(24, ALT_A) +#define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B) +#define GPIO24_MS_BS PIN_CFG(24, ALT_C) + +#define GPIO25_GPIO PIN_CFG(25, GPIO) +#define GPIO25_MC0_DAT0 PIN_CFG(25, ALT_A) +#define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B) +#define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C) + +#define GPIO26_GPIO PIN_CFG(26, GPIO) +#define GPIO26_MC0_DAT1 PIN_CFG(26, ALT_A) +#define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B) +#define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C) + +#define GPIO27_GPIO PIN_CFG(27, GPIO) +#define GPIO27_MC0_DAT2 PIN_CFG(27, ALT_A) +#define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B) +#define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C) + +#define GPIO28_GPIO PIN_CFG(28, GPIO) +#define GPIO28_MC0_DAT3 PIN_CFG(28, ALT_A) +#define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B) +#define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C) + +#define GPIO29_GPIO PIN_CFG(29, GPIO) +#define GPIO29_MC0_DAT4 PIN_CFG(29, ALT_A) +#define GPIO29_SPI3_CLK PIN_CFG(29, ALT_B) +#define GPIO29_U2_RXD PIN_CFG(29, ALT_C) + +#define GPIO30_GPIO PIN_CFG(30, GPIO) +#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A) +#define GPIO30_SPI3_RXD PIN_CFG(30, ALT_B) +#define GPIO30_U2_TXD PIN_CFG(30, ALT_C) + +#define GPIO31_GPIO PIN_CFG(31, GPIO) +#define GPIO31_MC0_DAT6 PIN_CFG(31, ALT_A) +#define GPIO31_SPI3_FRM PIN_CFG(31, ALT_B) +#define GPIO31_U2_CTSn PIN_CFG(31, ALT_C) + +#define GPIO32_GPIO PIN_CFG(32, GPIO) +#define GPIO32_MC0_DAT7 PIN_CFG(32, ALT_A) +#define GPIO32_SPI3_TXD PIN_CFG(32, ALT_B) +#define GPIO32_U2_RTSn PIN_CFG(32, ALT_C) + +#define GPIO33_GPIO PIN_CFG(33, GPIO) +#define GPIO33_MSP1_TXD PIN_CFG(33, ALT_A) +#define GPIO33_MSP1_RXD PIN_CFG(33, ALT_B) +#define GPIO33_U0_DTRn PIN_CFG(33, ALT_C) + +#define GPIO34_GPIO PIN_CFG(34, GPIO) +#define GPIO34_MSP1_TFS PIN_CFG(34, ALT_A) +#define GPIO34_NONE PIN_CFG(34, ALT_B) +#define GPIO34_U0_DCDn PIN_CFG(34, ALT_C) + +#define GPIO35_GPIO PIN_CFG(35, GPIO) +#define GPIO35_MSP1_TCK PIN_CFG(35, ALT_A) +#define GPIO35_NONE PIN_CFG(35, ALT_B) +#define GPIO35_U0_DSRn PIN_CFG(35, ALT_C) + +#define GPIO36_GPIO PIN_CFG(36, GPIO) +#define GPIO36_MSP1_RXD PIN_CFG(36, ALT_A) +#define GPIO36_MSP1_TXD PIN_CFG(36, ALT_B) +#define GPIO36_U0_RIn PIN_CFG(36, ALT_C) + +#define GPIO64_GPIO PIN_CFG(64, GPIO) +#define GPIO64_LCDB_DE PIN_CFG(64, ALT_A) +#define GPIO64_KP_O1 PIN_CFG(64, ALT_B) +#define GPIO64_IP_GPIO4 PIN_CFG(64, ALT_C) + +#define GPIO65_GPIO PIN_CFG(65, GPIO) +#define GPIO65_LCDB_HSO PIN_CFG(65, ALT_A) +#define GPIO65_KP_O0 PIN_CFG(65, ALT_B) +#define GPIO65_IP_GPIO5 PIN_CFG(65, ALT_C) + +#define GPIO66_GPIO PIN_CFG(66, GPIO) +#define GPIO66_LCDB_VSO PIN_CFG(66, ALT_A) +#define GPIO66_KP_I1 PIN_CFG(66, ALT_B) +#define GPIO66_IP_GPIO6 PIN_CFG(66, ALT_C) + +#define GPIO67_GPIO PIN_CFG(67, GPIO) +#define GPIO67_LCDB_CLK PIN_CFG(67, ALT_A) +#define GPIO67_KP_I0 PIN_CFG(67, ALT_B) +#define GPIO67_IP_GPIO7 PIN_CFG(67, ALT_C) + +#define GPIO68_GPIO PIN_CFG(68, GPIO) +#define GPIO68_LCD_VSI0 PIN_CFG(68, ALT_A) +#define GPIO68_KP_O7 PIN_CFG(68, ALT_B) +#define GPIO68_SM_CLE PIN_CFG(68, ALT_C) + +#define GPIO69_GPIO PIN_CFG(69, GPIO) +#define GPIO69_LCD_VSI1 PIN_CFG(69, ALT_A) +#define GPIO69_KP_I7 PIN_CFG(69, ALT_B) +#define GPIO69_SM_ALE PIN_CFG(69, ALT_C) + +#define GPIO70_GPIO PIN_CFG(70, GPIO) +#define GPIO70_LCD_D0 PIN_CFG(70, ALT_A) +#define GPIO70_KP_O5 PIN_CFG(70, ALT_B) +#define GPIO70_STMAPE_CLK PIN_CFG(70, ALT_C) + +#define GPIO71_GPIO PIN_CFG(71, GPIO) +#define GPIO71_LCD_D1 PIN_CFG(71, ALT_A) +#define GPIO71_KP_O4 PIN_CFG(71, ALT_B) +#define GPIO71_STMAPE_DAT3 PIN_CFG(71, ALT_C) + +#define GPIO72_GPIO PIN_CFG(72, GPIO) +#define GPIO72_LCD_D2 PIN_CFG(72, ALT_A) +#define GPIO72_KP_O3 PIN_CFG(72, ALT_B) +#define GPIO72_STMAPE_DAT2 PIN_CFG(72, ALT_C) + +#define GPIO73_GPIO PIN_CFG(73, GPIO) +#define GPIO73_LCD_D3 PIN_CFG(73, ALT_A) +#define GPIO73_KP_O2 PIN_CFG(73, ALT_B) +#define GPIO73_STMAPE_DAT1 PIN_CFG(73, ALT_C) + +#define GPIO74_GPIO PIN_CFG(74, GPIO) +#define GPIO74_LCD_D4 PIN_CFG(74, ALT_A) +#define GPIO74_KP_I5 PIN_CFG(74, ALT_B) +#define GPIO74_STMAPE_DAT0 PIN_CFG(74, ALT_C) + +#define GPIO75_GPIO PIN_CFG(75, GPIO) +#define GPIO75_LCD_D5 PIN_CFG(75, ALT_A) +#define GPIO75_KP_I4 PIN_CFG(75, ALT_B) +#define GPIO75_U2_RXD PIN_CFG(75, ALT_C) + +#define GPIO76_GPIO PIN_CFG(76, GPIO) +#define GPIO76_LCD_D6 PIN_CFG(76, ALT_A) +#define GPIO76_KP_I3 PIN_CFG(76, ALT_B) +#define GPIO76_U2_TXD PIN_CFG(76, ALT_C) + +#define GPIO77_GPIO PIN_CFG(77, GPIO) +#define GPIO77_LCD_D7 PIN_CFG(77, ALT_A) +#define GPIO77_KP_I2 PIN_CFG(77, ALT_B) +#define GPIO77_NONE PIN_CFG(77, ALT_C) + +#define GPIO78_GPIO PIN_CFG(78, GPIO) +#define GPIO78_LCD_D8 PIN_CFG(78, ALT_A) +#define GPIO78_KP_O6 PIN_CFG(78, ALT_B) +#define GPIO78_IP_GPIO2 PIN_CFG(78, ALT_C) + +#define GPIO79_GPIO PIN_CFG(79, GPIO) +#define GPIO79_LCD_D9 PIN_CFG(79, ALT_A) +#define GPIO79_KP_I6 PIN_CFG(79, ALT_B) +#define GPIO79_IP_GPIO3 PIN_CFG(79, ALT_C) + +#define GPIO80_GPIO PIN_CFG(80, GPIO) +#define GPIO80_LCD_D10 PIN_CFG(80, ALT_A) +#define GPIO80_KP_SKA0 PIN_CFG(80, ALT_B) +#define GPIO80_IP_GPIO4 PIN_CFG(80, ALT_C) + +#define GPIO81_GPIO PIN_CFG(81, GPIO) +#define GPIO81_LCD_D11 PIN_CFG(81, ALT_A) +#define GPIO81_KP_SKB0 PIN_CFG(81, ALT_B) +#define GPIO81_IP_GPIO5 PIN_CFG(81, ALT_C) + +#define GPIO82_GPIO PIN_CFG(82, GPIO) +#define GPIO82_LCD_D12 PIN_CFG(82, ALT_A) +#define GPIO82_KP_O5 PIN_CFG(82, ALT_B) + +#define GPIO83_GPIO PIN_CFG(83, GPIO) +#define GPIO83_LCD_D13 PIN_CFG(83, ALT_A) +#define GPIO83_KP_O4 PIN_CFG(83, ALT_B) + +#define GPIO84_GPIO PIN_CFG_PULL(84, GPIO, UP) +#define GPIO84_LCD_D14 PIN_CFG(84, ALT_A) +#define GPIO84_KP_I5 PIN_CFG(84, ALT_B) + +#define GPIO85_GPIO PIN_CFG(85, GPIO) +#define GPIO85_LCD_D15 PIN_CFG(85, ALT_A) +#define GPIO85_KP_I4 PIN_CFG(85, ALT_B) + +#define GPIO86_GPIO PIN_CFG(86, GPIO) +#define GPIO86_LCD_D16 PIN_CFG(86, ALT_A) +#define GPIO86_SM_ADQ0 PIN_CFG(86, ALT_B) +#define GPIO86_MC5_DAT0 PIN_CFG(86, ALT_C) + +#define GPIO87_GPIO PIN_CFG(87, GPIO) +#define GPIO87_LCD_D17 PIN_CFG(87, ALT_A) +#define GPIO87_SM_ADQ1 PIN_CFG(87, ALT_B) +#define GPIO87_MC5_DAT1 PIN_CFG(87, ALT_C) + +#define GPIO88_GPIO PIN_CFG(88, GPIO) +#define GPIO88_LCD_D18 PIN_CFG(88, ALT_A) +#define GPIO88_SM_ADQ2 PIN_CFG(88, ALT_B) +#define GPIO88_MC5_DAT2 PIN_CFG(88, ALT_C) + +#define GPIO89_GPIO PIN_CFG(89, GPIO) +#define GPIO89_LCD_D19 PIN_CFG(89, ALT_A) +#define GPIO89_SM_ADQ3 PIN_CFG(89, ALT_B) +#define GPIO89_MC5_DAT3 PIN_CFG(89, ALT_C) + +#define GPIO90_GPIO PIN_CFG(90, GPIO) +#define GPIO90_LCD_D20 PIN_CFG(90, ALT_A) +#define GPIO90_SM_ADQ4 PIN_CFG(90, ALT_B) +#define GPIO90_MC5_CMD PIN_CFG(90, ALT_C) + +#define GPIO91_GPIO PIN_CFG(91, GPIO) +#define GPIO91_LCD_D21 PIN_CFG(91, ALT_A) +#define GPIO91_SM_ADQ5 PIN_CFG(91, ALT_B) +#define GPIO91_MC5_FBCLK PIN_CFG(91, ALT_C) + +#define GPIO92_GPIO PIN_CFG(92, GPIO) +#define GPIO92_LCD_D22 PIN_CFG(92, ALT_A) +#define GPIO92_SM_ADQ6 PIN_CFG(92, ALT_B) +#define GPIO92_MC5_CLK PIN_CFG(92, ALT_C) + +#define GPIO93_GPIO PIN_CFG(93, GPIO) +#define GPIO93_LCD_D23 PIN_CFG(93, ALT_A) +#define GPIO93_SM_ADQ7 PIN_CFG(93, ALT_B) +#define GPIO93_MC5_DAT4 PIN_CFG(93, ALT_C) + +#define GPIO94_GPIO PIN_CFG(94, GPIO) +#define GPIO94_KP_O7 PIN_CFG(94, ALT_A) +#define GPIO94_SM_ADVn PIN_CFG(94, ALT_B) +#define GPIO94_MC5_DAT5 PIN_CFG(94, ALT_C) + +#define GPIO95_GPIO PIN_CFG(95, GPIO) +#define GPIO95_KP_I7 PIN_CFG(95, ALT_A) +#define GPIO95_SM_CS0n PIN_CFG(95, ALT_B) +#define GPIO95_SM_PS0n PIN_CFG(95, ALT_C) + +#define GPIO96_GPIO PIN_CFG(96, GPIO) +#define GPIO96_KP_O6 PIN_CFG(96, ALT_A) +#define GPIO96_SM_OEn PIN_CFG(96, ALT_B) +#define GPIO96_MC5_DAT6 PIN_CFG(96, ALT_C) + +#define GPIO97_GPIO PIN_CFG(97, GPIO) +#define GPIO97_KP_I6 PIN_CFG(97, ALT_A) +#define GPIO97_SM_WEn PIN_CFG(97, ALT_B) +#define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C) + +#define GPIO128_GPIO PIN_CFG(128, GPIO) +#define GPIO128_MC2_CLK PIN_CFG(128, ALT_A) +#define GPIO128_SM_CKO PIN_CFG(128, ALT_B) + +#define GPIO129_GPIO PIN_CFG(129, GPIO) +#define GPIO129_MC2_CMD PIN_CFG(129, ALT_A) +#define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B) + +#define GPIO130_GPIO PIN_CFG(130, GPIO) +#define GPIO130_MC2_FBCLK PIN_CFG(130, ALT_A) +#define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B) +#define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C) + +#define GPIO131_GPIO PIN_CFG(131, GPIO) +#define GPIO131_MC2_DAT0 PIN_CFG(131, ALT_A) +#define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B) + +#define GPIO132_GPIO PIN_CFG(132, GPIO) +#define GPIO132_MC2_DAT1 PIN_CFG(132, ALT_A) +#define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B) + +#define GPIO133_GPIO PIN_CFG(133, GPIO) +#define GPIO133_MC2_DAT2 PIN_CFG(133, ALT_A) +#define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B) + +#define GPIO134_GPIO PIN_CFG(134, GPIO) +#define GPIO134_MC2_DAT3 PIN_CFG(134, ALT_A) +#define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B) + +#define GPIO135_GPIO PIN_CFG(135, GPIO) +#define GPIO135_MC2_DAT4 PIN_CFG(135, ALT_A) +#define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B) + +#define GPIO136_GPIO PIN_CFG(136, GPIO) +#define GPIO136_MC2_DAT5 PIN_CFG(136, ALT_A) +#define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B) + +#define GPIO137_GPIO PIN_CFG(137, GPIO) +#define GPIO137_MC2_DAT6 PIN_CFG(137, ALT_A) +#define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B) + +#define GPIO138_GPIO PIN_CFG(138, GPIO) +#define GPIO138_MC2_DAT7 PIN_CFG(138, ALT_A) +#define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B) + +#define GPIO139_GPIO PIN_CFG(139, GPIO) +#define GPIO139_SSP1_RXD PIN_CFG(139, ALT_A) +#define GPIO139_SM_WAIT1n PIN_CFG(139, ALT_B) +#define GPIO139_KP_O8 PIN_CFG(139, ALT_C) + +#define GPIO140_GPIO PIN_CFG(140, GPIO) +#define GPIO140_SSP1_TXD PIN_CFG(140, ALT_A) +#define GPIO140_IP_GPIO7 PIN_CFG(140, ALT_B) +#define GPIO140_KP_SKA1 PIN_CFG(140, ALT_C) + +#define GPIO141_GPIO PIN_CFG(141, GPIO) +#define GPIO141_SSP1_CLK PIN_CFG(141, ALT_A) +#define GPIO141_IP_GPIO2 PIN_CFG(141, ALT_B) +#define GPIO141_KP_O9 PIN_CFG(141, ALT_C) + +#define GPIO142_GPIO PIN_CFG(142, GPIO) +#define GPIO142_SSP1_FRM PIN_CFG(142, ALT_A) +#define GPIO142_IP_GPIO3 PIN_CFG(142, ALT_B) +#define GPIO142_KP_SKB1 PIN_CFG(142, ALT_C) + +#define GPIO143_GPIO PIN_CFG(143, GPIO) +#define GPIO143_SSP0_CLK PIN_CFG(143, ALT_A) + +#define GPIO144_GPIO PIN_CFG(144, GPIO) +#define GPIO144_SSP0_FRM PIN_CFG(144, ALT_A) + +#define GPIO145_GPIO PIN_CFG(145, GPIO) +#define GPIO145_SSP0_RXD PIN_CFG(145, ALT_A) + +#define GPIO146_GPIO PIN_CFG(146, GPIO) +#define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A) + +#define GPIO147_GPIO PIN_CFG(147, GPIO) +#define GPIO147_I2C0_SCL PIN_CFG_PULL(147, ALT_A, UP) + +#define GPIO148_GPIO PIN_CFG(148, GPIO) +#define GPIO148_I2C0_SDA PIN_CFG_PULL(148, ALT_A, UP) + +#define GPIO149_GPIO PIN_CFG(149, GPIO) +#define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A) +#define GPIO149_SM_CS1n PIN_CFG(149, ALT_B) +#define GPIO149_SM_PS1n PIN_CFG(149, ALT_C) + +#define GPIO150_GPIO PIN_CFG(150, GPIO) +#define GPIO150_IP_GPIO1 PIN_CFG(150, ALT_A) +#define GPIO150_LCDA_CLK PIN_CFG(150, ALT_B) + +#define GPIO151_GPIO PIN_CFG(151, GPIO) +#define GPIO151_KP_SKA0 PIN_CFG(151, ALT_A) +#define GPIO151_LCD_VSI0 PIN_CFG(151, ALT_B) +#define GPIO151_KP_O8 PIN_CFG(151, ALT_C) + +#define GPIO152_GPIO PIN_CFG(152, GPIO) +#define GPIO152_KP_SKB0 PIN_CFG(152, ALT_A) +#define GPIO152_LCD_VSI1 PIN_CFG(152, ALT_B) +#define GPIO152_KP_O9 PIN_CFG(152, ALT_C) + +#define GPIO153_GPIO PIN_CFG(153, GPIO) +#define GPIO153_KP_I7 PIN_CFG_PULL(153, ALT_A, DOWN) +#define GPIO153_LCD_D24 PIN_CFG(153, ALT_B) +#define GPIO153_U2_RXD PIN_CFG(153, ALT_C) + +#define GPIO154_GPIO PIN_CFG(154, GPIO) +#define GPIO154_KP_I6 PIN_CFG_PULL(154, ALT_A, DOWN) +#define GPIO154_LCD_D25 PIN_CFG(154, ALT_B) +#define GPIO154_U2_TXD PIN_CFG(154, ALT_C) + +#define GPIO155_GPIO PIN_CFG(155, GPIO) +#define GPIO155_KP_I5 PIN_CFG_PULL(155, ALT_A, DOWN) +#define GPIO155_LCD_D26 PIN_CFG(155, ALT_B) +#define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C) + +#define GPIO156_GPIO PIN_CFG(156, GPIO) +#define GPIO156_KP_I4 PIN_CFG_PULL(156, ALT_A, DOWN) +#define GPIO156_LCD_D27 PIN_CFG(156, ALT_B) +#define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C) + +#define GPIO157_GPIO PIN_CFG(157, GPIO) +#define GPIO157_KP_O7 PIN_CFG_PULL(157, ALT_A, UP) +#define GPIO157_LCD_D28 PIN_CFG(157, ALT_B) +#define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C) + +#define GPIO158_GPIO PIN_CFG(158, GPIO) +#define GPIO158_KP_O6 PIN_CFG_PULL(158, ALT_A, UP) +#define GPIO158_LCD_D29 PIN_CFG(158, ALT_B) +#define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C) + +#define GPIO159_GPIO PIN_CFG(159, GPIO) +#define GPIO159_KP_O5 PIN_CFG_PULL(159, ALT_A, UP) +#define GPIO159_LCD_D30 PIN_CFG(159, ALT_B) +#define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C) + +#define GPIO160_GPIO PIN_CFG(160, GPIO) +#define GPIO160_KP_O4 PIN_CFG_PULL(160, ALT_A, UP) +#define GPIO160_LCD_D31 PIN_CFG(160, ALT_B) +#define GPIO160_NONE PIN_CFG(160, ALT_C) + +#define GPIO161_GPIO PIN_CFG(161, GPIO) +#define GPIO161_KP_I3 PIN_CFG_PULL(161, ALT_A, DOWN) +#define GPIO161_LCD_D32 PIN_CFG(161, ALT_B) +#define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C) + +#define GPIO162_GPIO PIN_CFG(162, GPIO) +#define GPIO162_KP_I2 PIN_CFG_PULL(162, ALT_A, DOWN) +#define GPIO162_LCD_D33 PIN_CFG(162, ALT_B) +#define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C) + +#define GPIO163_GPIO PIN_CFG(163, GPIO) +#define GPIO163_KP_I1 PIN_CFG_PULL(163, ALT_A, DOWN) +#define GPIO163_LCD_D34 PIN_CFG(163, ALT_B) +#define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C) + +#define GPIO164_GPIO PIN_CFG(164, GPIO) +#define GPIO164_KP_I0 PIN_CFG_PULL(164, ALT_A, UP) +#define GPIO164_LCD_D35 PIN_CFG(164, ALT_B) +#define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C) + +#define GPIO165_GPIO PIN_CFG(165, GPIO) +#define GPIO165_KP_O3 PIN_CFG_PULL(165, ALT_A, UP) +#define GPIO165_LCD_D36 PIN_CFG(165, ALT_B) +#define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C) + +#define GPIO166_GPIO PIN_CFG(166, GPIO) +#define GPIO166_KP_O2 PIN_CFG_PULL(166, ALT_A, UP) +#define GPIO166_LCD_D37 PIN_CFG(166, ALT_B) +#define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C) + +#define GPIO167_GPIO PIN_CFG(167, GPIO) +#define GPIO167_KP_O1 PIN_CFG_PULL(167, ALT_A, UP) +#define GPIO167_LCD_D38 PIN_CFG(167, ALT_B) +#define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C) + +#define GPIO168_GPIO PIN_CFG(168, GPIO) +#define GPIO168_KP_O0 PIN_CFG_PULL(168, ALT_A, UP) +#define GPIO168_LCD_D39 PIN_CFG(168, ALT_B) +#define GPIO168_NONE PIN_CFG(168, ALT_C) + +#define GPIO169_GPIO PIN_CFG(169, GPIO) +#define GPIO169_RF_PURn PIN_CFG(169, ALT_A) +#define GPIO169_LCDA_DE PIN_CFG(169, ALT_B) +#define GPIO169_USBSIM_PDC PIN_CFG(169, ALT_C) + +#define GPIO170_GPIO PIN_CFG(170, GPIO) +#define GPIO170_MODEM_STATE PIN_CFG(170, ALT_A) +#define GPIO170_LCDA_VSO PIN_CFG(170, ALT_B) +#define GPIO170_KP_SKA1 PIN_CFG(170, ALT_C) + +#define GPIO171_GPIO PIN_CFG(171, GPIO) +#define GPIO171_MODEM_PWREN PIN_CFG(171, ALT_A) +#define GPIO171_LCDA_HSO PIN_CFG(171, ALT_B) +#define GPIO171_KP_SKB1 PIN_CFG(171, ALT_C) + +#define GPIO192_GPIO PIN_CFG(192, GPIO) +#define GPIO192_MSP2_SCK PIN_CFG(192, ALT_A) + +#define GPIO193_GPIO PIN_CFG(193, GPIO) +#define GPIO193_MSP2_TXD PIN_CFG(193, ALT_A) + +#define GPIO194_GPIO PIN_CFG(194, GPIO) +#define GPIO194_MSP2_TCK PIN_CFG(194, ALT_A) + +#define GPIO195_GPIO PIN_CFG(195, GPIO) +#define GPIO195_MSP2_TFS PIN_CFG(195, ALT_A) + +#define GPIO196_GPIO PIN_CFG(196, GPIO) +#define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A) + +#define GPIO197_GPIO PIN_CFG(197, GPIO) +#define GPIO197_MC4_DAT3 PIN_CFG(197, ALT_A) + +#define GPIO198_GPIO PIN_CFG(198, GPIO) +#define GPIO198_MC4_DAT2 PIN_CFG(198, ALT_A) + +#define GPIO199_GPIO PIN_CFG(199, GPIO) +#define GPIO199_MC4_DAT1 PIN_CFG(199, ALT_A) + +#define GPIO200_GPIO PIN_CFG(200, GPIO) +#define GPIO200_MC4_DAT0 PIN_CFG(200, ALT_A) + +#define GPIO201_GPIO PIN_CFG(201, GPIO) +#define GPIO201_MC4_CMD PIN_CFG(201, ALT_A) + +#define GPIO202_GPIO PIN_CFG(202, GPIO) +#define GPIO202_MC4_FBCLK PIN_CFG(202, ALT_A) +#define GPIO202_PWL PIN_CFG(202, ALT_B) +#define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C) + +#define GPIO203_GPIO PIN_CFG(203, GPIO) +#define GPIO203_MC4_CLK PIN_CFG(203, ALT_A) + +#define GPIO204_GPIO PIN_CFG(204, GPIO) +#define GPIO204_MC4_DAT7 PIN_CFG(204, ALT_A) + +#define GPIO205_GPIO PIN_CFG(205, GPIO) +#define GPIO205_MC4_DAT6 PIN_CFG(205, ALT_A) + +#define GPIO206_GPIO PIN_CFG(206, GPIO) +#define GPIO206_MC4_DAT5 PIN_CFG(206, ALT_A) + +#define GPIO207_GPIO PIN_CFG(207, GPIO) +#define GPIO207_MC4_DAT4 PIN_CFG(207, ALT_A) + +#define GPIO208_GPIO PIN_CFG(208, GPIO) +#define GPIO208_MC1_CLK PIN_CFG(208, ALT_A) + +#define GPIO209_GPIO PIN_CFG(209, GPIO) +#define GPIO209_MC1_FBCLK PIN_CFG(209, ALT_A) +#define GPIO209_SPI1_CLK PIN_CFG(209, ALT_B) + +#define GPIO210_GPIO PIN_CFG(210, GPIO) +#define GPIO210_MC1_CMD PIN_CFG(210, ALT_A) + +#define GPIO211_GPIO PIN_CFG(211, GPIO) +#define GPIO211_MC1_DAT0 PIN_CFG(211, ALT_A) + +#define GPIO212_GPIO PIN_CFG(212, GPIO) +#define GPIO212_MC1_DAT1 PIN_CFG(212, ALT_A) +#define GPIO212_SPI1_FRM PIN_CFG(212, ALT_B) + +#define GPIO213_GPIO PIN_CFG(213, GPIO) +#define GPIO213_MC1_DAT2 PIN_CFG(213, ALT_A) +#define GPIO213_SPI1_TXD PIN_CFG(213, ALT_B) + +#define GPIO214_GPIO PIN_CFG(214, GPIO) +#define GPIO214_MC1_DAT3 PIN_CFG(214, ALT_A) +#define GPIO214_SPI1_RXD PIN_CFG(214, ALT_B) + +#define GPIO215_GPIO PIN_CFG(215, GPIO) +#define GPIO215_MC1_CMDDIR PIN_CFG(215, ALT_A) +#define GPIO215_MC3_DAT2DIR PIN_CFG(215, ALT_B) +#define GPIO215_CLKOUT1 PIN_CFG(215, ALT_C) + +#define GPIO216_GPIO PIN_CFG(216, GPIO) +#define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A) +#define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B) +#define GPIO216_I2C3_SDA PIN_CFG_PULL(216, ALT_C, UP) + +#define GPIO217_GPIO PIN_CFG(217, GPIO) +#define GPIO217_MC1_DAT0DIR PIN_CFG(217, ALT_A) +#define GPIO217_MC3_DAT31DIR PIN_CFG(217, ALT_B) +#define GPIO217_CLKOUT2 PIN_CFG(217, ALT_C) + +#define GPIO218_GPIO PIN_CFG(218, GPIO) +#define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A) +#define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B) +#define GPIO218_I2C3_SCL PIN_CFG_PULL(218, ALT_C, UP) + +#define GPIO219_GPIO PIN_CFG(219, GPIO) +#define GPIO219_HSIR_FLA0 PIN_CFG(219, ALT_A) +#define GPIO219_MC3_CLK PIN_CFG(219, ALT_B) + +#define GPIO220_GPIO PIN_CFG(220, GPIO) +#define GPIO220_HSIR_DAT0 PIN_CFG(220, ALT_A) +#define GPIO220_MC3_FBCLK PIN_CFG(220, ALT_B) +#define GPIO220_SPI0_CLK PIN_CFG(220, ALT_C) + +#define GPIO221_GPIO PIN_CFG(221, GPIO) +#define GPIO221_HSIR_RDY0 PIN_CFG(221, ALT_A) +#define GPIO221_MC3_CMD PIN_CFG(221, ALT_B) + +#define GPIO222_GPIO PIN_CFG(222, GPIO) +#define GPIO222_HSIT_FLA0 PIN_CFG(222, ALT_A) +#define GPIO222_MC3_DAT0 PIN_CFG(222, ALT_B) + +#define GPIO223_GPIO PIN_CFG(223, GPIO) +#define GPIO223_HSIT_DAT0 PIN_CFG(223, ALT_A) +#define GPIO223_MC3_DAT1 PIN_CFG(223, ALT_B) +#define GPIO223_SPI0_FRM PIN_CFG(223, ALT_C) + +#define GPIO224_GPIO PIN_CFG(224, GPIO) +#define GPIO224_HSIT_RDY0 PIN_CFG(224, ALT_A) +#define GPIO224_MC3_DAT2 PIN_CFG(224, ALT_B) +#define GPIO224_SPI0_TXD PIN_CFG(224, ALT_C) + +#define GPIO225_GPIO PIN_CFG(225, GPIO) +#define GPIO225_HSIT_CAWAKE0 PIN_CFG(225, ALT_A) +#define GPIO225_MC3_DAT3 PIN_CFG(225, ALT_B) +#define GPIO225_SPI0_RXD PIN_CFG(225, ALT_C) + +#define GPIO226_GPIO PIN_CFG(226, GPIO) +#define GPIO226_HSIT_ACWAKE0 PIN_CFG(226, ALT_A) +#define GPIO226_PWL PIN_CFG(226, ALT_B) +#define GPIO226_USBSIM_PDC PIN_CFG(226, ALT_C) + +#define GPIO227_GPIO PIN_CFG(227, GPIO) +#define GPIO227_CLKOUT1 PIN_CFG(227, ALT_A) + +#define GPIO228_GPIO PIN_CFG(228, GPIO) +#define GPIO228_CLKOUT2 PIN_CFG(228, ALT_A) + +#define GPIO229_GPIO PIN_CFG(229, GPIO) +#define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A) +#define GPIO229_PWL PIN_CFG(229, ALT_B) +#define GPIO229_I2C3_SDA PIN_CFG_PULL(229, ALT_C, UP) + +#define GPIO230_GPIO PIN_CFG(230, GPIO) +#define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A) +#define GPIO230_PWL PIN_CFG(230, ALT_B) +#define GPIO230_I2C3_SCL PIN_CFG_PULL(230, ALT_C, UP) + +#define GPIO256_GPIO PIN_CFG(256, GPIO) +#define GPIO256_USB_NXT PIN_CFG(256, ALT_A) + +#define GPIO257_GPIO PIN_CFG(257, GPIO) +#define GPIO257_USB_STP PIN_CFG(257, ALT_A) + +#define GPIO258_GPIO PIN_CFG(258, GPIO) +#define GPIO258_USB_XCLK PIN_CFG(258, ALT_A) +#define GPIO258_NONE PIN_CFG(258, ALT_B) +#define GPIO258_DDR_TRIG PIN_CFG(258, ALT_C) + +#define GPIO259_GPIO PIN_CFG(259, GPIO) +#define GPIO259_USB_DIR PIN_CFG(259, ALT_A) + +#define GPIO260_GPIO PIN_CFG(260, GPIO) +#define GPIO260_USB_DAT7 PIN_CFG(260, ALT_A) + +#define GPIO261_GPIO PIN_CFG(261, GPIO) +#define GPIO261_USB_DAT6 PIN_CFG(261, ALT_A) + +#define GPIO262_GPIO PIN_CFG(262, GPIO) +#define GPIO262_USB_DAT5 PIN_CFG(262, ALT_A) + +#define GPIO263_GPIO PIN_CFG(263, GPIO) +#define GPIO263_USB_DAT4 PIN_CFG(263, ALT_A) + +#define GPIO264_GPIO PIN_CFG(264, GPIO) +#define GPIO264_USB_DAT3 PIN_CFG(264, ALT_A) + +#define GPIO265_GPIO PIN_CFG(265, GPIO) +#define GPIO265_USB_DAT2 PIN_CFG(265, ALT_A) + +#define GPIO266_GPIO PIN_CFG(266, GPIO) +#define GPIO266_USB_DAT1 PIN_CFG(266, ALT_A) + +#define GPIO267_GPIO PIN_CFG(267, GPIO) +#define GPIO267_USB_DAT0 PIN_CFG(267, ALT_A) + +#endif diff --git a/board/st-ericsson/snowball/snowball.c b/board/st-ericsson/snowball/snowball.c new file mode 100644 index 0000000..79c86df --- /dev/null +++ b/board/st-ericsson/snowball/snowball.c @@ -0,0 +1,185 @@ +/* + * Copyright (C) ST-Ericsson SA 2009 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <malloc.h> +#include <i2c.h> +#include <mmc.h> +#include <asm/types.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/db8500_pincfg.h> + +#include "db8500_pins.h" + +/* + * Get a global data pointer + */ +DECLARE_GLOBAL_DATA_PTR; + +/* + * Memory controller register + */ +#define DMC_BASE_ADDR 0x80156000 +#define DMC_CTL_97 (DMC_BASE_ADDR + 0x184) + +/* + * GPIO pin config common for MOP500/HREF boards + */ +pin_cfg_t gpio_cfg_common[] = { + /* I2C */ + GPIO147_I2C0_SCL, + GPIO148_I2C0_SDA, + GPIO16_I2C1_SCL, + GPIO17_I2C1_SDA, + GPIO10_I2C2_SDA, + GPIO11_I2C2_SCL, + GPIO229_I2C3_SDA, + GPIO230_I2C3_SCL, + + /* SSP0, to AB8500 */ + GPIO143_SSP0_CLK, + GPIO144_SSP0_FRM, + GPIO145_SSP0_RXD | PIN_PULL_DOWN, + GPIO146_SSP0_TXD, + + /* MMC0 (MicroSD card) */ + GPIO18_MC0_CMDDIR | PIN_OUTPUT_HIGH, + GPIO19_MC0_DAT0DIR | PIN_OUTPUT_HIGH, + GPIO20_MC0_DAT2DIR | PIN_OUTPUT_HIGH, + GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH, + GPIO22_MC0_FBCLK | PIN_INPUT_NOPULL, + GPIO23_MC0_CLK | PIN_OUTPUT_LOW, + GPIO24_MC0_CMD | PIN_INPUT_PULLUP, + GPIO25_MC0_DAT0 | PIN_INPUT_PULLUP, + GPIO26_MC0_DAT1 | PIN_INPUT_PULLUP, + GPIO27_MC0_DAT2 | PIN_INPUT_PULLUP, + GPIO28_MC0_DAT3 | PIN_INPUT_PULLUP, + + /* MMC4 (On-board eMMC) */ + GPIO197_MC4_DAT3 | PIN_INPUT_PULLUP, + GPIO198_MC4_DAT2 | PIN_INPUT_PULLUP, + GPIO199_MC4_DAT1 | PIN_INPUT_PULLUP, + GPIO200_MC4_DAT0 | PIN_INPUT_PULLUP, + GPIO201_MC4_CMD | PIN_INPUT_PULLUP, + GPIO202_MC4_FBCLK | PIN_INPUT_NOPULL, + GPIO203_MC4_CLK | PIN_OUTPUT_LOW, + GPIO204_MC4_DAT7 | PIN_INPUT_PULLUP, + GPIO205_MC4_DAT6 | PIN_INPUT_PULLUP, + GPIO206_MC4_DAT5 | PIN_INPUT_PULLUP, + GPIO207_MC4_DAT4 | PIN_INPUT_PULLUP, + + /* UART2, console */ + GPIO29_U2_RXD | PIN_INPUT_PULLUP, + GPIO30_U2_TXD | PIN_OUTPUT_HIGH, + GPIO31_U2_CTSn | PIN_INPUT_PULLUP, + GPIO32_U2_RTSn | PIN_OUTPUT_HIGH, + + /* + * USB, pin 256-267 USB, Is probably already setup correctly from + * BootROM/boot stages, but we don't trust that and set it up anyway + */ + GPIO256_USB_NXT, + GPIO257_USB_STP, + GPIO258_USB_XCLK, + GPIO259_USB_DIR, + GPIO260_USB_DAT7, + GPIO261_USB_DAT6, + GPIO262_USB_DAT5, + GPIO263_USB_DAT4, + GPIO264_USB_DAT3, + GPIO265_USB_DAT2, + GPIO266_USB_DAT1, + GPIO267_USB_DAT0, +}; + +pin_cfg_t gpio_cfg_snowball[] = { + /* MMC0 (MicroSD card) */ + GPIO217_GPIO | PIN_OUTPUT_HIGH, /* MMC_EN */ + GPIO218_GPIO | PIN_INPUT_NOPULL, /* MMC_CD */ + GPIO228_GPIO | PIN_OUTPUT_HIGH, /* SD_SEL */ + + /* eMMC */ + GPIO167_GPIO | PIN_OUTPUT_HIGH, /* RSTn_MLC */ + + /* LAN */ + GPIO131_SM_ADQ8, + GPIO132_SM_ADQ9, + GPIO133_SM_ADQ10, + GPIO134_SM_ADQ11, + GPIO135_SM_ADQ12, + GPIO136_SM_ADQ13, + GPIO137_SM_ADQ14, + GPIO138_SM_ADQ15, + + /* RSTn_LAN */ + GPIO141_GPIO | PIN_OUTPUT_HIGH, +}; + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init(void) +{ + /* + * Setup board (bd) and board-info (bi). + * bi_arch_number: Unique id for this board. It will passed in r1 to + * Linux startup code and is the machine_id. + * bi_boot_params: Where this board expects params. + */ + gd->bd->bi_arch_number = MACH_TYPE_SNOWBALL; + gd->bd->bi_boot_params = 0x00000100; + + /* Configure GPIO pins needed by U-boot */ + db8500_gpio_config_pins(gpio_cfg_common, ARRAY_SIZE(gpio_cfg_common)); + + db8500_gpio_config_pins(gpio_cfg_snowball, + ARRAY_SIZE(gpio_cfg_snowball)); + + return 0; +} + +int dram_init(void) +{ + uint32_t unused_cols_rows; + unsigned int nrows; + unsigned int ncols; + + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->ram_size = PHYS_SDRAM_SIZE_1; + + /* + * Assumption: 2 CS active, both CS have same layout. + * 15 rows max, 11 cols max (controller spec). + * memory chip has 8 banks, I/O width 32 bit. + * The correct way would be to read MR#8: I/O width and density, + * but this requires locking against the PRCMU firmware. + * Simplified approach: + * Read number of unused rows and columns from mem controller. + * size = nCS x 2^(rows+cols) x nbanks x buswidth_bytes + */ + unused_cols_rows = readl(DMC_CTL_97); + nrows = 15 - (unused_cols_rows & 0x07); + ncols = 11 - ((unused_cols_rows & 0x0700) >> 8); + gd->ram_size = gd->bd->bi_dram[0].size = + 2 * (1 << (nrows + ncols)) * 8 * 4; + + return 0; +} diff --git a/boards.cfg b/boards.cfg index 9ef903a..db5cb0a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -232,6 +232,7 @@ harmony arm armv7 harmony nvidia seaboard arm armv7 seaboard nvidia tegra2 ventana arm armv7 ventana nvidia tegra2 u8500_href arm armv7 u8500 st-ericsson u8500 +snowball arm armv7 snowball st-ericsson u8500 actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index fb3b09a..36a0ff3 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -39,6 +39,7 @@ COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o +COBJS-$(CONFIG_DB8500_GPIO) += db8500_gpio.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/gpio/db8500_gpio.c b/drivers/gpio/db8500_gpio.c new file mode 100644 index 0000000..5eb6361 --- /dev/null +++ b/drivers/gpio/db8500_gpio.c @@ -0,0 +1,225 @@ +/* + * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. + * The purpose is that GPIO config found in kernel should work by simply + * copy-paste it to U-boot. + * + * Original Linux authors: + * Copyright (C) 2008,2009 STMicroelectronics + * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> + * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> + * + * Ported to U-boot by: + * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <common.h> +#include <asm/io.h> + +#include <asm/arch/db8500_gpio.h> +#include <asm/arch/db8500_pincfg.h> + +/* + * Macros to work with IO space + * Not actually used? + */ +#define __iomem +#define IO_ADDR(x) (void *) (x) + +/* + * The GPIO module in the db8500 Systems-on-Chip is an + * AMBA device, managing 32 pins and alternate functions. The logic block + * is currently only used in the db8500. + */ + +#define GPIO_TOTAL_PINS 268 +#define GPIO_PINS_PER_BLOCK 32 +#define GPIO_BLOCKS_COUNT (GPIO_TOTAL_PINS/GPIO_PINS_PER_BLOCK + 1) +#define GPIO_BLOCK(pin) (((pin + GPIO_PINS_PER_BLOCK) >> 5) - 1) +#define GPIO_PIN_WITHIN_BLOCK(pin) ((pin)%(GPIO_PINS_PER_BLOCK)) + +/* Register in the logic block */ +#define DB8500_GPIO_DAT 0x00 +#define DB8500_GPIO_DATS 0x04 +#define DB8500_GPIO_DATC 0x08 +#define DB8500_GPIO_PDIS 0x0c +#define DB8500_GPIO_DIR 0x10 +#define DB8500_GPIO_DIRS 0x14 +#define DB8500_GPIO_DIRC 0x18 +#define DB8500_GPIO_SLPC 0x1c +#define DB8500_GPIO_AFSLA 0x20 +#define DB8500_GPIO_AFSLB 0x24 + +#define DB8500_GPIO_RIMSC 0x40 +#define DB8500_GPIO_FIMSC 0x44 +#define DB8500_GPIO_IS 0x48 +#define DB8500_GPIO_IC 0x4c +#define DB8500_GPIO_RWIMSC 0x50 +#define DB8500_GPIO_FWIMSC 0x54 +#define DB8500_GPIO_WKS 0x58 + +static void __iomem *get_gpio_addr(unsigned gpio) +{ + /* Our list of GPIO chips */ + static void __iomem *gpio_addrs[GPIO_BLOCKS_COUNT] = { + IO_ADDR(CFG_GPIO_0_BASE), + IO_ADDR(CFG_GPIO_1_BASE), + IO_ADDR(CFG_GPIO_2_BASE), + IO_ADDR(CFG_GPIO_3_BASE), + IO_ADDR(CFG_GPIO_4_BASE), + IO_ADDR(CFG_GPIO_5_BASE), + IO_ADDR(CFG_GPIO_6_BASE), + IO_ADDR(CFG_GPIO_7_BASE), + IO_ADDR(CFG_GPIO_8_BASE) + }; + + return gpio_addrs[GPIO_BLOCK(gpio)]; +} + +static unsigned get_gpio_offset(unsigned gpio) +{ + return GPIO_PIN_WITHIN_BLOCK(gpio); +} + +/* Can only be called from config_pin. Don't configure alt-mode directly */ +static void gpio_set_mode(unsigned gpio, enum db8500_gpio_alt mode) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + u32 bit = 1 << offset; + u32 afunc, bfunc; + + afunc = readl(addr + DB8500_GPIO_AFSLA) & ~bit; + bfunc = readl(addr + DB8500_GPIO_AFSLB) & ~bit; + if (mode & DB8500_GPIO_ALT_A) + afunc |= bit; + if (mode & DB8500_GPIO_ALT_B) + bfunc |= bit; + writel(afunc, addr + DB8500_GPIO_AFSLA); + writel(bfunc, addr + DB8500_GPIO_AFSLB); +} + +/** + * db8500_gpio_set_pull() - enable/disable pull up/down on a gpio + * @gpio: pin number + * @pull: one of DB8500_GPIO_PULL_DOWN, DB8500_GPIO_PULL_UP, + * and DB8500_GPIO_PULL_NONE + * + * Enables/disables pull up/down on a specified pin. This only takes effect if + * the pin is configured as an input (either explicitly or by the alternate + * function). + * + * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is + * configured as an input. Otherwise, due to the way the controller registers + * work, this function will change the value output on the pin. + */ +void db8500_gpio_set_pull(unsigned gpio, enum db8500_gpio_pull pull) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + u32 bit = 1 << offset; + u32 pdis; + + pdis = readl(addr + DB8500_GPIO_PDIS); + if (pull == DB8500_GPIO_PULL_NONE) + pdis |= bit; + else + pdis &= ~bit; + writel(pdis, addr + DB8500_GPIO_PDIS); + + if (pull == DB8500_GPIO_PULL_UP) + writel(bit, addr + DB8500_GPIO_DATS); + else if (pull == DB8500_GPIO_PULL_DOWN) + writel(bit, addr + DB8500_GPIO_DATC); +} + +void db8500_gpio_make_input(unsigned gpio) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + + writel(1 << offset, addr + DB8500_GPIO_DIRC); +} + +int db8500_gpio_get_input(unsigned gpio) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + u32 bit = 1 << offset; + + printf("db8500_gpio_get_input gpio=%u addr=%p offset=%u bit=%#x\n", + gpio, addr, offset, bit); + + return (readl(addr + DB8500_GPIO_DAT) & bit) != 0; +} + +void db8500_gpio_make_output(unsigned gpio, int val) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + + writel(1 << offset, addr + DB8500_GPIO_DIRS); + db8500_gpio_set_output(gpio, val); +} + +void db8500_gpio_set_output(unsigned gpio, int val) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + + if (val) + writel(1 << offset, addr + DB8500_GPIO_DATS); + else + writel(1 << offset, addr + DB8500_GPIO_DATC); +} + +/** + * config_pin - configure a pin's mux attributes + * @cfg: pin confguration + * + * Configures a pin's mode (alternate function or GPIO), its pull up status, + * and its sleep mode based on the specified configuration. The @cfg is + * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These + * are constructed using, and can be further enhanced with, the macros in + * plat/pincfg.h. + * + * If a pin's mode is set to GPIO, it is configured as an input to avoid + * side-effects. The gpio can be manipulated later using standard GPIO API + * calls. + */ +static void config_pin(pin_cfg_t cfg) +{ + int pin = PIN_NUM(cfg); + int pull = PIN_PULL(cfg); + int af = PIN_ALT(cfg); + int output = PIN_DIR(cfg); + int val = PIN_VAL(cfg); + + if (output) + db8500_gpio_make_output(pin, val); + else { + db8500_gpio_make_input(pin); + db8500_gpio_set_pull(pin, pull); + } + + gpio_set_mode(pin, af); +} + +/** + * db8500_config_pins - configure several pins at once + * @cfgs: array of pin configurations + * @num: number of elments in the array + * + * Configures several pins using config_pin(). Refer to that function for + * further information. + */ +void db8500_gpio_config_pins(pin_cfg_t *cfgs, size_t num) +{ + size_t i; + + for (i = 0; i < num; i++) + config_pin(cfgs[i]); +} diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index ed581ae..d4c5137 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -156,6 +156,8 @@ int serial_init (void) writel(lcr, ®s->fr); writel(lcr, ®s->pl011_rlcr); + /* lcrh needs to be set again for change to be effective */ + writel(lcr, ®s->pl011_lcrh); } #endif /* Finally, enable the UART */ diff --git a/include/configs/snowball.h b/include/configs/snowball.h new file mode 100644 index 0000000..845db29 --- /dev/null +++ b/include/configs/snowball.h @@ -0,0 +1,274 @@ +/* + * Copyright (C) ST-Ericsson SA 2009 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * #define DEBUG 1 + */ + +#define CONFIG_SKIP_LOWLEVEL_INIT 1 +#define CONFIG_SNOWBALL 1 +#define CONFIG_SYS_ICACHE_OFF 1 +#define CONFIG_SYS_DCACHE_OFF 1 + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_U8500 +#define CONFIG_L2_OFF + +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF +#define CONFIG_SYS_HZ 1000 /* must be 1000 */ + +/*----------------------------------------------------------------------- + * Size of environment and malloc() pool + */ +/* + * If you use U-Boot as crash kernel, make sure that it does not overwrite + * information saved by kexec during panic. Kexec expects the start + * address of the executable 32K above "crashkernel" address. + */ +/* + * Size of malloc() pool + */ +#ifdef CONFIG_BOOT_SRAM +#define CONFIG_ENV_SIZE (32*1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64*1024) +#else +#define CONFIG_ENV_SIZE (128*1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) +#endif + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */ + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV +#define CONFIG_ENV_OFFSET 0x0118000 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* SLOT2: eMMC */ + +/* + * PL011 Configuration + */ +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_SERIAL_RLCR +#define CONFIG_PL011_SERIAL_FLUSH_ON_INIT + +/* + * U8500 UART registers base for 3 serial devices + */ +#define CFG_UART0_BASE 0x80120000 +#define CFG_UART1_BASE 0x80121000 +#define CFG_UART2_BASE 0x80007000 +#define CFG_SERIAL0 CFG_UART0_BASE +#define CFG_SERIAL1 CFG_UART1_BASE +#define CFG_SERIAL2 CFG_UART2_BASE +#define CONFIG_PL011_CLOCK 38400000 +#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \ + (void *)CFG_SERIAL2 } +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Devices and file systems + */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION + +/* + * Commands + */ +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_BDI +#define CONFIG_CMD_IMI +#define CONFIG_CMD_MISC +#define CONFIG_CMD_RUN +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_CONSOLE +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_SOURCE + +#ifndef CONFIG_BOOTDELAY +#define CONFIG_BOOTDELAY 1 +#endif +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "mmc dev 1; " \ + "if run loadbootscript; " \ + "then run bootscript; " \ + "else " \ + "if run mmcload; " \ + "then run mmcboot; " \ + "else " \ + "mmc dev 0; " \ + "if run emmcloadbootscript; " \ + "then run bootscript; " \ + "else " \ + "if run emmcload; " \ + "then run emmcboot; " \ + "else " \ + "echo No media to boot from; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "fi; " + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr=0x00100000\0" \ + "console=ttyAMA2,115200n8\0" \ + "loadbootscript=fatload mmc 1:1 ${loadaddr} boot.scr\0" \ + "emmcloadbootscript=fatload mmc 0:2 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript " \ + "from mmc ...; source ${loadaddr}\0" \ + "memargs256=mem=96M at 0 mem_modem=32M at 96M mem=32M at 128M " \ + "hwmem=22M at 160M pmem_hwb=42M at 182M mem_mali=32 at 224M\0" \ + "memargs512=mem=96M at 0 mem_modem=32M at 96M hwmem=32M at 128M " \ + "mem=64M at 160M mem_mali=32M at 224M " \ + "pmem_hwb=128M at 256M mem=128M at 384M\0" \ + "memargs1024=mem=128M at 0 mali.mali_mem=32M at 128M " \ + "hwmem=168M at M160M mem=48M at 328M " \ + "mem_issw=1M at 383M mem=640M at 384M\0" \ + "memargs=setenv bootargs ${bootargs} ${memargs1024}\0" \ + "emmcload=fatload mmc 0:2 ${loadaddr} uImage\0" \ + "mmcload=fatload mmc 1:1 ${loadaddr} uImage\0" \ + "commonargs=setenv bootargs console=${console} " \ + "vmalloc=300M\0" \ + "emmcargs=setenv bootargs ${bootargs} " \ + "root=/dev/mmcblk0p3 " \ + "rootwait\0" \ + "addcons=setenv bootargs ${bootargs} " \ + "console=${console}\0" \ + "emmcboot=echo Booting from eMMC ...; " \ + "run commonargs emmcargs memargs; " \ + "bootm ${loadaddr}\0" \ + "mmcargs=setenv bootargs ${bootargs} " \ + "root=/dev/mmcblk1p2 " \ + "rootwait earlyprintk\0" \ + "mmcboot=echo Booting from external MMC ...; " \ + "run commonargs mmcargs memargs; " \ + "bootm ${loadaddr}\0" \ + "fdt_high=0x2BC00000\0" \ + "stdout=serial,usbtty\0" \ + "stdin=serial,usbtty\0" \ + "stderr=serial,usbtty\0" + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "U8500 $ " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 + +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_SETUP_MEMORY_TAGS 2 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ + +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */ +#define PHYS_SDRAM_SIZE_1 0x10000000 /* 256 MB */ + +/* + * additions for new relocation code + */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET + +/* landing address before relocation */ +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0x0 +#endif + +/* + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/* + * base register values for U8500 + */ +#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock */ + + +/* + * U8500 GPIO register base for 9 banks + */ +#define CONFIG_DB8500_GPIO +#define CFG_GPIO_0_BASE 0x8012E000 +#define CFG_GPIO_1_BASE 0x8012E080 +#define CFG_GPIO_2_BASE 0x8000E000 +#define CFG_GPIO_3_BASE 0x8000E080 +#define CFG_GPIO_4_BASE 0x8000E100 +#define CFG_GPIO_5_BASE 0x8000E180 +#define CFG_GPIO_6_BASE 0x8011E000 +#define CFG_GPIO_7_BASE 0x8011E080 +#define CFG_GPIO_8_BASE 0xA03FE000 + +#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */ + +#endif /* __CONFIG_H */ -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 01/11] snowball: Add support for ux500 based snowball board 2012-06-18 16:35 ` [U-Boot] [PATCH 01/11] snowball: Add support for ux500 based " mathieu.poirier at linaro.org @ 2012-06-18 17:59 ` Tom Rini 2012-06-18 22:16 ` Mathieu Poirier 0 siblings, 1 reply; 24+ messages in thread From: Tom Rini @ 2012-06-18 17:59 UTC (permalink / raw) To: u-boot On Mon, Jun 18, 2012 at 10:35:34AM -0600, mathieu.poirier at linaro.org wrote: [snip] > diff --git a/include/configs/snowball.h b/include/configs/snowball.h > new file mode 100644 > index 0000000..845db29 > --- /dev/null > +++ b/include/configs/snowball.h > @@ -0,0 +1,274 @@ > +/* > + * Copyright (C) ST-Ericsson SA 2009 > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +/* > + * #define DEBUG 1 > + */ > + > +#define CONFIG_SKIP_LOWLEVEL_INIT 1 > +#define CONFIG_SNOWBALL 1 > +#define CONFIG_SYS_ICACHE_OFF 1 > +#define CONFIG_SYS_DCACHE_OFF 1 Whitespace and just do '#define CONFIG_FOO' not '#define CONFIG_FOO 1'. [snip] > +#ifdef CONFIG_BOOT_SRAM > +#define CONFIG_ENV_SIZE (32*1024) > +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64*1024) > +#else > +#define CONFIG_ENV_SIZE (128*1024) > +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) > +#endif I assume you build a U-Boot for an initial loader and then a fuller U-Boot that runs in DRAM? This is what SPL is for and I hope you will convert at some point :) [snip] > +/* > + * Stack sizes > + * > + * The stack sizes are set up in start.S using the settings below > + */ > + > +#ifdef CONFIG_USE_IRQ > +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ > +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ > +#endif I don't believe CONFIG_USE_IRQ was set, so these shouldn't be here. -- Tom ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 01/11] snowball: Add support for ux500 based snowball board 2012-06-18 17:59 ` Tom Rini @ 2012-06-18 22:16 ` Mathieu Poirier 0 siblings, 0 replies; 24+ messages in thread From: Mathieu Poirier @ 2012-06-18 22:16 UTC (permalink / raw) To: u-boot On 12-06-18 11:59 AM, Tom Rini wrote: > On Mon, Jun 18, 2012 at 10:35:34AM -0600, mathieu.poirier at linaro.org wrote: > > [snip] >> diff --git a/include/configs/snowball.h b/include/configs/snowball.h >> new file mode 100644 >> index 0000000..845db29 >> --- /dev/null >> +++ b/include/configs/snowball.h >> @@ -0,0 +1,274 @@ >> +/* >> + * Copyright (C) ST-Ericsson SA 2009 >> + * >> + * See file CREDITS for list of people who contributed to this >> + * project. >> + * >> + * This program is free software; you can redistribute it and/or >> + * modify it under the terms of the GNU General Public License as >> + * published by the Free Software Foundation; either version 2 of >> + * the License, or (at your option) any later version. >> + * >> + * This program is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * You should have received a copy of the GNU General Public License >> + * along with this program; if not, write to the Free Software >> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, >> + * MA 02111-1307 USA >> + */ >> + >> +#ifndef __CONFIG_H >> +#define __CONFIG_H >> + >> +/* >> + * #define DEBUG 1 >> + */ >> + >> +#define CONFIG_SKIP_LOWLEVEL_INIT 1 >> +#define CONFIG_SNOWBALL 1 >> +#define CONFIG_SYS_ICACHE_OFF 1 >> +#define CONFIG_SYS_DCACHE_OFF 1 > > Whitespace and just do '#define CONFIG_FOO' not '#define CONFIG_FOO 1'. Weird, checkpatch.pl didn't complain. > > [snip] >> +#ifdef CONFIG_BOOT_SRAM >> +#define CONFIG_ENV_SIZE (32*1024) >> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64*1024) >> +#else >> +#define CONFIG_ENV_SIZE (128*1024) >> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) >> +#endif > > I assume you build a U-Boot for an initial loader and then a fuller > U-Boot that runs in DRAM? This is what SPL is for and I hope you will > convert at some point :) This board has a SPL but it is not compiled from this code base. I will remove the extra lines. > > [snip] >> +/* >> + * Stack sizes >> + * >> + * The stack sizes are set up in start.S using the settings below >> + */ >> + >> +#ifdef CONFIG_USE_IRQ >> +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ >> +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ >> +#endif > > I don't believe CONFIG_USE_IRQ was set, so these shouldn't be here. Correct - IRQs aren't used. > ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 00/11] support for ST-Ericsson snowball board @ 2012-06-18 16:25 mathieu.poirier at linaro.org 2012-06-18 16:25 ` [U-Boot] [PATCH 01/11] snowball: Add support for ux500 based " mathieu.poirier at linaro.org 0 siblings, 1 reply; 24+ messages in thread From: mathieu.poirier at linaro.org @ 2012-06-18 16:25 UTC (permalink / raw) To: u-boot From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org> This set adds support for the ST-Ericsson u8500 based snowball board. Doing so it moves u8500-href code around to allow for code reuse. John Rigby (1): u8500: Separating mmc config parameters from driver Mathieu J. Poirier (10): snowball: Add support for ux500 based snowball board u8500: Moving prcmu to cpu directory snowball: Adding architecture dependent initialisation snowball: Adding CPU clock initialisation snowball: Moving to ux500.v2 addess scheme for PRCMU access snowball: applying power to LAN and GBF controllers u8500: Moving processor-specific functions to cpu area. u8500: Enabling power to MMC device on AB8500 V2 armv7: Adding cpu specific cache managmenent snowball: Adding board specific cache cleanup routine arch/arm/cpu/armv7/cpu.c | 9 + arch/arm/cpu/armv7/u8500/Makefile | 2 +- arch/arm/cpu/armv7/u8500/clock.c | 34 + arch/arm/cpu/armv7/u8500/cpu.c | 175 ++++++ arch/arm/cpu/armv7/u8500/prcmu.c | 229 +++++++ arch/arm/include/asm/arch-u8500/clock.h | 5 +- arch/arm/include/asm/arch-u8500/db8500_gpio.h | 42 ++ arch/arm/include/asm/arch-u8500/db8500_pincfg.h | 172 ++++++ arch/arm/include/asm/arch-u8500/hardware.h | 33 +- arch/arm/include/asm/arch-u8500/prcmu.h | 76 +++ arch/arm/include/asm/arch-u8500/sys_proto.h | 1 + board/armltd/vexpress/ca9x4_ct_vxp.c | 21 +- board/st-ericsson/snowball/Makefile | 51 ++ board/st-ericsson/snowball/db8500_pins.h | 745 +++++++++++++++++++++++ board/st-ericsson/snowball/snowball.c | 367 +++++++++++ board/st-ericsson/u8500/Makefile | 2 +- board/st-ericsson/u8500/prcmu-fw.h | 55 -- board/st-ericsson/u8500/prcmu.c | 165 ----- board/st-ericsson/u8500/u8500_href.c | 99 +--- boards.cfg | 1 + drivers/gpio/Makefile | 1 + drivers/gpio/db8500_gpio.c | 225 +++++++ drivers/mmc/arm_pl180_mmci.c | 132 ++--- drivers/mmc/arm_pl180_mmci.h | 27 +- drivers/serial/serial_pl01x.c | 2 + include/configs/snowball.h | 283 +++++++++ 26 files changed, 2563 insertions(+), 391 deletions(-) create mode 100644 arch/arm/cpu/armv7/u8500/cpu.c create mode 100644 arch/arm/cpu/armv7/u8500/prcmu.c create mode 100644 arch/arm/include/asm/arch-u8500/db8500_gpio.h create mode 100644 arch/arm/include/asm/arch-u8500/db8500_pincfg.h create mode 100644 arch/arm/include/asm/arch-u8500/prcmu.h create mode 100644 board/st-ericsson/snowball/Makefile create mode 100644 board/st-ericsson/snowball/db8500_pins.h create mode 100644 board/st-ericsson/snowball/snowball.c delete mode 100644 board/st-ericsson/u8500/prcmu-fw.h delete mode 100644 board/st-ericsson/u8500/prcmu.c create mode 100644 drivers/gpio/db8500_gpio.c create mode 100644 include/configs/snowball.h -- 1.7.5.4 ^ permalink raw reply [flat|nested] 24+ messages in thread
* [U-Boot] [PATCH 01/11] snowball: Add support for ux500 based snowball board 2012-06-18 16:25 [U-Boot] [PATCH 00/11] support for ST-Ericsson " mathieu.poirier at linaro.org @ 2012-06-18 16:25 ` mathieu.poirier at linaro.org 0 siblings, 0 replies; 24+ messages in thread From: mathieu.poirier at linaro.org @ 2012-06-18 16:25 UTC (permalink / raw) To: u-boot From: "Mathieu J. Poirier" <mathieu.poirier@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> --- arch/arm/include/asm/arch-u8500/db8500_gpio.h | 42 ++ arch/arm/include/asm/arch-u8500/db8500_pincfg.h | 172 ++++++ board/st-ericsson/snowball/Makefile | 51 ++ board/st-ericsson/snowball/db8500_pins.h | 745 +++++++++++++++++++++++ board/st-ericsson/snowball/snowball.c | 185 ++++++ boards.cfg | 1 + drivers/gpio/Makefile | 1 + drivers/gpio/db8500_gpio.c | 225 +++++++ drivers/serial/serial_pl01x.c | 2 + include/configs/snowball.h | 274 +++++++++ 10 files changed, 1698 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-u8500/db8500_gpio.h b/arch/arm/include/asm/arch-u8500/db8500_gpio.h new file mode 100644 index 0000000..7c85a89 --- /dev/null +++ b/arch/arm/include/asm/arch-u8500/db8500_gpio.h @@ -0,0 +1,42 @@ +/* + * Structures and registers for GPIO access in the Nomadik SoC + * + * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. + * The purpose is that GPIO config found in kernel should work by simply + * copy-paste it to U-boot. + * + * Ported to U-boot by: + * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com> + * Copyright (C) 2008 STMicroelectronics + * Author: Prafulla WADASKAR <prafulla.wadaskar@st.com> + * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DB8500_GPIO_H__ +#define __DB8500_GPIO_H__ + +/* Alternate functions: function C is set in hw by setting both A and B */ +enum db8500_gpio_alt { + DB8500_GPIO_ALT_GPIO = 0, + DB8500_GPIO_ALT_A = 1, + DB8500_GPIO_ALT_B = 2, + DB8500_GPIO_ALT_C = (DB8500_GPIO_ALT_A | DB8500_GPIO_ALT_B) +}; + +enum db8500_gpio_pull { + DB8500_GPIO_PULL_NONE, + DB8500_GPIO_PULL_UP, + DB8500_GPIO_PULL_DOWN +}; + +void db8500_gpio_set_pull(unsigned gpio, enum db8500_gpio_pull pull); +void db8500_gpio_make_input(unsigned gpio); +int db8500_gpio_get_input(unsigned gpio); +void db8500_gpio_make_output(unsigned gpio, int val); +void db8500_gpio_set_output(unsigned gpio, int val); + +#endif /* __DB8500_GPIO_H__ */ diff --git a/arch/arm/include/asm/arch-u8500/db8500_pincfg.h b/arch/arm/include/asm/arch-u8500/db8500_pincfg.h new file mode 100644 index 0000000..137377d --- /dev/null +++ b/arch/arm/include/asm/arch-u8500/db8500_pincfg.h @@ -0,0 +1,172 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. + * The purpose is that GPIO config found in kernel should work by simply + * copy-paste it to U-boot. Ported 2010 to U-boot by: + * Author: Joakim Axelsson <joakim.axelsson AT stericsson.com> + * + * License terms: GNU General Public License, version 2 + * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson + * + * + * Based on arch/arm/mach-pxa/include/mach/mfp.h: + * Copyright (C) 2007 Marvell International Ltd. + * eric miao <eric.miao@marvell.com> + */ + +#ifndef __DB8500_PINCFG_H +#define __DB8500_PINCFG_H + +#include "db8500_gpio.h" + +/* + * U-boot info: + * SLPM (sleep mode) config will be ignored by U-boot but it is still + * possible to configure it in order to keep cut-n-paste compability + * with Linux kernel config. + * + * pin configurations are represented by 32-bit integers: + * + * bit 0.. 8 - Pin Number (512 Pins Maximum) + * bit 9..10 - Alternate Function Selection + * bit 11..12 - Pull up/down state + * bit 13 - Sleep mode behaviour (not used in U-boot) + * bit 14 - Direction + * bit 15 - Value (if output) + * bit 16..18 - SLPM pull up/down state (not used in U-boot) + * bit 19..20 - SLPM direction (not used in U-boot) + * bit 21..22 - SLPM Value (if output) (not used in U-boot) + * + * to facilitate the definition, the following macros are provided + * + * PIN_CFG_DEFAULT - default config (0): + * pull up/down = disabled + * sleep mode = input/wakeup + * direction = input + * value = low + * SLPM direction = same as normal + * SLPM pull = same as normal + * SLPM value = same as normal + * + * PIN_CFG - default config with alternate function + * PIN_CFG_PULL - default config with alternate function and pull up/down + */ + +typedef unsigned long pin_cfg_t; + +/* Sleep mode */ +enum db8500_gpio_slpm { + DB8500_GPIO_SLPM_INPUT, + DB8500_GPIO_SLPM_WAKEUP_ENABLE = DB8500_GPIO_SLPM_INPUT, + DB8500_GPIO_SLPM_NOCHANGE, + DB8500_GPIO_SLPM_WAKEUP_DISABLE = DB8500_GPIO_SLPM_NOCHANGE, +}; + +#define PIN_NUM_MASK 0x1ff +#define PIN_NUM(x) ((x) & PIN_NUM_MASK) + +#define PIN_ALT_SHIFT 9 +#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT) +#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT) +#define PIN_GPIO (DB8500_GPIO_ALT_GPIO << PIN_ALT_SHIFT) +#define PIN_ALT_A (DB8500_GPIO_ALT_A << PIN_ALT_SHIFT) +#define PIN_ALT_B (DB8500_GPIO_ALT_B << PIN_ALT_SHIFT) +#define PIN_ALT_C (DB8500_GPIO_ALT_C << PIN_ALT_SHIFT) + +#define PIN_PULL_SHIFT 11 +#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT) +#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT) +#define PIN_PULL_NONE (DB8500_GPIO_PULL_NONE << PIN_PULL_SHIFT) +#define PIN_PULL_UP (DB8500_GPIO_PULL_UP << PIN_PULL_SHIFT) +#define PIN_PULL_DOWN (DB8500_GPIO_PULL_DOWN << PIN_PULL_SHIFT) + +#define PIN_SLPM_SHIFT 13 +#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) +#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) +#define PIN_SLPM_MAKE_INPUT (DB8500_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) +#define PIN_SLPM_NOCHANGE (DB8500_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) +/* These two replace the above in DB8500v2+ */ +#define PIN_SLPM_WAKEUP_ENABLE \ + (DB8500_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) +#define PIN_SLPM_WAKEUP_DISABLE \ + (DB8500_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) + +#define PIN_DIR_SHIFT 14 +#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) +#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT) +#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT) +#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT) + +#define PIN_VAL_SHIFT 15 +#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT) +#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT) +#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) +#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) + +#define PIN_SLPM_PULL_SHIFT 16 +#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL(x) \ + (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL_NONE \ + ((1 + DB8500_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL_UP \ + ((1 + DB8500_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) +#define PIN_SLPM_PULL_DOWN \ + ((1 + DB8500_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) + +#define PIN_SLPM_DIR_SHIFT 19 +#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) +#define PIN_SLPM_DIR(x) \ + (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) +#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) +#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) + +#define PIN_SLPM_VAL_SHIFT 21 +#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) +#define PIN_SLPM_VAL(x) \ + (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) +#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) +#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) + +/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ +#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) +#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) +#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) +#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) +#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) + +#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) +#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) +#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) +#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) +#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) + +#define PIN_CFG_DEFAULT (0) + +#define PIN_CFG(num, alt) \ + (PIN_CFG_DEFAULT |\ + (PIN_NUM(num) | PIN_##alt)) + +#define PIN_CFG_INPUT(num, alt, pull) \ + (PIN_CFG_DEFAULT |\ + (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) + +#define PIN_CFG_OUTPUT(num, alt, val) \ + (PIN_CFG_DEFAULT |\ + (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) + +#define PIN_CFG_PULL(num, alt, pull) \ + ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\ + (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull)) + +/** + * db8500_gpio_config_pins - configure several pins@once + * @cfgs: array of pin configurations + * @num: number of elments in the array + * + * Configures several GPIO pins. + */ +void db8500_gpio_config_pins(pin_cfg_t *cfgs, size_t num); + +#endif diff --git a/board/st-ericsson/snowball/Makefile b/board/st-ericsson/snowball/Makefile new file mode 100644 index 0000000..6138296 --- /dev/null +++ b/board/st-ericsson/snowball/Makefile @@ -0,0 +1,51 @@ +# +# Copyright (C) ST-Ericsson SA 2009 +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +CFLAGS += -D__RELEASE -D__STN_8500 +LIB = $(obj)lib$(BOARD).o + +COBJS := snowball.o + +#prcmu.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/st-ericsson/snowball/db8500_pins.h b/board/st-ericsson/snowball/db8500_pins.h new file mode 100644 index 0000000..e339cb8 --- /dev/null +++ b/board/st-ericsson/snowball/db8500_pins.h @@ -0,0 +1,745 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. + * The purpose is that GPIO config found in kernel should work by simply + * copy-paste it to U-boot. + * + * Ported to U-boot by: + * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com> + ** + * License terms: GNU General Public License, version 2 + * Author: Rabin Vincent <rabin.vincent@stericsson.com> + */ + +#ifndef __DB8500_PINS_H +#define __DB8500_PINS_H + +#include <asm/arch/db8500_pincfg.h> + +#define GPIO0_GPIO PIN_CFG(0, GPIO) +#define GPIO0_U0_CTSn PIN_CFG(0, ALT_A) +#define GPIO0_TRIG_OUT PIN_CFG(0, ALT_B) +#define GPIO0_IP_TDO PIN_CFG(0, ALT_C) + +#define GPIO1_GPIO PIN_CFG(1, GPIO) +#define GPIO1_U0_RTSn PIN_CFG(1, ALT_A) +#define GPIO1_TRIG_IN PIN_CFG(1, ALT_B) +#define GPIO1_IP_TDI PIN_CFG(1, ALT_C) + +#define GPIO2_GPIO PIN_CFG(2, GPIO) +#define GPIO2_U0_RXD PIN_CFG(2, ALT_A) +#define GPIO2_NONE PIN_CFG(2, ALT_B) +#define GPIO2_IP_TMS PIN_CFG(2, ALT_C) + +#define GPIO3_GPIO PIN_CFG(3, GPIO) +#define GPIO3_U0_TXD PIN_CFG(3, ALT_A) +#define GPIO3_NONE PIN_CFG(3, ALT_B) +#define GPIO3_IP_TCK PIN_CFG(3, ALT_C) + +#define GPIO4_GPIO PIN_CFG(4, GPIO) +#define GPIO4_U1_RXD PIN_CFG(4, ALT_A) +#define GPIO4_I2C4_SCL PIN_CFG_PULL(4, ALT_B, UP) +#define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C) + +#define GPIO5_GPIO PIN_CFG(5, GPIO) +#define GPIO5_U1_TXD PIN_CFG(5, ALT_A) +#define GPIO5_I2C4_SDA PIN_CFG_PULL(5, ALT_B, UP) +#define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C) + +#define GPIO6_GPIO PIN_CFG(6, GPIO) +#define GPIO6_U1_CTSn PIN_CFG(6, ALT_A) +#define GPIO6_I2C1_SCL PIN_CFG_PULL(6, ALT_B, UP) +#define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C) + +#define GPIO7_GPIO PIN_CFG(7, GPIO) +#define GPIO7_U1_RTSn PIN_CFG(7, ALT_A) +#define GPIO7_I2C1_SDA PIN_CFG_PULL(7, ALT_B, UP) +#define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C) + +#define GPIO8_GPIO PIN_CFG(8, GPIO) +#define GPIO8_IPI2C_SDA PIN_CFG_PULL(8, ALT_A, UP) +#define GPIO8_I2C2_SDA PIN_CFG_PULL(8, ALT_B, UP) + +#define GPIO9_GPIO PIN_CFG(9, GPIO) +#define GPIO9_IPI2C_SCL PIN_CFG_PULL(9, ALT_A, UP) +#define GPIO9_I2C2_SCL PIN_CFG_PULL(9, ALT_B, UP) + +#define GPIO10_GPIO PIN_CFG(10, GPIO) +#define GPIO10_IPI2C_SDA PIN_CFG_PULL(10, ALT_A, UP) +#define GPIO10_I2C2_SDA PIN_CFG_PULL(10, ALT_B, UP) +#define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C) + +#define GPIO11_GPIO PIN_CFG(11, GPIO) +#define GPIO11_IPI2C_SCL PIN_CFG_PULL(11, ALT_A, UP) +#define GPIO11_I2C2_SCL PIN_CFG_PULL(11, ALT_B, UP) +#define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C) + +#define GPIO12_GPIO PIN_CFG(12, GPIO) +#define GPIO12_MSP0_TXD PIN_CFG(12, ALT_A) +#define GPIO12_MSP0_RXD PIN_CFG(12, ALT_B) + +#define GPIO13_GPIO PIN_CFG(13, GPIO) +#define GPIO13_MSP0_TFS PIN_CFG(13, ALT_A) + +#define GPIO14_GPIO PIN_CFG(14, GPIO) +#define GPIO14_MSP0_TCK PIN_CFG(14, ALT_A) + +#define GPIO15_GPIO PIN_CFG(15, GPIO) +#define GPIO15_MSP0_RXD PIN_CFG(15, ALT_A) +#define GPIO15_MSP0_TXD PIN_CFG(15, ALT_B) + +#define GPIO16_GPIO PIN_CFG(16, GPIO) +#define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A) +#define GPIO16_I2C1_SCL PIN_CFG_PULL(16, ALT_B, UP) +#define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C) + +#define GPIO17_GPIO PIN_CFG(17, GPIO) +#define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A) +#define GPIO17_I2C1_SDA PIN_CFG_PULL(17, ALT_B, UP) +#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C) + +#define GPIO18_GPIO PIN_CFG(18, GPIO) +#define GPIO18_MC0_CMDDIR PIN_CFG(18, ALT_A) +#define GPIO18_U2_RXD PIN_CFG(18, ALT_B) +#define GPIO18_MS_IEP PIN_CFG(18, ALT_C) + +#define GPIO19_GPIO PIN_CFG(19, GPIO) +#define GPIO19_MC0_DAT0DIR PIN_CFG(19, ALT_A) +#define GPIO19_U2_TXD PIN_CFG(19, ALT_B) +#define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C) + +#define GPIO20_GPIO PIN_CFG(20, GPIO) +#define GPIO20_MC0_DAT2DIR PIN_CFG(20, ALT_A) +#define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B) +#define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C) + +#define GPIO21_GPIO PIN_CFG(21, GPIO) +#define GPIO21_MC0_DAT31DIR PIN_CFG(21, ALT_A) +#define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B) +#define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C) + +#define GPIO22_GPIO PIN_CFG(22, GPIO) +#define GPIO22_MC0_FBCLK PIN_CFG(22, ALT_A) +#define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B) +#define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C) + +#define GPIO23_GPIO PIN_CFG(23, GPIO) +#define GPIO23_MC0_CLK PIN_CFG(23, ALT_A) +#define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B) +#define GPIO23_MS_CLK PIN_CFG(23, ALT_C) + +#define GPIO24_GPIO PIN_CFG(24, GPIO) +#define GPIO24_MC0_CMD PIN_CFG(24, ALT_A) +#define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B) +#define GPIO24_MS_BS PIN_CFG(24, ALT_C) + +#define GPIO25_GPIO PIN_CFG(25, GPIO) +#define GPIO25_MC0_DAT0 PIN_CFG(25, ALT_A) +#define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B) +#define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C) + +#define GPIO26_GPIO PIN_CFG(26, GPIO) +#define GPIO26_MC0_DAT1 PIN_CFG(26, ALT_A) +#define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B) +#define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C) + +#define GPIO27_GPIO PIN_CFG(27, GPIO) +#define GPIO27_MC0_DAT2 PIN_CFG(27, ALT_A) +#define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B) +#define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C) + +#define GPIO28_GPIO PIN_CFG(28, GPIO) +#define GPIO28_MC0_DAT3 PIN_CFG(28, ALT_A) +#define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B) +#define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C) + +#define GPIO29_GPIO PIN_CFG(29, GPIO) +#define GPIO29_MC0_DAT4 PIN_CFG(29, ALT_A) +#define GPIO29_SPI3_CLK PIN_CFG(29, ALT_B) +#define GPIO29_U2_RXD PIN_CFG(29, ALT_C) + +#define GPIO30_GPIO PIN_CFG(30, GPIO) +#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A) +#define GPIO30_SPI3_RXD PIN_CFG(30, ALT_B) +#define GPIO30_U2_TXD PIN_CFG(30, ALT_C) + +#define GPIO31_GPIO PIN_CFG(31, GPIO) +#define GPIO31_MC0_DAT6 PIN_CFG(31, ALT_A) +#define GPIO31_SPI3_FRM PIN_CFG(31, ALT_B) +#define GPIO31_U2_CTSn PIN_CFG(31, ALT_C) + +#define GPIO32_GPIO PIN_CFG(32, GPIO) +#define GPIO32_MC0_DAT7 PIN_CFG(32, ALT_A) +#define GPIO32_SPI3_TXD PIN_CFG(32, ALT_B) +#define GPIO32_U2_RTSn PIN_CFG(32, ALT_C) + +#define GPIO33_GPIO PIN_CFG(33, GPIO) +#define GPIO33_MSP1_TXD PIN_CFG(33, ALT_A) +#define GPIO33_MSP1_RXD PIN_CFG(33, ALT_B) +#define GPIO33_U0_DTRn PIN_CFG(33, ALT_C) + +#define GPIO34_GPIO PIN_CFG(34, GPIO) +#define GPIO34_MSP1_TFS PIN_CFG(34, ALT_A) +#define GPIO34_NONE PIN_CFG(34, ALT_B) +#define GPIO34_U0_DCDn PIN_CFG(34, ALT_C) + +#define GPIO35_GPIO PIN_CFG(35, GPIO) +#define GPIO35_MSP1_TCK PIN_CFG(35, ALT_A) +#define GPIO35_NONE PIN_CFG(35, ALT_B) +#define GPIO35_U0_DSRn PIN_CFG(35, ALT_C) + +#define GPIO36_GPIO PIN_CFG(36, GPIO) +#define GPIO36_MSP1_RXD PIN_CFG(36, ALT_A) +#define GPIO36_MSP1_TXD PIN_CFG(36, ALT_B) +#define GPIO36_U0_RIn PIN_CFG(36, ALT_C) + +#define GPIO64_GPIO PIN_CFG(64, GPIO) +#define GPIO64_LCDB_DE PIN_CFG(64, ALT_A) +#define GPIO64_KP_O1 PIN_CFG(64, ALT_B) +#define GPIO64_IP_GPIO4 PIN_CFG(64, ALT_C) + +#define GPIO65_GPIO PIN_CFG(65, GPIO) +#define GPIO65_LCDB_HSO PIN_CFG(65, ALT_A) +#define GPIO65_KP_O0 PIN_CFG(65, ALT_B) +#define GPIO65_IP_GPIO5 PIN_CFG(65, ALT_C) + +#define GPIO66_GPIO PIN_CFG(66, GPIO) +#define GPIO66_LCDB_VSO PIN_CFG(66, ALT_A) +#define GPIO66_KP_I1 PIN_CFG(66, ALT_B) +#define GPIO66_IP_GPIO6 PIN_CFG(66, ALT_C) + +#define GPIO67_GPIO PIN_CFG(67, GPIO) +#define GPIO67_LCDB_CLK PIN_CFG(67, ALT_A) +#define GPIO67_KP_I0 PIN_CFG(67, ALT_B) +#define GPIO67_IP_GPIO7 PIN_CFG(67, ALT_C) + +#define GPIO68_GPIO PIN_CFG(68, GPIO) +#define GPIO68_LCD_VSI0 PIN_CFG(68, ALT_A) +#define GPIO68_KP_O7 PIN_CFG(68, ALT_B) +#define GPIO68_SM_CLE PIN_CFG(68, ALT_C) + +#define GPIO69_GPIO PIN_CFG(69, GPIO) +#define GPIO69_LCD_VSI1 PIN_CFG(69, ALT_A) +#define GPIO69_KP_I7 PIN_CFG(69, ALT_B) +#define GPIO69_SM_ALE PIN_CFG(69, ALT_C) + +#define GPIO70_GPIO PIN_CFG(70, GPIO) +#define GPIO70_LCD_D0 PIN_CFG(70, ALT_A) +#define GPIO70_KP_O5 PIN_CFG(70, ALT_B) +#define GPIO70_STMAPE_CLK PIN_CFG(70, ALT_C) + +#define GPIO71_GPIO PIN_CFG(71, GPIO) +#define GPIO71_LCD_D1 PIN_CFG(71, ALT_A) +#define GPIO71_KP_O4 PIN_CFG(71, ALT_B) +#define GPIO71_STMAPE_DAT3 PIN_CFG(71, ALT_C) + +#define GPIO72_GPIO PIN_CFG(72, GPIO) +#define GPIO72_LCD_D2 PIN_CFG(72, ALT_A) +#define GPIO72_KP_O3 PIN_CFG(72, ALT_B) +#define GPIO72_STMAPE_DAT2 PIN_CFG(72, ALT_C) + +#define GPIO73_GPIO PIN_CFG(73, GPIO) +#define GPIO73_LCD_D3 PIN_CFG(73, ALT_A) +#define GPIO73_KP_O2 PIN_CFG(73, ALT_B) +#define GPIO73_STMAPE_DAT1 PIN_CFG(73, ALT_C) + +#define GPIO74_GPIO PIN_CFG(74, GPIO) +#define GPIO74_LCD_D4 PIN_CFG(74, ALT_A) +#define GPIO74_KP_I5 PIN_CFG(74, ALT_B) +#define GPIO74_STMAPE_DAT0 PIN_CFG(74, ALT_C) + +#define GPIO75_GPIO PIN_CFG(75, GPIO) +#define GPIO75_LCD_D5 PIN_CFG(75, ALT_A) +#define GPIO75_KP_I4 PIN_CFG(75, ALT_B) +#define GPIO75_U2_RXD PIN_CFG(75, ALT_C) + +#define GPIO76_GPIO PIN_CFG(76, GPIO) +#define GPIO76_LCD_D6 PIN_CFG(76, ALT_A) +#define GPIO76_KP_I3 PIN_CFG(76, ALT_B) +#define GPIO76_U2_TXD PIN_CFG(76, ALT_C) + +#define GPIO77_GPIO PIN_CFG(77, GPIO) +#define GPIO77_LCD_D7 PIN_CFG(77, ALT_A) +#define GPIO77_KP_I2 PIN_CFG(77, ALT_B) +#define GPIO77_NONE PIN_CFG(77, ALT_C) + +#define GPIO78_GPIO PIN_CFG(78, GPIO) +#define GPIO78_LCD_D8 PIN_CFG(78, ALT_A) +#define GPIO78_KP_O6 PIN_CFG(78, ALT_B) +#define GPIO78_IP_GPIO2 PIN_CFG(78, ALT_C) + +#define GPIO79_GPIO PIN_CFG(79, GPIO) +#define GPIO79_LCD_D9 PIN_CFG(79, ALT_A) +#define GPIO79_KP_I6 PIN_CFG(79, ALT_B) +#define GPIO79_IP_GPIO3 PIN_CFG(79, ALT_C) + +#define GPIO80_GPIO PIN_CFG(80, GPIO) +#define GPIO80_LCD_D10 PIN_CFG(80, ALT_A) +#define GPIO80_KP_SKA0 PIN_CFG(80, ALT_B) +#define GPIO80_IP_GPIO4 PIN_CFG(80, ALT_C) + +#define GPIO81_GPIO PIN_CFG(81, GPIO) +#define GPIO81_LCD_D11 PIN_CFG(81, ALT_A) +#define GPIO81_KP_SKB0 PIN_CFG(81, ALT_B) +#define GPIO81_IP_GPIO5 PIN_CFG(81, ALT_C) + +#define GPIO82_GPIO PIN_CFG(82, GPIO) +#define GPIO82_LCD_D12 PIN_CFG(82, ALT_A) +#define GPIO82_KP_O5 PIN_CFG(82, ALT_B) + +#define GPIO83_GPIO PIN_CFG(83, GPIO) +#define GPIO83_LCD_D13 PIN_CFG(83, ALT_A) +#define GPIO83_KP_O4 PIN_CFG(83, ALT_B) + +#define GPIO84_GPIO PIN_CFG_PULL(84, GPIO, UP) +#define GPIO84_LCD_D14 PIN_CFG(84, ALT_A) +#define GPIO84_KP_I5 PIN_CFG(84, ALT_B) + +#define GPIO85_GPIO PIN_CFG(85, GPIO) +#define GPIO85_LCD_D15 PIN_CFG(85, ALT_A) +#define GPIO85_KP_I4 PIN_CFG(85, ALT_B) + +#define GPIO86_GPIO PIN_CFG(86, GPIO) +#define GPIO86_LCD_D16 PIN_CFG(86, ALT_A) +#define GPIO86_SM_ADQ0 PIN_CFG(86, ALT_B) +#define GPIO86_MC5_DAT0 PIN_CFG(86, ALT_C) + +#define GPIO87_GPIO PIN_CFG(87, GPIO) +#define GPIO87_LCD_D17 PIN_CFG(87, ALT_A) +#define GPIO87_SM_ADQ1 PIN_CFG(87, ALT_B) +#define GPIO87_MC5_DAT1 PIN_CFG(87, ALT_C) + +#define GPIO88_GPIO PIN_CFG(88, GPIO) +#define GPIO88_LCD_D18 PIN_CFG(88, ALT_A) +#define GPIO88_SM_ADQ2 PIN_CFG(88, ALT_B) +#define GPIO88_MC5_DAT2 PIN_CFG(88, ALT_C) + +#define GPIO89_GPIO PIN_CFG(89, GPIO) +#define GPIO89_LCD_D19 PIN_CFG(89, ALT_A) +#define GPIO89_SM_ADQ3 PIN_CFG(89, ALT_B) +#define GPIO89_MC5_DAT3 PIN_CFG(89, ALT_C) + +#define GPIO90_GPIO PIN_CFG(90, GPIO) +#define GPIO90_LCD_D20 PIN_CFG(90, ALT_A) +#define GPIO90_SM_ADQ4 PIN_CFG(90, ALT_B) +#define GPIO90_MC5_CMD PIN_CFG(90, ALT_C) + +#define GPIO91_GPIO PIN_CFG(91, GPIO) +#define GPIO91_LCD_D21 PIN_CFG(91, ALT_A) +#define GPIO91_SM_ADQ5 PIN_CFG(91, ALT_B) +#define GPIO91_MC5_FBCLK PIN_CFG(91, ALT_C) + +#define GPIO92_GPIO PIN_CFG(92, GPIO) +#define GPIO92_LCD_D22 PIN_CFG(92, ALT_A) +#define GPIO92_SM_ADQ6 PIN_CFG(92, ALT_B) +#define GPIO92_MC5_CLK PIN_CFG(92, ALT_C) + +#define GPIO93_GPIO PIN_CFG(93, GPIO) +#define GPIO93_LCD_D23 PIN_CFG(93, ALT_A) +#define GPIO93_SM_ADQ7 PIN_CFG(93, ALT_B) +#define GPIO93_MC5_DAT4 PIN_CFG(93, ALT_C) + +#define GPIO94_GPIO PIN_CFG(94, GPIO) +#define GPIO94_KP_O7 PIN_CFG(94, ALT_A) +#define GPIO94_SM_ADVn PIN_CFG(94, ALT_B) +#define GPIO94_MC5_DAT5 PIN_CFG(94, ALT_C) + +#define GPIO95_GPIO PIN_CFG(95, GPIO) +#define GPIO95_KP_I7 PIN_CFG(95, ALT_A) +#define GPIO95_SM_CS0n PIN_CFG(95, ALT_B) +#define GPIO95_SM_PS0n PIN_CFG(95, ALT_C) + +#define GPIO96_GPIO PIN_CFG(96, GPIO) +#define GPIO96_KP_O6 PIN_CFG(96, ALT_A) +#define GPIO96_SM_OEn PIN_CFG(96, ALT_B) +#define GPIO96_MC5_DAT6 PIN_CFG(96, ALT_C) + +#define GPIO97_GPIO PIN_CFG(97, GPIO) +#define GPIO97_KP_I6 PIN_CFG(97, ALT_A) +#define GPIO97_SM_WEn PIN_CFG(97, ALT_B) +#define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C) + +#define GPIO128_GPIO PIN_CFG(128, GPIO) +#define GPIO128_MC2_CLK PIN_CFG(128, ALT_A) +#define GPIO128_SM_CKO PIN_CFG(128, ALT_B) + +#define GPIO129_GPIO PIN_CFG(129, GPIO) +#define GPIO129_MC2_CMD PIN_CFG(129, ALT_A) +#define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B) + +#define GPIO130_GPIO PIN_CFG(130, GPIO) +#define GPIO130_MC2_FBCLK PIN_CFG(130, ALT_A) +#define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B) +#define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C) + +#define GPIO131_GPIO PIN_CFG(131, GPIO) +#define GPIO131_MC2_DAT0 PIN_CFG(131, ALT_A) +#define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B) + +#define GPIO132_GPIO PIN_CFG(132, GPIO) +#define GPIO132_MC2_DAT1 PIN_CFG(132, ALT_A) +#define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B) + +#define GPIO133_GPIO PIN_CFG(133, GPIO) +#define GPIO133_MC2_DAT2 PIN_CFG(133, ALT_A) +#define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B) + +#define GPIO134_GPIO PIN_CFG(134, GPIO) +#define GPIO134_MC2_DAT3 PIN_CFG(134, ALT_A) +#define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B) + +#define GPIO135_GPIO PIN_CFG(135, GPIO) +#define GPIO135_MC2_DAT4 PIN_CFG(135, ALT_A) +#define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B) + +#define GPIO136_GPIO PIN_CFG(136, GPIO) +#define GPIO136_MC2_DAT5 PIN_CFG(136, ALT_A) +#define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B) + +#define GPIO137_GPIO PIN_CFG(137, GPIO) +#define GPIO137_MC2_DAT6 PIN_CFG(137, ALT_A) +#define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B) + +#define GPIO138_GPIO PIN_CFG(138, GPIO) +#define GPIO138_MC2_DAT7 PIN_CFG(138, ALT_A) +#define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B) + +#define GPIO139_GPIO PIN_CFG(139, GPIO) +#define GPIO139_SSP1_RXD PIN_CFG(139, ALT_A) +#define GPIO139_SM_WAIT1n PIN_CFG(139, ALT_B) +#define GPIO139_KP_O8 PIN_CFG(139, ALT_C) + +#define GPIO140_GPIO PIN_CFG(140, GPIO) +#define GPIO140_SSP1_TXD PIN_CFG(140, ALT_A) +#define GPIO140_IP_GPIO7 PIN_CFG(140, ALT_B) +#define GPIO140_KP_SKA1 PIN_CFG(140, ALT_C) + +#define GPIO141_GPIO PIN_CFG(141, GPIO) +#define GPIO141_SSP1_CLK PIN_CFG(141, ALT_A) +#define GPIO141_IP_GPIO2 PIN_CFG(141, ALT_B) +#define GPIO141_KP_O9 PIN_CFG(141, ALT_C) + +#define GPIO142_GPIO PIN_CFG(142, GPIO) +#define GPIO142_SSP1_FRM PIN_CFG(142, ALT_A) +#define GPIO142_IP_GPIO3 PIN_CFG(142, ALT_B) +#define GPIO142_KP_SKB1 PIN_CFG(142, ALT_C) + +#define GPIO143_GPIO PIN_CFG(143, GPIO) +#define GPIO143_SSP0_CLK PIN_CFG(143, ALT_A) + +#define GPIO144_GPIO PIN_CFG(144, GPIO) +#define GPIO144_SSP0_FRM PIN_CFG(144, ALT_A) + +#define GPIO145_GPIO PIN_CFG(145, GPIO) +#define GPIO145_SSP0_RXD PIN_CFG(145, ALT_A) + +#define GPIO146_GPIO PIN_CFG(146, GPIO) +#define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A) + +#define GPIO147_GPIO PIN_CFG(147, GPIO) +#define GPIO147_I2C0_SCL PIN_CFG_PULL(147, ALT_A, UP) + +#define GPIO148_GPIO PIN_CFG(148, GPIO) +#define GPIO148_I2C0_SDA PIN_CFG_PULL(148, ALT_A, UP) + +#define GPIO149_GPIO PIN_CFG(149, GPIO) +#define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A) +#define GPIO149_SM_CS1n PIN_CFG(149, ALT_B) +#define GPIO149_SM_PS1n PIN_CFG(149, ALT_C) + +#define GPIO150_GPIO PIN_CFG(150, GPIO) +#define GPIO150_IP_GPIO1 PIN_CFG(150, ALT_A) +#define GPIO150_LCDA_CLK PIN_CFG(150, ALT_B) + +#define GPIO151_GPIO PIN_CFG(151, GPIO) +#define GPIO151_KP_SKA0 PIN_CFG(151, ALT_A) +#define GPIO151_LCD_VSI0 PIN_CFG(151, ALT_B) +#define GPIO151_KP_O8 PIN_CFG(151, ALT_C) + +#define GPIO152_GPIO PIN_CFG(152, GPIO) +#define GPIO152_KP_SKB0 PIN_CFG(152, ALT_A) +#define GPIO152_LCD_VSI1 PIN_CFG(152, ALT_B) +#define GPIO152_KP_O9 PIN_CFG(152, ALT_C) + +#define GPIO153_GPIO PIN_CFG(153, GPIO) +#define GPIO153_KP_I7 PIN_CFG_PULL(153, ALT_A, DOWN) +#define GPIO153_LCD_D24 PIN_CFG(153, ALT_B) +#define GPIO153_U2_RXD PIN_CFG(153, ALT_C) + +#define GPIO154_GPIO PIN_CFG(154, GPIO) +#define GPIO154_KP_I6 PIN_CFG_PULL(154, ALT_A, DOWN) +#define GPIO154_LCD_D25 PIN_CFG(154, ALT_B) +#define GPIO154_U2_TXD PIN_CFG(154, ALT_C) + +#define GPIO155_GPIO PIN_CFG(155, GPIO) +#define GPIO155_KP_I5 PIN_CFG_PULL(155, ALT_A, DOWN) +#define GPIO155_LCD_D26 PIN_CFG(155, ALT_B) +#define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C) + +#define GPIO156_GPIO PIN_CFG(156, GPIO) +#define GPIO156_KP_I4 PIN_CFG_PULL(156, ALT_A, DOWN) +#define GPIO156_LCD_D27 PIN_CFG(156, ALT_B) +#define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C) + +#define GPIO157_GPIO PIN_CFG(157, GPIO) +#define GPIO157_KP_O7 PIN_CFG_PULL(157, ALT_A, UP) +#define GPIO157_LCD_D28 PIN_CFG(157, ALT_B) +#define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C) + +#define GPIO158_GPIO PIN_CFG(158, GPIO) +#define GPIO158_KP_O6 PIN_CFG_PULL(158, ALT_A, UP) +#define GPIO158_LCD_D29 PIN_CFG(158, ALT_B) +#define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C) + +#define GPIO159_GPIO PIN_CFG(159, GPIO) +#define GPIO159_KP_O5 PIN_CFG_PULL(159, ALT_A, UP) +#define GPIO159_LCD_D30 PIN_CFG(159, ALT_B) +#define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C) + +#define GPIO160_GPIO PIN_CFG(160, GPIO) +#define GPIO160_KP_O4 PIN_CFG_PULL(160, ALT_A, UP) +#define GPIO160_LCD_D31 PIN_CFG(160, ALT_B) +#define GPIO160_NONE PIN_CFG(160, ALT_C) + +#define GPIO161_GPIO PIN_CFG(161, GPIO) +#define GPIO161_KP_I3 PIN_CFG_PULL(161, ALT_A, DOWN) +#define GPIO161_LCD_D32 PIN_CFG(161, ALT_B) +#define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C) + +#define GPIO162_GPIO PIN_CFG(162, GPIO) +#define GPIO162_KP_I2 PIN_CFG_PULL(162, ALT_A, DOWN) +#define GPIO162_LCD_D33 PIN_CFG(162, ALT_B) +#define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C) + +#define GPIO163_GPIO PIN_CFG(163, GPIO) +#define GPIO163_KP_I1 PIN_CFG_PULL(163, ALT_A, DOWN) +#define GPIO163_LCD_D34 PIN_CFG(163, ALT_B) +#define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C) + +#define GPIO164_GPIO PIN_CFG(164, GPIO) +#define GPIO164_KP_I0 PIN_CFG_PULL(164, ALT_A, UP) +#define GPIO164_LCD_D35 PIN_CFG(164, ALT_B) +#define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C) + +#define GPIO165_GPIO PIN_CFG(165, GPIO) +#define GPIO165_KP_O3 PIN_CFG_PULL(165, ALT_A, UP) +#define GPIO165_LCD_D36 PIN_CFG(165, ALT_B) +#define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C) + +#define GPIO166_GPIO PIN_CFG(166, GPIO) +#define GPIO166_KP_O2 PIN_CFG_PULL(166, ALT_A, UP) +#define GPIO166_LCD_D37 PIN_CFG(166, ALT_B) +#define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C) + +#define GPIO167_GPIO PIN_CFG(167, GPIO) +#define GPIO167_KP_O1 PIN_CFG_PULL(167, ALT_A, UP) +#define GPIO167_LCD_D38 PIN_CFG(167, ALT_B) +#define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C) + +#define GPIO168_GPIO PIN_CFG(168, GPIO) +#define GPIO168_KP_O0 PIN_CFG_PULL(168, ALT_A, UP) +#define GPIO168_LCD_D39 PIN_CFG(168, ALT_B) +#define GPIO168_NONE PIN_CFG(168, ALT_C) + +#define GPIO169_GPIO PIN_CFG(169, GPIO) +#define GPIO169_RF_PURn PIN_CFG(169, ALT_A) +#define GPIO169_LCDA_DE PIN_CFG(169, ALT_B) +#define GPIO169_USBSIM_PDC PIN_CFG(169, ALT_C) + +#define GPIO170_GPIO PIN_CFG(170, GPIO) +#define GPIO170_MODEM_STATE PIN_CFG(170, ALT_A) +#define GPIO170_LCDA_VSO PIN_CFG(170, ALT_B) +#define GPIO170_KP_SKA1 PIN_CFG(170, ALT_C) + +#define GPIO171_GPIO PIN_CFG(171, GPIO) +#define GPIO171_MODEM_PWREN PIN_CFG(171, ALT_A) +#define GPIO171_LCDA_HSO PIN_CFG(171, ALT_B) +#define GPIO171_KP_SKB1 PIN_CFG(171, ALT_C) + +#define GPIO192_GPIO PIN_CFG(192, GPIO) +#define GPIO192_MSP2_SCK PIN_CFG(192, ALT_A) + +#define GPIO193_GPIO PIN_CFG(193, GPIO) +#define GPIO193_MSP2_TXD PIN_CFG(193, ALT_A) + +#define GPIO194_GPIO PIN_CFG(194, GPIO) +#define GPIO194_MSP2_TCK PIN_CFG(194, ALT_A) + +#define GPIO195_GPIO PIN_CFG(195, GPIO) +#define GPIO195_MSP2_TFS PIN_CFG(195, ALT_A) + +#define GPIO196_GPIO PIN_CFG(196, GPIO) +#define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A) + +#define GPIO197_GPIO PIN_CFG(197, GPIO) +#define GPIO197_MC4_DAT3 PIN_CFG(197, ALT_A) + +#define GPIO198_GPIO PIN_CFG(198, GPIO) +#define GPIO198_MC4_DAT2 PIN_CFG(198, ALT_A) + +#define GPIO199_GPIO PIN_CFG(199, GPIO) +#define GPIO199_MC4_DAT1 PIN_CFG(199, ALT_A) + +#define GPIO200_GPIO PIN_CFG(200, GPIO) +#define GPIO200_MC4_DAT0 PIN_CFG(200, ALT_A) + +#define GPIO201_GPIO PIN_CFG(201, GPIO) +#define GPIO201_MC4_CMD PIN_CFG(201, ALT_A) + +#define GPIO202_GPIO PIN_CFG(202, GPIO) +#define GPIO202_MC4_FBCLK PIN_CFG(202, ALT_A) +#define GPIO202_PWL PIN_CFG(202, ALT_B) +#define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C) + +#define GPIO203_GPIO PIN_CFG(203, GPIO) +#define GPIO203_MC4_CLK PIN_CFG(203, ALT_A) + +#define GPIO204_GPIO PIN_CFG(204, GPIO) +#define GPIO204_MC4_DAT7 PIN_CFG(204, ALT_A) + +#define GPIO205_GPIO PIN_CFG(205, GPIO) +#define GPIO205_MC4_DAT6 PIN_CFG(205, ALT_A) + +#define GPIO206_GPIO PIN_CFG(206, GPIO) +#define GPIO206_MC4_DAT5 PIN_CFG(206, ALT_A) + +#define GPIO207_GPIO PIN_CFG(207, GPIO) +#define GPIO207_MC4_DAT4 PIN_CFG(207, ALT_A) + +#define GPIO208_GPIO PIN_CFG(208, GPIO) +#define GPIO208_MC1_CLK PIN_CFG(208, ALT_A) + +#define GPIO209_GPIO PIN_CFG(209, GPIO) +#define GPIO209_MC1_FBCLK PIN_CFG(209, ALT_A) +#define GPIO209_SPI1_CLK PIN_CFG(209, ALT_B) + +#define GPIO210_GPIO PIN_CFG(210, GPIO) +#define GPIO210_MC1_CMD PIN_CFG(210, ALT_A) + +#define GPIO211_GPIO PIN_CFG(211, GPIO) +#define GPIO211_MC1_DAT0 PIN_CFG(211, ALT_A) + +#define GPIO212_GPIO PIN_CFG(212, GPIO) +#define GPIO212_MC1_DAT1 PIN_CFG(212, ALT_A) +#define GPIO212_SPI1_FRM PIN_CFG(212, ALT_B) + +#define GPIO213_GPIO PIN_CFG(213, GPIO) +#define GPIO213_MC1_DAT2 PIN_CFG(213, ALT_A) +#define GPIO213_SPI1_TXD PIN_CFG(213, ALT_B) + +#define GPIO214_GPIO PIN_CFG(214, GPIO) +#define GPIO214_MC1_DAT3 PIN_CFG(214, ALT_A) +#define GPIO214_SPI1_RXD PIN_CFG(214, ALT_B) + +#define GPIO215_GPIO PIN_CFG(215, GPIO) +#define GPIO215_MC1_CMDDIR PIN_CFG(215, ALT_A) +#define GPIO215_MC3_DAT2DIR PIN_CFG(215, ALT_B) +#define GPIO215_CLKOUT1 PIN_CFG(215, ALT_C) + +#define GPIO216_GPIO PIN_CFG(216, GPIO) +#define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A) +#define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B) +#define GPIO216_I2C3_SDA PIN_CFG_PULL(216, ALT_C, UP) + +#define GPIO217_GPIO PIN_CFG(217, GPIO) +#define GPIO217_MC1_DAT0DIR PIN_CFG(217, ALT_A) +#define GPIO217_MC3_DAT31DIR PIN_CFG(217, ALT_B) +#define GPIO217_CLKOUT2 PIN_CFG(217, ALT_C) + +#define GPIO218_GPIO PIN_CFG(218, GPIO) +#define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A) +#define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B) +#define GPIO218_I2C3_SCL PIN_CFG_PULL(218, ALT_C, UP) + +#define GPIO219_GPIO PIN_CFG(219, GPIO) +#define GPIO219_HSIR_FLA0 PIN_CFG(219, ALT_A) +#define GPIO219_MC3_CLK PIN_CFG(219, ALT_B) + +#define GPIO220_GPIO PIN_CFG(220, GPIO) +#define GPIO220_HSIR_DAT0 PIN_CFG(220, ALT_A) +#define GPIO220_MC3_FBCLK PIN_CFG(220, ALT_B) +#define GPIO220_SPI0_CLK PIN_CFG(220, ALT_C) + +#define GPIO221_GPIO PIN_CFG(221, GPIO) +#define GPIO221_HSIR_RDY0 PIN_CFG(221, ALT_A) +#define GPIO221_MC3_CMD PIN_CFG(221, ALT_B) + +#define GPIO222_GPIO PIN_CFG(222, GPIO) +#define GPIO222_HSIT_FLA0 PIN_CFG(222, ALT_A) +#define GPIO222_MC3_DAT0 PIN_CFG(222, ALT_B) + +#define GPIO223_GPIO PIN_CFG(223, GPIO) +#define GPIO223_HSIT_DAT0 PIN_CFG(223, ALT_A) +#define GPIO223_MC3_DAT1 PIN_CFG(223, ALT_B) +#define GPIO223_SPI0_FRM PIN_CFG(223, ALT_C) + +#define GPIO224_GPIO PIN_CFG(224, GPIO) +#define GPIO224_HSIT_RDY0 PIN_CFG(224, ALT_A) +#define GPIO224_MC3_DAT2 PIN_CFG(224, ALT_B) +#define GPIO224_SPI0_TXD PIN_CFG(224, ALT_C) + +#define GPIO225_GPIO PIN_CFG(225, GPIO) +#define GPIO225_HSIT_CAWAKE0 PIN_CFG(225, ALT_A) +#define GPIO225_MC3_DAT3 PIN_CFG(225, ALT_B) +#define GPIO225_SPI0_RXD PIN_CFG(225, ALT_C) + +#define GPIO226_GPIO PIN_CFG(226, GPIO) +#define GPIO226_HSIT_ACWAKE0 PIN_CFG(226, ALT_A) +#define GPIO226_PWL PIN_CFG(226, ALT_B) +#define GPIO226_USBSIM_PDC PIN_CFG(226, ALT_C) + +#define GPIO227_GPIO PIN_CFG(227, GPIO) +#define GPIO227_CLKOUT1 PIN_CFG(227, ALT_A) + +#define GPIO228_GPIO PIN_CFG(228, GPIO) +#define GPIO228_CLKOUT2 PIN_CFG(228, ALT_A) + +#define GPIO229_GPIO PIN_CFG(229, GPIO) +#define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A) +#define GPIO229_PWL PIN_CFG(229, ALT_B) +#define GPIO229_I2C3_SDA PIN_CFG_PULL(229, ALT_C, UP) + +#define GPIO230_GPIO PIN_CFG(230, GPIO) +#define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A) +#define GPIO230_PWL PIN_CFG(230, ALT_B) +#define GPIO230_I2C3_SCL PIN_CFG_PULL(230, ALT_C, UP) + +#define GPIO256_GPIO PIN_CFG(256, GPIO) +#define GPIO256_USB_NXT PIN_CFG(256, ALT_A) + +#define GPIO257_GPIO PIN_CFG(257, GPIO) +#define GPIO257_USB_STP PIN_CFG(257, ALT_A) + +#define GPIO258_GPIO PIN_CFG(258, GPIO) +#define GPIO258_USB_XCLK PIN_CFG(258, ALT_A) +#define GPIO258_NONE PIN_CFG(258, ALT_B) +#define GPIO258_DDR_TRIG PIN_CFG(258, ALT_C) + +#define GPIO259_GPIO PIN_CFG(259, GPIO) +#define GPIO259_USB_DIR PIN_CFG(259, ALT_A) + +#define GPIO260_GPIO PIN_CFG(260, GPIO) +#define GPIO260_USB_DAT7 PIN_CFG(260, ALT_A) + +#define GPIO261_GPIO PIN_CFG(261, GPIO) +#define GPIO261_USB_DAT6 PIN_CFG(261, ALT_A) + +#define GPIO262_GPIO PIN_CFG(262, GPIO) +#define GPIO262_USB_DAT5 PIN_CFG(262, ALT_A) + +#define GPIO263_GPIO PIN_CFG(263, GPIO) +#define GPIO263_USB_DAT4 PIN_CFG(263, ALT_A) + +#define GPIO264_GPIO PIN_CFG(264, GPIO) +#define GPIO264_USB_DAT3 PIN_CFG(264, ALT_A) + +#define GPIO265_GPIO PIN_CFG(265, GPIO) +#define GPIO265_USB_DAT2 PIN_CFG(265, ALT_A) + +#define GPIO266_GPIO PIN_CFG(266, GPIO) +#define GPIO266_USB_DAT1 PIN_CFG(266, ALT_A) + +#define GPIO267_GPIO PIN_CFG(267, GPIO) +#define GPIO267_USB_DAT0 PIN_CFG(267, ALT_A) + +#endif diff --git a/board/st-ericsson/snowball/snowball.c b/board/st-ericsson/snowball/snowball.c new file mode 100644 index 0000000..79c86df --- /dev/null +++ b/board/st-ericsson/snowball/snowball.c @@ -0,0 +1,185 @@ +/* + * Copyright (C) ST-Ericsson SA 2009 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <malloc.h> +#include <i2c.h> +#include <mmc.h> +#include <asm/types.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/db8500_pincfg.h> + +#include "db8500_pins.h" + +/* + * Get a global data pointer + */ +DECLARE_GLOBAL_DATA_PTR; + +/* + * Memory controller register + */ +#define DMC_BASE_ADDR 0x80156000 +#define DMC_CTL_97 (DMC_BASE_ADDR + 0x184) + +/* + * GPIO pin config common for MOP500/HREF boards + */ +pin_cfg_t gpio_cfg_common[] = { + /* I2C */ + GPIO147_I2C0_SCL, + GPIO148_I2C0_SDA, + GPIO16_I2C1_SCL, + GPIO17_I2C1_SDA, + GPIO10_I2C2_SDA, + GPIO11_I2C2_SCL, + GPIO229_I2C3_SDA, + GPIO230_I2C3_SCL, + + /* SSP0, to AB8500 */ + GPIO143_SSP0_CLK, + GPIO144_SSP0_FRM, + GPIO145_SSP0_RXD | PIN_PULL_DOWN, + GPIO146_SSP0_TXD, + + /* MMC0 (MicroSD card) */ + GPIO18_MC0_CMDDIR | PIN_OUTPUT_HIGH, + GPIO19_MC0_DAT0DIR | PIN_OUTPUT_HIGH, + GPIO20_MC0_DAT2DIR | PIN_OUTPUT_HIGH, + GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH, + GPIO22_MC0_FBCLK | PIN_INPUT_NOPULL, + GPIO23_MC0_CLK | PIN_OUTPUT_LOW, + GPIO24_MC0_CMD | PIN_INPUT_PULLUP, + GPIO25_MC0_DAT0 | PIN_INPUT_PULLUP, + GPIO26_MC0_DAT1 | PIN_INPUT_PULLUP, + GPIO27_MC0_DAT2 | PIN_INPUT_PULLUP, + GPIO28_MC0_DAT3 | PIN_INPUT_PULLUP, + + /* MMC4 (On-board eMMC) */ + GPIO197_MC4_DAT3 | PIN_INPUT_PULLUP, + GPIO198_MC4_DAT2 | PIN_INPUT_PULLUP, + GPIO199_MC4_DAT1 | PIN_INPUT_PULLUP, + GPIO200_MC4_DAT0 | PIN_INPUT_PULLUP, + GPIO201_MC4_CMD | PIN_INPUT_PULLUP, + GPIO202_MC4_FBCLK | PIN_INPUT_NOPULL, + GPIO203_MC4_CLK | PIN_OUTPUT_LOW, + GPIO204_MC4_DAT7 | PIN_INPUT_PULLUP, + GPIO205_MC4_DAT6 | PIN_INPUT_PULLUP, + GPIO206_MC4_DAT5 | PIN_INPUT_PULLUP, + GPIO207_MC4_DAT4 | PIN_INPUT_PULLUP, + + /* UART2, console */ + GPIO29_U2_RXD | PIN_INPUT_PULLUP, + GPIO30_U2_TXD | PIN_OUTPUT_HIGH, + GPIO31_U2_CTSn | PIN_INPUT_PULLUP, + GPIO32_U2_RTSn | PIN_OUTPUT_HIGH, + + /* + * USB, pin 256-267 USB, Is probably already setup correctly from + * BootROM/boot stages, but we don't trust that and set it up anyway + */ + GPIO256_USB_NXT, + GPIO257_USB_STP, + GPIO258_USB_XCLK, + GPIO259_USB_DIR, + GPIO260_USB_DAT7, + GPIO261_USB_DAT6, + GPIO262_USB_DAT5, + GPIO263_USB_DAT4, + GPIO264_USB_DAT3, + GPIO265_USB_DAT2, + GPIO266_USB_DAT1, + GPIO267_USB_DAT0, +}; + +pin_cfg_t gpio_cfg_snowball[] = { + /* MMC0 (MicroSD card) */ + GPIO217_GPIO | PIN_OUTPUT_HIGH, /* MMC_EN */ + GPIO218_GPIO | PIN_INPUT_NOPULL, /* MMC_CD */ + GPIO228_GPIO | PIN_OUTPUT_HIGH, /* SD_SEL */ + + /* eMMC */ + GPIO167_GPIO | PIN_OUTPUT_HIGH, /* RSTn_MLC */ + + /* LAN */ + GPIO131_SM_ADQ8, + GPIO132_SM_ADQ9, + GPIO133_SM_ADQ10, + GPIO134_SM_ADQ11, + GPIO135_SM_ADQ12, + GPIO136_SM_ADQ13, + GPIO137_SM_ADQ14, + GPIO138_SM_ADQ15, + + /* RSTn_LAN */ + GPIO141_GPIO | PIN_OUTPUT_HIGH, +}; + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init(void) +{ + /* + * Setup board (bd) and board-info (bi). + * bi_arch_number: Unique id for this board. It will passed in r1 to + * Linux startup code and is the machine_id. + * bi_boot_params: Where this board expects params. + */ + gd->bd->bi_arch_number = MACH_TYPE_SNOWBALL; + gd->bd->bi_boot_params = 0x00000100; + + /* Configure GPIO pins needed by U-boot */ + db8500_gpio_config_pins(gpio_cfg_common, ARRAY_SIZE(gpio_cfg_common)); + + db8500_gpio_config_pins(gpio_cfg_snowball, + ARRAY_SIZE(gpio_cfg_snowball)); + + return 0; +} + +int dram_init(void) +{ + uint32_t unused_cols_rows; + unsigned int nrows; + unsigned int ncols; + + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->ram_size = PHYS_SDRAM_SIZE_1; + + /* + * Assumption: 2 CS active, both CS have same layout. + * 15 rows max, 11 cols max (controller spec). + * memory chip has 8 banks, I/O width 32 bit. + * The correct way would be to read MR#8: I/O width and density, + * but this requires locking against the PRCMU firmware. + * Simplified approach: + * Read number of unused rows and columns from mem controller. + * size = nCS x 2^(rows+cols) x nbanks x buswidth_bytes + */ + unused_cols_rows = readl(DMC_CTL_97); + nrows = 15 - (unused_cols_rows & 0x07); + ncols = 11 - ((unused_cols_rows & 0x0700) >> 8); + gd->ram_size = gd->bd->bi_dram[0].size = + 2 * (1 << (nrows + ncols)) * 8 * 4; + + return 0; +} diff --git a/boards.cfg b/boards.cfg index 9ef903a..db5cb0a 100644 --- a/boards.cfg +++ b/boards.cfg @@ -232,6 +232,7 @@ harmony arm armv7 harmony nvidia seaboard arm armv7 seaboard nvidia tegra2 ventana arm armv7 ventana nvidia tegra2 u8500_href arm armv7 u8500 st-ericsson u8500 +snowball arm armv7 snowball st-ericsson u8500 actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index fb3b09a..36a0ff3 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -39,6 +39,7 @@ COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o +COBJS-$(CONFIG_DB8500_GPIO) += db8500_gpio.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/gpio/db8500_gpio.c b/drivers/gpio/db8500_gpio.c new file mode 100644 index 0000000..5eb6361 --- /dev/null +++ b/drivers/gpio/db8500_gpio.c @@ -0,0 +1,225 @@ +/* + * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. + * The purpose is that GPIO config found in kernel should work by simply + * copy-paste it to U-boot. + * + * Original Linux authors: + * Copyright (C) 2008,2009 STMicroelectronics + * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> + * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> + * + * Ported to U-boot by: + * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <common.h> +#include <asm/io.h> + +#include <asm/arch/db8500_gpio.h> +#include <asm/arch/db8500_pincfg.h> + +/* + * Macros to work with IO space + * Not actually used? + */ +#define __iomem +#define IO_ADDR(x) (void *) (x) + +/* + * The GPIO module in the db8500 Systems-on-Chip is an + * AMBA device, managing 32 pins and alternate functions. The logic block + * is currently only used in the db8500. + */ + +#define GPIO_TOTAL_PINS 268 +#define GPIO_PINS_PER_BLOCK 32 +#define GPIO_BLOCKS_COUNT (GPIO_TOTAL_PINS/GPIO_PINS_PER_BLOCK + 1) +#define GPIO_BLOCK(pin) (((pin + GPIO_PINS_PER_BLOCK) >> 5) - 1) +#define GPIO_PIN_WITHIN_BLOCK(pin) ((pin)%(GPIO_PINS_PER_BLOCK)) + +/* Register in the logic block */ +#define DB8500_GPIO_DAT 0x00 +#define DB8500_GPIO_DATS 0x04 +#define DB8500_GPIO_DATC 0x08 +#define DB8500_GPIO_PDIS 0x0c +#define DB8500_GPIO_DIR 0x10 +#define DB8500_GPIO_DIRS 0x14 +#define DB8500_GPIO_DIRC 0x18 +#define DB8500_GPIO_SLPC 0x1c +#define DB8500_GPIO_AFSLA 0x20 +#define DB8500_GPIO_AFSLB 0x24 + +#define DB8500_GPIO_RIMSC 0x40 +#define DB8500_GPIO_FIMSC 0x44 +#define DB8500_GPIO_IS 0x48 +#define DB8500_GPIO_IC 0x4c +#define DB8500_GPIO_RWIMSC 0x50 +#define DB8500_GPIO_FWIMSC 0x54 +#define DB8500_GPIO_WKS 0x58 + +static void __iomem *get_gpio_addr(unsigned gpio) +{ + /* Our list of GPIO chips */ + static void __iomem *gpio_addrs[GPIO_BLOCKS_COUNT] = { + IO_ADDR(CFG_GPIO_0_BASE), + IO_ADDR(CFG_GPIO_1_BASE), + IO_ADDR(CFG_GPIO_2_BASE), + IO_ADDR(CFG_GPIO_3_BASE), + IO_ADDR(CFG_GPIO_4_BASE), + IO_ADDR(CFG_GPIO_5_BASE), + IO_ADDR(CFG_GPIO_6_BASE), + IO_ADDR(CFG_GPIO_7_BASE), + IO_ADDR(CFG_GPIO_8_BASE) + }; + + return gpio_addrs[GPIO_BLOCK(gpio)]; +} + +static unsigned get_gpio_offset(unsigned gpio) +{ + return GPIO_PIN_WITHIN_BLOCK(gpio); +} + +/* Can only be called from config_pin. Don't configure alt-mode directly */ +static void gpio_set_mode(unsigned gpio, enum db8500_gpio_alt mode) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + u32 bit = 1 << offset; + u32 afunc, bfunc; + + afunc = readl(addr + DB8500_GPIO_AFSLA) & ~bit; + bfunc = readl(addr + DB8500_GPIO_AFSLB) & ~bit; + if (mode & DB8500_GPIO_ALT_A) + afunc |= bit; + if (mode & DB8500_GPIO_ALT_B) + bfunc |= bit; + writel(afunc, addr + DB8500_GPIO_AFSLA); + writel(bfunc, addr + DB8500_GPIO_AFSLB); +} + +/** + * db8500_gpio_set_pull() - enable/disable pull up/down on a gpio + * @gpio: pin number + * @pull: one of DB8500_GPIO_PULL_DOWN, DB8500_GPIO_PULL_UP, + * and DB8500_GPIO_PULL_NONE + * + * Enables/disables pull up/down on a specified pin. This only takes effect if + * the pin is configured as an input (either explicitly or by the alternate + * function). + * + * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is + * configured as an input. Otherwise, due to the way the controller registers + * work, this function will change the value output on the pin. + */ +void db8500_gpio_set_pull(unsigned gpio, enum db8500_gpio_pull pull) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + u32 bit = 1 << offset; + u32 pdis; + + pdis = readl(addr + DB8500_GPIO_PDIS); + if (pull == DB8500_GPIO_PULL_NONE) + pdis |= bit; + else + pdis &= ~bit; + writel(pdis, addr + DB8500_GPIO_PDIS); + + if (pull == DB8500_GPIO_PULL_UP) + writel(bit, addr + DB8500_GPIO_DATS); + else if (pull == DB8500_GPIO_PULL_DOWN) + writel(bit, addr + DB8500_GPIO_DATC); +} + +void db8500_gpio_make_input(unsigned gpio) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + + writel(1 << offset, addr + DB8500_GPIO_DIRC); +} + +int db8500_gpio_get_input(unsigned gpio) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + u32 bit = 1 << offset; + + printf("db8500_gpio_get_input gpio=%u addr=%p offset=%u bit=%#x\n", + gpio, addr, offset, bit); + + return (readl(addr + DB8500_GPIO_DAT) & bit) != 0; +} + +void db8500_gpio_make_output(unsigned gpio, int val) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + + writel(1 << offset, addr + DB8500_GPIO_DIRS); + db8500_gpio_set_output(gpio, val); +} + +void db8500_gpio_set_output(unsigned gpio, int val) +{ + void __iomem *addr = get_gpio_addr(gpio); + unsigned offset = get_gpio_offset(gpio); + + if (val) + writel(1 << offset, addr + DB8500_GPIO_DATS); + else + writel(1 << offset, addr + DB8500_GPIO_DATC); +} + +/** + * config_pin - configure a pin's mux attributes + * @cfg: pin confguration + * + * Configures a pin's mode (alternate function or GPIO), its pull up status, + * and its sleep mode based on the specified configuration. The @cfg is + * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These + * are constructed using, and can be further enhanced with, the macros in + * plat/pincfg.h. + * + * If a pin's mode is set to GPIO, it is configured as an input to avoid + * side-effects. The gpio can be manipulated later using standard GPIO API + * calls. + */ +static void config_pin(pin_cfg_t cfg) +{ + int pin = PIN_NUM(cfg); + int pull = PIN_PULL(cfg); + int af = PIN_ALT(cfg); + int output = PIN_DIR(cfg); + int val = PIN_VAL(cfg); + + if (output) + db8500_gpio_make_output(pin, val); + else { + db8500_gpio_make_input(pin); + db8500_gpio_set_pull(pin, pull); + } + + gpio_set_mode(pin, af); +} + +/** + * db8500_config_pins - configure several pins at once + * @cfgs: array of pin configurations + * @num: number of elments in the array + * + * Configures several pins using config_pin(). Refer to that function for + * further information. + */ +void db8500_gpio_config_pins(pin_cfg_t *cfgs, size_t num) +{ + size_t i; + + for (i = 0; i < num; i++) + config_pin(cfgs[i]); +} diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index ed581ae..d4c5137 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -156,6 +156,8 @@ int serial_init (void) writel(lcr, ®s->fr); writel(lcr, ®s->pl011_rlcr); + /* lcrh needs to be set again for change to be effective */ + writel(lcr, ®s->pl011_lcrh); } #endif /* Finally, enable the UART */ diff --git a/include/configs/snowball.h b/include/configs/snowball.h new file mode 100644 index 0000000..845db29 --- /dev/null +++ b/include/configs/snowball.h @@ -0,0 +1,274 @@ +/* + * Copyright (C) ST-Ericsson SA 2009 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * #define DEBUG 1 + */ + +#define CONFIG_SKIP_LOWLEVEL_INIT 1 +#define CONFIG_SNOWBALL 1 +#define CONFIG_SYS_ICACHE_OFF 1 +#define CONFIG_SYS_DCACHE_OFF 1 + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_U8500 +#define CONFIG_L2_OFF + +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF +#define CONFIG_SYS_HZ 1000 /* must be 1000 */ + +/*----------------------------------------------------------------------- + * Size of environment and malloc() pool + */ +/* + * If you use U-Boot as crash kernel, make sure that it does not overwrite + * information saved by kexec during panic. Kexec expects the start + * address of the executable 32K above "crashkernel" address. + */ +/* + * Size of malloc() pool + */ +#ifdef CONFIG_BOOT_SRAM +#define CONFIG_ENV_SIZE (32*1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64*1024) +#else +#define CONFIG_ENV_SIZE (128*1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) +#endif + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */ + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV +#define CONFIG_ENV_OFFSET 0x0118000 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* SLOT2: eMMC */ + +/* + * PL011 Configuration + */ +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_SERIAL_RLCR +#define CONFIG_PL011_SERIAL_FLUSH_ON_INIT + +/* + * U8500 UART registers base for 3 serial devices + */ +#define CFG_UART0_BASE 0x80120000 +#define CFG_UART1_BASE 0x80121000 +#define CFG_UART2_BASE 0x80007000 +#define CFG_SERIAL0 CFG_UART0_BASE +#define CFG_SERIAL1 CFG_UART1_BASE +#define CFG_SERIAL2 CFG_UART2_BASE +#define CONFIG_PL011_CLOCK 38400000 +#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \ + (void *)CFG_SERIAL2 } +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Devices and file systems + */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION + +/* + * Commands + */ +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_BDI +#define CONFIG_CMD_IMI +#define CONFIG_CMD_MISC +#define CONFIG_CMD_RUN +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_CONSOLE +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_SOURCE + +#ifndef CONFIG_BOOTDELAY +#define CONFIG_BOOTDELAY 1 +#endif +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +#undef CONFIG_BOOTARGS +#define CONFIG_BOOTCOMMAND \ + "mmc dev 1; " \ + "if run loadbootscript; " \ + "then run bootscript; " \ + "else " \ + "if run mmcload; " \ + "then run mmcboot; " \ + "else " \ + "mmc dev 0; " \ + "if run emmcloadbootscript; " \ + "then run bootscript; " \ + "else " \ + "if run emmcload; " \ + "then run emmcboot; " \ + "else " \ + "echo No media to boot from; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "fi; " + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr=0x00100000\0" \ + "console=ttyAMA2,115200n8\0" \ + "loadbootscript=fatload mmc 1:1 ${loadaddr} boot.scr\0" \ + "emmcloadbootscript=fatload mmc 0:2 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript " \ + "from mmc ...; source ${loadaddr}\0" \ + "memargs256=mem=96M at 0 mem_modem=32M at 96M mem=32M at 128M " \ + "hwmem=22M at 160M pmem_hwb=42M at 182M mem_mali=32 at 224M\0" \ + "memargs512=mem=96M at 0 mem_modem=32M at 96M hwmem=32M at 128M " \ + "mem=64M at 160M mem_mali=32M at 224M " \ + "pmem_hwb=128M at 256M mem=128M at 384M\0" \ + "memargs1024=mem=128M at 0 mali.mali_mem=32M at 128M " \ + "hwmem=168M at M160M mem=48M at 328M " \ + "mem_issw=1M at 383M mem=640M at 384M\0" \ + "memargs=setenv bootargs ${bootargs} ${memargs1024}\0" \ + "emmcload=fatload mmc 0:2 ${loadaddr} uImage\0" \ + "mmcload=fatload mmc 1:1 ${loadaddr} uImage\0" \ + "commonargs=setenv bootargs console=${console} " \ + "vmalloc=300M\0" \ + "emmcargs=setenv bootargs ${bootargs} " \ + "root=/dev/mmcblk0p3 " \ + "rootwait\0" \ + "addcons=setenv bootargs ${bootargs} " \ + "console=${console}\0" \ + "emmcboot=echo Booting from eMMC ...; " \ + "run commonargs emmcargs memargs; " \ + "bootm ${loadaddr}\0" \ + "mmcargs=setenv bootargs ${bootargs} " \ + "root=/dev/mmcblk1p2 " \ + "rootwait earlyprintk\0" \ + "mmcboot=echo Booting from external MMC ...; " \ + "run commonargs mmcargs memargs; " \ + "bootm ${loadaddr}\0" \ + "fdt_high=0x2BC00000\0" \ + "stdout=serial,usbtty\0" \ + "stdin=serial,usbtty\0" \ + "stderr=serial,usbtty\0" + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "U8500 $ " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 + +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_SETUP_MEMORY_TAGS 2 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ + +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */ +#define PHYS_SDRAM_SIZE_1 0x10000000 /* 256 MB */ + +/* + * additions for new relocation code + */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET + +/* landing address before relocation */ +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0x0 +#endif + +/* + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/* + * base register values for U8500 + */ +#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock */ + + +/* + * U8500 GPIO register base for 9 banks + */ +#define CONFIG_DB8500_GPIO +#define CFG_GPIO_0_BASE 0x8012E000 +#define CFG_GPIO_1_BASE 0x8012E080 +#define CFG_GPIO_2_BASE 0x8000E000 +#define CFG_GPIO_3_BASE 0x8000E080 +#define CFG_GPIO_4_BASE 0x8000E100 +#define CFG_GPIO_5_BASE 0x8000E180 +#define CFG_GPIO_6_BASE 0x8011E000 +#define CFG_GPIO_7_BASE 0x8011E080 +#define CFG_GPIO_8_BASE 0xA03FE000 + +#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */ + +#endif /* __CONFIG_H */ -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 24+ messages in thread
end of thread, other threads:[~2012-08-10 16:08 UTC | newest] Thread overview: 24+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2012-07-31 18:59 [U-Boot] [PATCH 00/11] Support for ST-Ericsson snowball board mathieu.poirier at linaro.org 2012-07-31 18:59 ` [U-Boot] [PATCH 01/11] snowball: Add support for ux500 based " mathieu.poirier at linaro.org 2012-08-03 14:46 ` Tom Rini 2012-08-03 19:32 ` Mathieu Poirier 2012-08-03 19:45 ` Tom Rini 2012-08-03 15:32 ` Tom Rini 2012-07-31 18:59 ` [U-Boot] [PATCH 02/11] u8500: Moving prcmu to cpu directory mathieu.poirier at linaro.org 2012-07-31 18:59 ` [U-Boot] [PATCH 03/11] snowball: Adding architecture dependent initialisation mathieu.poirier at linaro.org 2012-07-31 18:59 ` [U-Boot] [PATCH 04/11] snowball: Adding CPU clock initialisation mathieu.poirier at linaro.org 2012-07-31 18:59 ` [U-Boot] [PATCH 05/11] snowball: Moving to ux500.v2 addess scheme for PRCMU access mathieu.poirier at linaro.org 2012-07-31 18:59 ` [U-Boot] [PATCH 06/11] snowball: applying power to LAN and GBF controllers mathieu.poirier at linaro.org 2012-07-31 18:59 ` [U-Boot] [PATCH 07/11] u8500: Moving processor-specific functions to cpu area mathieu.poirier at linaro.org 2012-08-10 16:08 ` Tom Rini 2012-07-31 18:59 ` [U-Boot] [PATCH 08/11] u8500: Enabling power to MMC device on AB8500 V2 mathieu.poirier at linaro.org 2012-08-10 16:08 ` Tom Rini 2012-07-31 18:59 ` [U-Boot] [PATCH 09/11] u8500: Separating mmc config parameters from driver mathieu.poirier at linaro.org 2012-08-10 16:08 ` Tom Rini 2012-07-31 18:59 ` [U-Boot] [PATCH 10/11] armv7: Adding cpu specific cache managmenent mathieu.poirier at linaro.org 2012-07-31 18:59 ` [U-Boot] [PATCH 11/11] snowball: Adding board specific cache cleanup routine mathieu.poirier at linaro.org 2012-08-10 16:08 ` [U-Boot] [PATCH 00/11] Support for ST-Ericsson snowball board Tom Rini -- strict thread matches above, loose matches on Subject: below -- 2012-06-18 16:35 [U-Boot] [PATCH 00/11] support " mathieu.poirier at linaro.org 2012-06-18 16:35 ` [U-Boot] [PATCH 01/11] snowball: Add support for ux500 based " mathieu.poirier at linaro.org 2012-06-18 17:59 ` Tom Rini 2012-06-18 22:16 ` Mathieu Poirier 2012-06-18 16:25 [U-Boot] [PATCH 00/11] support for ST-Ericsson " mathieu.poirier at linaro.org 2012-06-18 16:25 ` [U-Boot] [PATCH 01/11] snowball: Add support for ux500 based " mathieu.poirier at linaro.org
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