[U-Boot] [PATCH 5/6] nand_spl: p1023rds: wait before enabling DDR controller

[Scott Wood <scottwood@freescale.com>]

On 08/13/2012 01:10 PM, Matthew McClintock wrote:
> We have a requirement to wait a period of time before enabling the
> DDR controller
> 
> Signed-off-by: Matthew McClintock <msm@freescale.com>
> ---
>  nand_spl/board/freescale/p1023rds/Makefile    |    6 +++++-
>  nand_spl/board/freescale/p1023rds/nand_boot.c |   14 ++++++++++++--
>  2 files changed, 17 insertions(+), 3 deletions(-)
> 
> diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile
> index 168e868..da43521 100644
> --- a/nand_spl/board/freescale/p1023rds/Makefile
> +++ b/nand_spl/board/freescale/p1023rds/Makefile
> @@ -34,7 +34,8 @@ CFLAGS	+= -DCONFIG_NAND_SPL
>  
>  SOBJS	= start.o resetvec.o
>  COBJS	= cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
> -	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
> +	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \
> +	  ../common.o
>  
>  SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
>  OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
> @@ -114,6 +115,9 @@ ifneq ($(OBJTREE), $(SRCTREE))
>  $(obj)nand_boot.c:
>  	@rm -f $(obj)nand_boot.c
>  	ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
> +$(obj)../common.c:
> +	@rm -f $(obj)../common.c
> +	ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c
>  endif
>  
>  #########################################################################
> diff --git a/nand_spl/board/freescale/p1023rds/nand_boot.c b/nand_spl/board/freescale/p1023rds/nand_boot.c
> index 0065c87..9309936 100644
> --- a/nand_spl/board/freescale/p1023rds/nand_boot.c
> +++ b/nand_spl/board/freescale/p1023rds/nand_boot.c
> @@ -25,6 +25,7 @@
>  #include <asm/io.h>
>  #include <nand.h>
>  #include <asm/fsl_law.h>
> +#include <asm/fsl_ddr_sdram.h>
>  
>  /* Fixed sdram init -- doesn't use serial presence detect. */
>  void sdram_init(void)
> @@ -53,12 +54,21 @@ void sdram_init(void)
>  	out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
>  	out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1);
>  	out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_2);
> -	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
> +	/* Set, but do not enable the memory */
> +	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN);
> +
> +	asm volatile("sync;isync");
> +	udelay(500);
> +
> +	/* Let the controller go */
> +	out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
>  }
>  
> +u32 bus_clk;
> +
>  void board_init_f(ulong bootflag)
>  {
> -	u32 plat_ratio, bus_clk;
> +	u32 plat_ratio;
>  	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
>  
>  	/* initialize selected port with appropriate baud rate */
> 

This is before relocation, so you can't use global variables.  Use
gd->bus_clk.

In our SDK where this code has already been applied, I spent some debug
time tracking why the first word of the SPL was getting corrupted (the
BSS goes right after the end of the NAND buffer and it wraps around),
when trying to find the cause of other corruption (the rest was bad DDR
settings).

-Scott