* [U-Boot] [PATCH 1/2] mx5: Add default pin initializers
@ 2012-08-14 15:46 Benoît Thébaudeau
2012-08-14 15:47 ` [U-Boot] [PATCH 2/2] mx5: Use " Benoît Thébaudeau
` (2 more replies)
0 siblings, 3 replies; 15+ messages in thread
From: Benoît Thébaudeau @ 2012-08-14 15:46 UTC (permalink / raw)
To: u-boot
Create default pin initialization functions for the default iomux function
assignments of the main peripherals.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
.../arch/arm/cpu/armv7/mx5/soc.c | 139 ++++++++++++++++++++
.../arch/arm/include/asm/arch-mx5/sys_proto.h | 5 +
2 files changed, 144 insertions(+)
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/soc.c u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/soc.c
index 3f5a4f7..ee19b54 100644
--- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/soc.c
+++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/soc.c
@@ -25,6 +25,8 @@
#include <common.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/iomux.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
@@ -71,6 +73,143 @@ u32 get_cpu_rev(void)
return system_rev;
}
+#ifdef CONFIG_MXC_UART
+#if CONFIG_MXC_UART_BASE == UART1_BASE
+#ifdef CONFIG_MX51
+void mx51_uart1_init_pins(void)
+{
+ int in_pad, out_pad;
+
+ /* Set up pins for UART1. */
+ mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
+
+ mxc_iomux_set_input(MX51_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
+ INPUT_CTL_PATH0);
+ mxc_iomux_set_input(MX51_UART1_IPP_UART_RTS_B_SELECT_INPUT,
+ INPUT_CTL_PATH0);
+
+ in_pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
+ PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW;
+ out_pad = PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE |
+ PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_SRE_SLOW;
+
+ mxc_iomux_set_pad(MX51_PIN_UART1_RXD, in_pad);
+ mxc_iomux_set_pad(MX51_PIN_UART1_TXD, out_pad);
+ mxc_iomux_set_pad(MX51_PIN_UART1_RTS, in_pad);
+ mxc_iomux_set_pad(MX51_PIN_UART1_CTS, out_pad);
+}
+#endif
+#endif
+#endif
+
+#ifdef CONFIG_MXC_SPI
+void mx51_ecspi1_init_pins(void)
+{
+ int act_lo_pad, act_hi_pad;
+
+ /* Set up pins for eCSPI1. */
+ mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT0);
+
+ act_lo_pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PULL | PAD_CTL_100K_PU |
+ PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_SRE_SLOW;
+ act_hi_pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PULL | PAD_CTL_100K_PD |
+ PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH |
+ PAD_CTL_SRE_SLOW;
+
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, act_hi_pad);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, act_lo_pad);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, act_hi_pad);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, act_hi_pad);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, act_lo_pad);
+ mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, act_lo_pad);
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+void mx51_esdhc1_init_pins(void)
+{
+ int out_pad, io_pad;
+
+ /* Set up pins for eSDHC1. */
+ mxc_request_iomux(MX51_PIN_SD1_CMD,
+ IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_SD1_DATA0,
+ IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_SD1_DATA1,
+ IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_SD1_DATA2,
+ IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_SD1_DATA3,
+ IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_GPIO1_1,
+ IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0); /* WP */
+ mxc_request_iomux(MX51_PIN_GPIO1_0,
+ IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0); /* CD */
+
+ out_pad = PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PULL | PAD_CTL_47K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST;
+ io_pad = PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_ENABLE |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_47K_PU |
+ PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST;
+
+ mxc_iomux_set_pad(MX51_PIN_SD1_CMD, io_pad);
+ mxc_iomux_set_pad(MX51_PIN_SD1_CLK, out_pad);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, io_pad);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, io_pad);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, io_pad);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, io_pad);
+ mxc_iomux_set_pad(MX51_PIN_GPIO1_1, PAD_CTL_HYS_ENABLE); /* WP */
+ mxc_iomux_set_pad(MX51_PIN_GPIO1_0, PAD_CTL_HYS_ENABLE); /* CD */
+}
+
+void mx51_esdhc2_init_pins(void)
+{
+ int out_pad, io_pad;
+
+ /* Set up pins for eSDHC2. */
+ mxc_request_iomux(MX51_PIN_SD2_CMD,
+ IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_SD2_CLK, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_SD2_DATA0,
+ IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_SD2_DATA1,
+ IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_SD2_DATA2,
+ IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_SD2_DATA3,
+ IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT0);
+
+ out_pad = PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PULL | PAD_CTL_47K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
+ PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST;
+ io_pad = PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_ENABLE |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_47K_PU |
+ PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST;
+
+ mxc_iomux_set_pad(MX51_PIN_SD2_CMD, io_pad);
+ mxc_iomux_set_pad(MX51_PIN_SD2_CLK, out_pad);
+ mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, io_pad);
+ mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, io_pad);
+ mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, io_pad);
+ mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, io_pad);
+}
+#endif
+
#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/sys_proto.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/sys_proto.h
index 7b5246e..ce4a94c 100644
--- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/sys_proto.h
+++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/sys_proto.h
@@ -39,4 +39,9 @@ u32 get_ahb_clk(void);
u32 get_periph_clk(void);
char *get_reset_cause(void);
+void mx51_uart1_init_pins(void);
+void mx51_ecspi1_init_pins(void);
+void mx51_esdhc1_init_pins(void);
+void mx51_esdhc2_init_pins(void);
+
#endif
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 2/2] mx5: Use default pin initializers
2012-08-14 15:46 [U-Boot] [PATCH 1/2] mx5: Add default pin initializers Benoît Thébaudeau
@ 2012-08-14 15:47 ` Benoît Thébaudeau
2012-08-15 14:37 ` Benoît Thébaudeau
2012-08-16 19:46 ` Matt Sealey
2012-08-17 19:10 ` [U-Boot] [PATCH 1/2] mx5: Add " Matt Sealey
2012-08-17 20:25 ` Stefano Babic
2 siblings, 2 replies; 15+ messages in thread
From: Benoît Thébaudeau @ 2012-08-14 15:47 UTC (permalink / raw)
To: u-boot
Use the newly created mx5 default pin initialization functions in mx5 board
files.
Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
.../board/efikamx/efikamx.c | 133 ++------------------
.../board/freescale/mx51evk/mx51evk.c | 121 +-----------------
.../board/ttcontrol/vision2/vision2.c | 72 +----------
3 files changed, 15 insertions(+), 311 deletions(-)
diff --git u-boot-4d3c95f.orig/board/efikamx/efikamx.c u-boot-4d3c95f/board/efikamx/efikamx.c
index e88b2ed..6810433 100644
--- u-boot-4d3c95f.orig/board/efikamx/efikamx.c
+++ u-boot-4d3c95f/board/efikamx/efikamx.c
@@ -143,38 +143,12 @@ int dram_init(void)
}
/*
- * UART configuration
- */
-static void setup_iomux_uart(void)
-{
- unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
- PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
-
- mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
- mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
-}
-
-/*
* SPI configuration
*/
#ifdef CONFIG_MXC_SPI
static void setup_iomux_spi(void)
{
- /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
- mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
-
- /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
+ mx51_ecspi1_init_pins();
/* Configure SS0 as a GPIO */
mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
@@ -183,16 +157,6 @@ static void setup_iomux_spi(void)
/* Configure SS1 as a GPIO */
mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO);
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1);
-
- /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
- /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
}
#else
static inline void setup_iomux_spi(void) { }
@@ -333,7 +297,12 @@ int board_mmc_init(bd_t *bis)
int ret;
uint32_t cd = efika_mmc_cd();
- /* SDHC1 is used on all revisions, setup control pins first */
+ /* SDHC1 is used on all revisions */
+
+ /* SDHC1 IOMUX */
+ mx51_esdhc1_init_pins();
+
+ /* SDHC1 Control lines IOMUX */
mxc_request_iomux(cd,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(cd,
@@ -354,65 +323,8 @@ int board_mmc_init(bd_t *bis)
/* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */
if (machine_is_efikasb() || (machine_is_efikamx() &&
(get_efika_rev() < EFIKAMX_BOARD_REV_12))) {
- /* SDHC1 IOMUX */
- mxc_request_iomux(MX51_PIN_SD1_CMD,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
- PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_CLK,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
- PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
- PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
- PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
- PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
- PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
- PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
-
/* SDHC2 IOMUX */
- mxc_request_iomux(MX51_PIN_SD2_CMD,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD2_CLK,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
+ mx51_esdhc2_init_pins();
/* SDHC2 Control lines IOMUX */
mxc_request_iomux(MX51_PIN_GPIO1_7,
@@ -436,33 +348,6 @@ int board_mmc_init(bd_t *bis)
if (!ret)
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
} else { /* New boards use only SDHC1 */
- /* SDHC1 IOMUX */
- mxc_request_iomux(MX51_PIN_SD1_CMD,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_CLK,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
- mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
-
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
}
@@ -676,7 +561,7 @@ int board_early_init_f(void)
{
init_drive_strength();
- setup_iomux_uart();
+ mx51_uart1_init_pins();
setup_iomux_spi();
setup_iomux_led();
diff --git u-boot-4d3c95f.orig/board/freescale/mx51evk/mx51evk.c u-boot-4d3c95f/board/freescale/mx51evk/mx51evk.c
index 514a7ac..dedfb7e 100644
--- u-boot-4d3c95f.orig/board/freescale/mx51evk/mx51evk.c
+++ u-boot-4d3c95f/board/freescale/mx51evk/mx51evk.c
@@ -60,21 +60,6 @@ int dram_init(void)
return 0;
}
-static void setup_iomux_uart(void)
-{
- unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
- PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
-
- mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
- mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
-}
-
static void setup_iomux_fec(void)
{
/*FEC_MDIO*/
@@ -153,29 +138,11 @@ static void setup_iomux_fec(void)
#ifdef CONFIG_MXC_SPI
static void setup_iomux_spi(void)
{
- /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
- mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
-
- /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
+ mx51_ecspi1_init_pins();
/* de-select SS1 of instance: ecspi1. */
mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
-
- /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
- mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
-
- /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
-
- /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
}
#endif
@@ -354,90 +321,10 @@ int board_mmc_init(bd_t *bis)
index++) {
switch (index) {
case 0:
- mxc_request_iomux(MX51_PIN_SD1_CMD,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_CLK,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_DATA0,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_DATA1,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_DATA2,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_DATA3,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_GPIO1_0,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
- PAD_CTL_HYS_ENABLE);
- mxc_request_iomux(MX51_PIN_GPIO1_1,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
- PAD_CTL_HYS_ENABLE);
+ mx51_esdhc1_init_pins();
break;
case 1:
- mxc_request_iomux(MX51_PIN_SD2_CMD,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD2_CLK,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD2_DATA0,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_SD2_DATA1,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_SD2_DATA2,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX51_PIN_SD2_DATA3,
- IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
- PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
- PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
- PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
- PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
- PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
- PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
- PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_SD2_CMD,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mx51_esdhc2_init_pins();
mxc_request_iomux(MX51_PIN_GPIO1_6,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
@@ -509,7 +396,7 @@ void lcd_enable(void)
int board_early_init_f(void)
{
- setup_iomux_uart();
+ mx51_uart1_init_pins();
setup_iomux_fec();
#ifdef CONFIG_USB_EHCI_MX5
setup_usb_h1();
diff --git u-boot-4d3c95f.orig/board/ttcontrol/vision2/vision2.c u-boot-4d3c95f/board/ttcontrol/vision2/vision2.c
index d68bef7..a96c475 100644
--- u-boot-4d3c95f.orig/board/ttcontrol/vision2/vision2.c
+++ u-boot-4d3c95f/board/ttcontrol/vision2/vision2.c
@@ -182,21 +182,7 @@ static void setup_uart(void)
#ifdef CONFIG_MXC_SPI
void spi_io_init(void)
{
- /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
- mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
-
- /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
-
- /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
- PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
+ mx51_ecspi1_init_pins();
/*
* SS1 will be used as GPIO because of uninterrupted
@@ -212,11 +198,6 @@ void spi_io_init(void)
mxc_iomux_set_pad(MX51_PIN_DI1_PIN11,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
-
- /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
}
static void reset_peripherals(int reset)
@@ -539,56 +520,7 @@ int get_mmc_getcd(u8 *cd, struct mmc *mmc)
#ifdef CONFIG_FSL_ESDHC
int board_mmc_init(bd_t *bis)
{
- mxc_request_iomux(MX51_PIN_SD1_CMD,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_CLK,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_DATA0,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_DATA1,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_DATA2,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_request_iomux(MX51_PIN_SD1_DATA3,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
- PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
- PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
- PAD_CTL_PUE_PULL |
- PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_GPIO1_0,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
- PAD_CTL_HYS_ENABLE);
- mxc_request_iomux(MX51_PIN_GPIO1_1,
- IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
- mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
- PAD_CTL_HYS_ENABLE);
+ mx51_esdhc1_init_pins();
return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
}
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 2/2] mx5: Use default pin initializers
2012-08-14 15:47 ` [U-Boot] [PATCH 2/2] mx5: Use " Benoît Thébaudeau
@ 2012-08-15 14:37 ` Benoît Thébaudeau
2012-08-16 19:46 ` Matt Sealey
1 sibling, 0 replies; 15+ messages in thread
From: Benoît Thébaudeau @ 2012-08-15 14:37 UTC (permalink / raw)
To: u-boot
> Use the newly created mx5 default pin initialization functions in mx5
> board
> files.
>
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Stefano Babic <sbabic@denx.de>
Adding missing board maintainers to Cc.
> ---
> .../board/efikamx/efikamx.c | 133
> ++------------------
> .../board/freescale/mx51evk/mx51evk.c | 121
> +-----------------
> .../board/ttcontrol/vision2/vision2.c | 72
> +----------
> 3 files changed, 15 insertions(+), 311 deletions(-)
>
> diff --git u-boot-4d3c95f.orig/board/efikamx/efikamx.c
> u-boot-4d3c95f/board/efikamx/efikamx.c
> index e88b2ed..6810433 100644
> --- u-boot-4d3c95f.orig/board/efikamx/efikamx.c
> +++ u-boot-4d3c95f/board/efikamx/efikamx.c
> @@ -143,38 +143,12 @@ int dram_init(void)
> }
>
> /*
> - * UART configuration
> - */
> -static void setup_iomux_uart(void)
> -{
> - unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
> -
> - mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
> - mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
> - mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
> - mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
> -}
> -
> -/*
> * SPI configuration
> */
> #ifdef CONFIG_MXC_SPI
> static void setup_iomux_spi(void)
> {
> - /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
> - mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
> -
> - /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1.
> */
> - mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
> + mx51_ecspi1_init_pins();
>
> /* Configure SS0 as a GPIO */
> mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
> @@ -183,16 +157,6 @@ static void setup_iomux_spi(void)
> /* Configure SS1 as a GPIO */
> mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO);
> gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1);
> -
> - /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
> - mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
> -
> - /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1.
> */
> - mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
> }
> #else
> static inline void setup_iomux_spi(void) { }
> @@ -333,7 +297,12 @@ int board_mmc_init(bd_t *bis)
> int ret;
> uint32_t cd = efika_mmc_cd();
>
> - /* SDHC1 is used on all revisions, setup control pins first */
> + /* SDHC1 is used on all revisions */
> +
> + /* SDHC1 IOMUX */
> + mx51_esdhc1_init_pins();
> +
> + /* SDHC1 Control lines IOMUX */
> mxc_request_iomux(cd,
> IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> mxc_iomux_set_pad(cd,
> @@ -354,65 +323,8 @@ int board_mmc_init(bd_t *bis)
> /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */
> if (machine_is_efikasb() || (machine_is_efikamx() &&
> (get_efika_rev() < EFIKAMX_BOARD_REV_12))) {
> - /* SDHC1 IOMUX */
> - mxc_request_iomux(MX51_PIN_SD1_CMD,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
> - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_CLK,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
> - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
> - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
> - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
> - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
> - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
> -
> /* SDHC2 IOMUX */
> - mxc_request_iomux(MX51_PIN_SD2_CMD,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD2_CLK,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> + mx51_esdhc2_init_pins();
>
> /* SDHC2 Control lines IOMUX */
> mxc_request_iomux(MX51_PIN_GPIO1_7,
> @@ -436,33 +348,6 @@ int board_mmc_init(bd_t *bis)
> if (!ret)
> ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
> } else { /* New boards use only SDHC1 */
> - /* SDHC1 IOMUX */
> - mxc_request_iomux(MX51_PIN_SD1_CMD,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_CLK,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
> }
>
> @@ -676,7 +561,7 @@ int board_early_init_f(void)
> {
> init_drive_strength();
>
> - setup_iomux_uart();
> + mx51_uart1_init_pins();
> setup_iomux_spi();
> setup_iomux_led();
>
> diff --git u-boot-4d3c95f.orig/board/freescale/mx51evk/mx51evk.c
> u-boot-4d3c95f/board/freescale/mx51evk/mx51evk.c
> index 514a7ac..dedfb7e 100644
> --- u-boot-4d3c95f.orig/board/freescale/mx51evk/mx51evk.c
> +++ u-boot-4d3c95f/board/freescale/mx51evk/mx51evk.c
> @@ -60,21 +60,6 @@ int dram_init(void)
> return 0;
> }
>
> -static void setup_iomux_uart(void)
> -{
> - unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
> -
> - mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
> - mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
> - mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
> - mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
> -}
> -
> static void setup_iomux_fec(void)
> {
> /*FEC_MDIO*/
> @@ -153,29 +138,11 @@ static void setup_iomux_fec(void)
> #ifdef CONFIG_MXC_SPI
> static void setup_iomux_spi(void)
> {
> - /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
> - mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
> -
> - /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1.
> */
> - mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
> + mx51_ecspi1_init_pins();
>
> /* de-select SS1 of instance: ecspi1. */
> mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
> mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
> -
> - /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
> - mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
> -
> - /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
> - mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
> -
> - /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1.
> */
> - mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
> }
> #endif
>
> @@ -354,90 +321,10 @@ int board_mmc_init(bd_t *bis)
> index++) {
> switch (index) {
> case 0:
> - mxc_request_iomux(MX51_PIN_SD1_CMD,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_CLK,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA0,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA1,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA2,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA3,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_request_iomux(MX51_PIN_GPIO1_0,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
> - PAD_CTL_HYS_ENABLE);
> - mxc_request_iomux(MX51_PIN_GPIO1_1,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
> - PAD_CTL_HYS_ENABLE);
> + mx51_esdhc1_init_pins();
> break;
> case 1:
> - mxc_request_iomux(MX51_PIN_SD2_CMD,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD2_CLK,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD2_DATA0,
> - IOMUX_CONFIG_ALT0);
> - mxc_request_iomux(MX51_PIN_SD2_DATA1,
> - IOMUX_CONFIG_ALT0);
> - mxc_request_iomux(MX51_PIN_SD2_DATA2,
> - IOMUX_CONFIG_ALT0);
> - mxc_request_iomux(MX51_PIN_SD2_DATA3,
> - IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
> - PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
> - PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
> - PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
> - PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
> - PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
> - PAD_CTL_SRE_FAST);
> - mxc_request_iomux(MX51_PIN_SD2_CMD,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> + mx51_esdhc2_init_pins();
> mxc_request_iomux(MX51_PIN_GPIO1_6,
> IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
> @@ -509,7 +396,7 @@ void lcd_enable(void)
>
> int board_early_init_f(void)
> {
> - setup_iomux_uart();
> + mx51_uart1_init_pins();
> setup_iomux_fec();
> #ifdef CONFIG_USB_EHCI_MX5
> setup_usb_h1();
> diff --git u-boot-4d3c95f.orig/board/ttcontrol/vision2/vision2.c
> u-boot-4d3c95f/board/ttcontrol/vision2/vision2.c
> index d68bef7..a96c475 100644
> --- u-boot-4d3c95f.orig/board/ttcontrol/vision2/vision2.c
> +++ u-boot-4d3c95f/board/ttcontrol/vision2/vision2.c
> @@ -182,21 +182,7 @@ static void setup_uart(void)
> #ifdef CONFIG_MXC_SPI
> void spi_io_init(void)
> {
> - /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
> - mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
> -
> - /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1.
> */
> - mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
> -
> - /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
> - mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
> + mx51_ecspi1_init_pins();
>
> /*
> * SS1 will be used as GPIO because of uninterrupted
> @@ -212,11 +198,6 @@ void spi_io_init(void)
> mxc_iomux_set_pad(MX51_PIN_DI1_PIN11,
> PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
> PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
> -
> - /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1.
> */
> - mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
> }
>
> static void reset_peripherals(int reset)
> @@ -539,56 +520,7 @@ int get_mmc_getcd(u8 *cd, struct mmc *mmc)
> #ifdef CONFIG_FSL_ESDHC
> int board_mmc_init(bd_t *bis)
> {
> - mxc_request_iomux(MX51_PIN_SD1_CMD,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_CLK,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA0,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA1,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA2,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA3,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_request_iomux(MX51_PIN_GPIO1_0,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
> - PAD_CTL_HYS_ENABLE);
> - mxc_request_iomux(MX51_PIN_GPIO1_1,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
> - PAD_CTL_HYS_ENABLE);
> + mx51_esdhc1_init_pins();
>
> return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
> }
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 2/2] mx5: Use default pin initializers
2012-08-14 15:47 ` [U-Boot] [PATCH 2/2] mx5: Use " Benoît Thébaudeau
2012-08-15 14:37 ` Benoît Thébaudeau
@ 2012-08-16 19:46 ` Matt Sealey
2012-08-16 20:09 ` Benoît Thébaudeau
2012-08-16 20:19 ` Marek Vasut
1 sibling, 2 replies; 15+ messages in thread
From: Matt Sealey @ 2012-08-16 19:46 UTC (permalink / raw)
To: u-boot
I'm gonna NACK this because most of these pin settings are actually
the POR defaults anyway (UART1 is
the example I can easily pick out).
.. unless someone's setting them up wrong between warn reboots, or
changing a UART into something else
later in boot.. which is unfathomable.. we don't need to even touch
the iomux controller to get a working UART
on MX51, Efika MX or anything.
Why bother touching them?
--
Matt Sealey <matt@genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.
On Tue, Aug 14, 2012 at 10:47 AM, Beno?t Th?baudeau
<benoit.thebaudeau@advansee.com> wrote:
> Use the newly created mx5 default pin initialization functions in mx5 board
> files.
>
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> .../board/efikamx/efikamx.c | 133 ++------------------
> .../board/freescale/mx51evk/mx51evk.c | 121 +-----------------
> .../board/ttcontrol/vision2/vision2.c | 72 +----------
> 3 files changed, 15 insertions(+), 311 deletions(-)
>
> diff --git u-boot-4d3c95f.orig/board/efikamx/efikamx.c u-boot-4d3c95f/board/efikamx/efikamx.c
> index e88b2ed..6810433 100644
> --- u-boot-4d3c95f.orig/board/efikamx/efikamx.c
> +++ u-boot-4d3c95f/board/efikamx/efikamx.c
> @@ -143,38 +143,12 @@ int dram_init(void)
> }
>
> /*
> - * UART configuration
> - */
> -static void setup_iomux_uart(void)
> -{
> - unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
> -
> - mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
> - mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
> - mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
> - mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
> -}
> -
> -/*
> * SPI configuration
> */
> #ifdef CONFIG_MXC_SPI
> static void setup_iomux_spi(void)
> {
> - /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
> - mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
> -
> - /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
> - mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
> + mx51_ecspi1_init_pins();
>
> /* Configure SS0 as a GPIO */
> mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
> @@ -183,16 +157,6 @@ static void setup_iomux_spi(void)
> /* Configure SS1 as a GPIO */
> mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO);
> gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1);
> -
> - /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
> - mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
> -
> - /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
> - mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
> }
> #else
> static inline void setup_iomux_spi(void) { }
> @@ -333,7 +297,12 @@ int board_mmc_init(bd_t *bis)
> int ret;
> uint32_t cd = efika_mmc_cd();
>
> - /* SDHC1 is used on all revisions, setup control pins first */
> + /* SDHC1 is used on all revisions */
> +
> + /* SDHC1 IOMUX */
> + mx51_esdhc1_init_pins();
> +
> + /* SDHC1 Control lines IOMUX */
> mxc_request_iomux(cd,
> IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> mxc_iomux_set_pad(cd,
> @@ -354,65 +323,8 @@ int board_mmc_init(bd_t *bis)
> /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */
> if (machine_is_efikasb() || (machine_is_efikamx() &&
> (get_efika_rev() < EFIKAMX_BOARD_REV_12))) {
> - /* SDHC1 IOMUX */
> - mxc_request_iomux(MX51_PIN_SD1_CMD,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
> - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_CLK,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
> - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
> - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
> - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
> - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
> - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
> -
> /* SDHC2 IOMUX */
> - mxc_request_iomux(MX51_PIN_SD2_CMD,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD2_CLK,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> + mx51_esdhc2_init_pins();
>
> /* SDHC2 Control lines IOMUX */
> mxc_request_iomux(MX51_PIN_GPIO1_7,
> @@ -436,33 +348,6 @@ int board_mmc_init(bd_t *bis)
> if (!ret)
> ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
> } else { /* New boards use only SDHC1 */
> - /* SDHC1 IOMUX */
> - mxc_request_iomux(MX51_PIN_SD1_CMD,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_CLK,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> - mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
> -
> ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
> }
>
> @@ -676,7 +561,7 @@ int board_early_init_f(void)
> {
> init_drive_strength();
>
> - setup_iomux_uart();
> + mx51_uart1_init_pins();
> setup_iomux_spi();
> setup_iomux_led();
>
> diff --git u-boot-4d3c95f.orig/board/freescale/mx51evk/mx51evk.c u-boot-4d3c95f/board/freescale/mx51evk/mx51evk.c
> index 514a7ac..dedfb7e 100644
> --- u-boot-4d3c95f.orig/board/freescale/mx51evk/mx51evk.c
> +++ u-boot-4d3c95f/board/freescale/mx51evk/mx51evk.c
> @@ -60,21 +60,6 @@ int dram_init(void)
> return 0;
> }
>
> -static void setup_iomux_uart(void)
> -{
> - unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
> -
> - mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
> - mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
> - mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
> - mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
> -}
> -
> static void setup_iomux_fec(void)
> {
> /*FEC_MDIO*/
> @@ -153,29 +138,11 @@ static void setup_iomux_fec(void)
> #ifdef CONFIG_MXC_SPI
> static void setup_iomux_spi(void)
> {
> - /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
> - mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
> -
> - /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
> - mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
> + mx51_ecspi1_init_pins();
>
> /* de-select SS1 of instance: ecspi1. */
> mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
> mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
> -
> - /* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
> - mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
> -
> - /* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
> - mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
> -
> - /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
> - mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
> }
> #endif
>
> @@ -354,90 +321,10 @@ int board_mmc_init(bd_t *bis)
> index++) {
> switch (index) {
> case 0:
> - mxc_request_iomux(MX51_PIN_SD1_CMD,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_CLK,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA0,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA1,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA2,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA3,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_request_iomux(MX51_PIN_GPIO1_0,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
> - PAD_CTL_HYS_ENABLE);
> - mxc_request_iomux(MX51_PIN_GPIO1_1,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
> - PAD_CTL_HYS_ENABLE);
> + mx51_esdhc1_init_pins();
> break;
> case 1:
> - mxc_request_iomux(MX51_PIN_SD2_CMD,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD2_CLK,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD2_DATA0,
> - IOMUX_CONFIG_ALT0);
> - mxc_request_iomux(MX51_PIN_SD2_DATA1,
> - IOMUX_CONFIG_ALT0);
> - mxc_request_iomux(MX51_PIN_SD2_DATA2,
> - IOMUX_CONFIG_ALT0);
> - mxc_request_iomux(MX51_PIN_SD2_DATA3,
> - IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
> - PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
> - PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
> - PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
> - PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
> - PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
> - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
> - PAD_CTL_SRE_FAST);
> - mxc_request_iomux(MX51_PIN_SD2_CMD,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> + mx51_esdhc2_init_pins();
> mxc_request_iomux(MX51_PIN_GPIO1_6,
> IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
> @@ -509,7 +396,7 @@ void lcd_enable(void)
>
> int board_early_init_f(void)
> {
> - setup_iomux_uart();
> + mx51_uart1_init_pins();
> setup_iomux_fec();
> #ifdef CONFIG_USB_EHCI_MX5
> setup_usb_h1();
> diff --git u-boot-4d3c95f.orig/board/ttcontrol/vision2/vision2.c u-boot-4d3c95f/board/ttcontrol/vision2/vision2.c
> index d68bef7..a96c475 100644
> --- u-boot-4d3c95f.orig/board/ttcontrol/vision2/vision2.c
> +++ u-boot-4d3c95f/board/ttcontrol/vision2/vision2.c
> @@ -182,21 +182,7 @@ static void setup_uart(void)
> #ifdef CONFIG_MXC_SPI
> void spi_io_init(void)
> {
> - /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
> - mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
> -
> - /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
> - mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
> -
> - /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
> - mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
> - PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
> + mx51_ecspi1_init_pins();
>
> /*
> * SS1 will be used as GPIO because of uninterrupted
> @@ -212,11 +198,6 @@ void spi_io_init(void)
> mxc_iomux_set_pad(MX51_PIN_DI1_PIN11,
> PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
> PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
> -
> - /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
> - mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
> - mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
> - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
> }
>
> static void reset_peripherals(int reset)
> @@ -539,56 +520,7 @@ int get_mmc_getcd(u8 *cd, struct mmc *mmc)
> #ifdef CONFIG_FSL_ESDHC
> int board_mmc_init(bd_t *bis)
> {
> - mxc_request_iomux(MX51_PIN_SD1_CMD,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_CLK,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA0,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA1,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA2,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_request_iomux(MX51_PIN_SD1_DATA3,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
> - PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
> - PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
> - PAD_CTL_PUE_PULL |
> - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> - mxc_request_iomux(MX51_PIN_GPIO1_0,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
> - PAD_CTL_HYS_ENABLE);
> - mxc_request_iomux(MX51_PIN_GPIO1_1,
> - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
> - mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
> - PAD_CTL_HYS_ENABLE);
> + mx51_esdhc1_init_pins();
>
> return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
> }
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 2/2] mx5: Use default pin initializers
2012-08-16 19:46 ` Matt Sealey
@ 2012-08-16 20:09 ` Benoît Thébaudeau
2012-08-16 21:25 ` Matt Sealey
2012-08-16 20:19 ` Marek Vasut
1 sibling, 1 reply; 15+ messages in thread
From: Benoît Thébaudeau @ 2012-08-16 20:09 UTC (permalink / raw)
To: u-boot
Dear Matt Sealey,
> I'm gonna NACK this because most of these pin settings are actually
> the POR defaults anyway (UART1 is
> the example I can easily pick out).
>
> .. unless someone's setting them up wrong between warn reboots, or
> changing a UART into something else
> later in boot.. which is unfathomable.. we don't need to even touch
> the iomux controller to get a working UART
> on MX51, Efika MX or anything.
>
> Why bother touching them?
I agree, but the purpose of this patch is not to add this code, only to move it
to a common place... Why didn't you NAK the addition of these boards because of
that?
This kind of code is present in all i.MX board files. If it is useful, it's
better to have it merged rather than duplicated. If it is useless, then it can
be removed from all boards.
If you NAK this, following your rationale, it means that you prefer to have
useless duplicated code everywhere rather than in a single location. This just
doesn't make any sense. Or are you suggesting to remove this code from all
boards instead? Was there a good reason for this code to be there in the first
place?
Best regards,
Beno?t
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 2/2] mx5: Use default pin initializers
2012-08-16 19:46 ` Matt Sealey
2012-08-16 20:09 ` Benoît Thébaudeau
@ 2012-08-16 20:19 ` Marek Vasut
1 sibling, 0 replies; 15+ messages in thread
From: Marek Vasut @ 2012-08-16 20:19 UTC (permalink / raw)
To: u-boot
Dear Matt Sealey,
> I'm gonna NACK
You can't, only the custodians can ... you can only disagree and provide your
opinion, which you did ;-)
> this because most of these pin settings are actually
> the POR defaults anyway (UART1 is
> the example I can easily pick out).
>
> .. unless someone's setting them up wrong between warn reboots
Which in turn might cause trouble during reboots, so it's better to configure
them back properly.
> or
> changing a UART into something else
> later in boot.. which is unfathomable.. we don't need to even touch
> the iomux controller to get a working UART
> on MX51, Efika MX or anything.
You don't ... lucky you.
> Why bother touching them?
To avoid cases where broken kernel can't reboot or even cause hardware damage.
[...]
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 2/2] mx5: Use default pin initializers
2012-08-16 20:09 ` Benoît Thébaudeau
@ 2012-08-16 21:25 ` Matt Sealey
2012-08-16 22:51 ` Benoît Thébaudeau
2012-08-17 21:08 ` Stefano Babic
0 siblings, 2 replies; 15+ messages in thread
From: Matt Sealey @ 2012-08-16 21:25 UTC (permalink / raw)
To: u-boot
On Thu, Aug 16, 2012 at 3:09 PM, Beno?t Th?baudeau
<benoit.thebaudeau@advansee.com> wrote:
> Dear Matt Sealey,
>
>> I'm gonna NACK this because most of these pin settings are actually
>> the POR defaults anyway (UART1 is
>> the example I can easily pick out).
>>
>> .. unless someone's setting them up wrong between warn reboots, or
>> changing a UART into something else
>> later in boot.. which is unfathomable.. we don't need to even touch
>> the iomux controller to get a working UART
>> on MX51, Efika MX or anything.
>>
>> Why bother touching them?
>
> I agree, but the purpose of this patch is not to add this code, only to move it
> to a common place... Why didn't you NAK the addition of these boards because of
> that?
Why bother changing it in the first place if it's already doing the
same thing? :)
I have a MAJOR nit that is going to ruin your day; this is from
mx51_uart1_init_pins, just one line:
mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
Why are you using the old mxc_request_iomux model, when MX6 and
Sabrelite for example uses the newer iomux_v3_configure_pad model?
Surely someone should be thinking of putting that into place for MX51
and MX53 first so these pin init things can be done on the newer one.
I already ported 2012.07 for Efika MX and have an include (Troy
Kisky's got a copy of it too, we sent it there hoping for a little
review but he doesn't have our board to test IIRC) and a working tree.
What's stopping us submitting this already? Churn. Also, we thought we
could get away with U-Boot doing the grunt work of configuring pins
where needed, and the Linux DT guys vetoed it in favor of needlessly
reconfiguring the pins U-Boot already set up by redefining them for
reconfiguration in the DT anyway - I would have hoped we could avoid
that, and as such our U-Boot tree internally does a LOT of iomux setup
that U-Boot doesn't even drive (audio clock enables, amplifier, i2c..)
on our board. I need to cut that down a little bit.
> This kind of code is present in all i.MX board files. If it is useful, it's
> better to have it merged rather than duplicated.
See above :)
For i.MX we have two iomux models and function sets available for
doing identical stuff. Isn't that kind of wasteful?
> If you NAK this, following your rationale, it means that you prefer to have
> useless duplicated code everywhere rather than in a single location.
I'd prefer to have useless code removed, rather than just moved.
> doesn't make any sense. Or are you suggesting to remove this code from all
> boards instead? Was there a good reason for this code to be there in the first
> place?
No, there was never a good reason for it. It's there because whoever
wrote the very, very original code in the first place (Pegatron)
didn't read the docs properly and just set everything up regardless of
whether it was already set up, then whoever put the Efika MX support
in mainline didn't read the docs either and just reformatted what was
there in our source release and/or read the schematics without fact
checking.
It's a hideous legacy being perpetuated here. I am fully in favor of
you leaving Efika MX out to languish in the deep dark recesses of
boards that might compile but are basically doing weird stuff, and
nobody uses anyway, until we work out the situation to actually
support the board 100% in the most efficient way possible.
I'll throw a patchset out to add the iomux-mx51.h file (with all the
pins Efika MX needs at least. I had a little chat with Troy at BD and
he suggested people should add pins per board where needed and not
just copy the entire set from the Linux code if possible) sometime end
of week or next week, and maybe we can revisit these patches. I've
been concentrating on the Linux side and didn't think this new driver
model/code cleanup nightmare would happen at the same time as the
Linux board removal/wholesale DT switch.
Marek; I realise it's just an opinion, which I feel as the maintainer
of this platform (not for U-Boot in terms of custodian status, but in
terms of who at Genesi has the responsibility to keep track of this
stuff) I should express and I feel it would be remiss of me if I did
not. Who's the custodian of the Efika MX stuff anyway? Does it just
default to Stefano, or is it you as the committer?
As for problems during reboots, well, unsupported configurations are
unsupported configurations. If your kernel muxes out DIFFERENT pins to
U-Boot, expect U-Boot to burn the board. As it stands, the old
"linux-legacy" kernels don't make too heavy a set of changes (maybe
just drive strength and hysteresis stuff that is totally pointless).
If you boot U-Boot from POR and then boot a DT linux kernel, it'll all
be exactly the same on every reboot. Boot an old kernel and it'll
still work. You can't be too careful here, and by that I mean, you
can't keep reconfiguring the chip just because you think there may be
the possibility of some idiot doing something wrong. This isn't
something that is burned into the chip and configured as such on boot
without intervention, after all, it's all going to revert to power on
defaults the moment you yank the power. At that point, if you're
running a new U-Boot, and any Linux kernel published in the last few
years for Efika MX, nothing is going to explode.
--
Matt Sealey <matt@genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 2/2] mx5: Use default pin initializers
2012-08-16 21:25 ` Matt Sealey
@ 2012-08-16 22:51 ` Benoît Thébaudeau
2012-08-17 18:53 ` Matt Sealey
2012-08-17 21:08 ` Stefano Babic
1 sibling, 1 reply; 15+ messages in thread
From: Benoît Thébaudeau @ 2012-08-16 22:51 UTC (permalink / raw)
To: u-boot
Dear Matt Sealey,
> On Thu, Aug 16, 2012 at 3:09 PM, Beno?t Th?baudeau
> <benoit.thebaudeau@advansee.com> wrote:
> > Dear Matt Sealey,
> >
> >> I'm gonna NACK this because most of these pin settings are
> >> actually
> >> the POR defaults anyway (UART1 is
> >> the example I can easily pick out).
> >>
> >> .. unless someone's setting them up wrong between warn reboots, or
> >> changing a UART into something else
> >> later in boot.. which is unfathomable.. we don't need to even
> >> touch
> >> the iomux controller to get a working UART
> >> on MX51, Efika MX or anything.
> >>
> >> Why bother touching them?
> >
> > I agree, but the purpose of this patch is not to add this code,
> > only to move it
> > to a common place... Why didn't you NAK the addition of these
> > boards because of
> > that?
>
> Why bother changing it in the first place if it's already doing the
> same thing? :)
To improve code quality... And because I have local boards that also needed the
same functions, so it avoided more duplications.
> I have a MAJOR nit that is going to ruin your day; this is from
> mx51_uart1_init_pins, just one line:
>
> mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
>
> Why are you using the old mxc_request_iomux model, when MX6 and
> Sabrelite for example uses the newer iomux_v3_configure_pad model?
Simply because the current mx51 pin definitions are made for this API.
> Surely someone should be thinking of putting that into place for MX51
> and MX53 first so these pin init things can be done on the newer one.
> I already ported 2012.07 for Efika MX and have an include (Troy
> Kisky's got a copy of it too, we sent it there hoping for a little
> review but he doesn't have our board to test IIRC) and a working
> tree.
>
> What's stopping us submitting this already? Churn. Also, we thought
> we
> could get away with U-Boot doing the grunt work of configuring pins
> where needed, and the Linux DT guys vetoed it in favor of needlessly
> reconfiguring the pins U-Boot already set up by redefining them for
> reconfiguration in the DT anyway - I would have hoped we could avoid
> that, and as such our U-Boot tree internally does a LOT of iomux
> setup
> that U-Boot doesn't even drive (audio clock enables, amplifier,
> i2c..)
> on our board. I need to cut that down a little bit.
>
> > This kind of code is present in all i.MX board files. If it is
> > useful, it's
> > better to have it merged rather than duplicated.
>
> See above :)
>
> For i.MX we have two iomux models and function sets available for
> doing identical stuff. Isn't that kind of wasteful?
There's probably room for improvement on iomux, but we have to start cleanup
with something. If you want, you can submit patches and rebase after mine. That
would avoid you to duplicate your patch code for all boards. These are two
different topics, and my change comes logically first.
> > If you NAK this, following your rationale, it means that you prefer
> > to have
> > useless duplicated code everywhere rather than in a single
> > location.
>
> I'd prefer to have useless code removed, rather than just moved.
It's not useless. See below. :)
> > doesn't make any sense. Or are you suggesting to remove this code
> > from all
> > boards instead? Was there a good reason for this code to be there
> > in the first
> > place?
>
> No, there was never a good reason for it. It's there because whoever
> wrote the very, very original code in the first place (Pegatron)
> didn't read the docs properly and just set everything up regardless
> of
> whether it was already set up, then whoever put the Efika MX support
> in mainline didn't read the docs either and just reformatted what was
> there in our source release and/or read the schematics without fact
> checking.
>
> It's a hideous legacy being perpetuated here. I am fully in favor of
> you leaving Efika MX out to languish in the deep dark recesses of
> boards that might compile but are basically doing weird stuff, and
> nobody uses anyway, until we work out the situation to actually
> support the board 100% in the most efficient way possible.
>
> I'll throw a patchset out to add the iomux-mx51.h file (with all the
> pins Efika MX needs at least. I had a little chat with Troy at BD and
> he suggested people should add pins per board where needed and not
> just copy the entire set from the Linux code if possible) sometime
> end
> of week or next week, and maybe we can revisit these patches. I've
> been concentrating on the Linux side and didn't think this new driver
> model/code cleanup nightmare would happen at the same time as the
> Linux board removal/wholesale DT switch.
>
> Marek; I realise it's just an opinion, which I feel as the maintainer
> of this platform (not for U-Boot in terms of custodian status, but in
> terms of who at Genesi has the responsibility to keep track of this
> stuff) I should express and I feel it would be remiss of me if I did
> not. Who's the custodian of the Efika MX stuff anyway? Does it just
> default to Stefano, or is it you as the committer?
http://git.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=blob;f=MAINTAINERS;h=c5a6f2f297353b5883f751af9780de440bc3b4d7;hb=HEAD
is here to tell you just that.
> As for problems during reboots, well, unsupported configurations are
> unsupported configurations. If your kernel muxes out DIFFERENT pins
> to
> U-Boot, expect U-Boot to burn the board. As it stands, the old
> "linux-legacy" kernels don't make too heavy a set of changes (maybe
> just drive strength and hysteresis stuff that is totally pointless).
> If you boot U-Boot from POR and then boot a DT linux kernel, it'll
> all
> be exactly the same on every reboot. Boot an old kernel and it'll
> still work. You can't be too careful here, and by that I mean, you
> can't keep reconfiguring the chip just because you think there may be
> the possibility of some idiot doing something wrong. This isn't
> something that is burned into the chip and configured as such on boot
> without intervention, after all, it's all going to revert to power on
> defaults the moment you yank the power. At that point, if you're
> running a new U-Boot, and any Linux kernel published in the last few
> years for Efika MX, nothing is going to explode.
As a general rule, you should not rely on the expected post-reset state. You
really can't know for sure what may have happened before your code starts. Weird
things could have occurred, e.g. you may have launched your code from a JTAG
probe that put your binary right into RAM instead of using normal reset + ROM
bootloader.
Best regards,
Beno?t
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 2/2] mx5: Use default pin initializers
2012-08-16 22:51 ` Benoît Thébaudeau
@ 2012-08-17 18:53 ` Matt Sealey
2012-08-17 19:26 ` Benoît Thébaudeau
0 siblings, 1 reply; 15+ messages in thread
From: Matt Sealey @ 2012-08-17 18:53 UTC (permalink / raw)
To: u-boot
On Thu, Aug 16, 2012 at 5:51 PM, Beno?t Th?baudeau
<benoit.thebaudeau@advansee.com> wrote:
> Dear Matt Sealey,
>
>> On Thu, Aug 16, 2012 at 3:09 PM, Beno?t Th?baudeau
>> <benoit.thebaudeau@advansee.com> wrote:
>
> To improve code quality... And because I have local boards that also needed the
> same functions, so it avoided more duplications.
>
>> For i.MX we have two iomux models and function sets available for
>> doing identical stuff. Isn't that kind of wasteful?
>
> There's probably room for improvement on iomux, but we have to start cleanup
> with something. If you want, you can submit patches and rebase after mine.
Done, to a degree :)
> would avoid you to duplicate your patch code for all boards. These are two
> different topics, and my change comes logically first.
See patches. On Marex's recommendation I based against u-boot-imx
master rather than trying to fit it on top of your stuff. In the end,
I would prefer that boards specifically implement pad settings in
their own board files rather than assuming that some common function
in the driver will suit them; we have an MX6 board here that uses the
SD4 pads for UART2 for debug console. This is absolutely not common at
all to any other MX6 board, so it would have to do UART pad setup and
not use the generic function.
With pads defined as reasonable defaults, and NEW_PAD_CTRL available
to modify pads per-board this is a more flexible setup and exactly why
it was coded this way in Linux and why Freescale seemed to see fit to
backport it to U-Boot (and why it was accepted to mainline for MX6).
There's still some cleanup, all the other boards, and obviously MX53
needs to be added to make it more useful.
If we wish to continue with functions like mx51_uart1_setup() or so,
then that function can reference these values, but I think you will
find it more likely that someone in the future modifies it to take
reference to an iomux_v3_cfg_t array so they can configure their board
properly to something that doesn't meet your assumed defaults, or
defines the pad setup internally to their board and skips calling your
setup function. Then there would be no difference between calling
mx51_uart1_setup vs. imx_iomux_v3_setup_multiple_pads anyway..
reducing the need for it.
I kept the redefinition of the pads for UART etc, even though POR
defaults work fine, just to keep within your assumption that we
shouldn't trust POR defaults.. although I don't think that loading
code via JTAG and executing it (i.e. skipping the i.MX boot ROM) is a
very common process at all as it just flies in the face of what
Freescale intend to be the boot process for the chip, and in any case,
the defaults are part of the SoC logic (and are correct in the
documentation as far as I have checked), not some pre-U-Boot software
configuration. Given the dangers inherent in doing this anyway, I
don't think it would be fitting to make sure things are configured how
you want (and in any case, why would someone configure UART pads
differently to your expectations, and then let U-Boot reconfigure them
on boot?)
--
Matt Sealey <matt@genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 1/2] mx5: Add default pin initializers
2012-08-14 15:46 [U-Boot] [PATCH 1/2] mx5: Add default pin initializers Benoît Thébaudeau
2012-08-14 15:47 ` [U-Boot] [PATCH 2/2] mx5: Use " Benoît Thébaudeau
@ 2012-08-17 19:10 ` Matt Sealey
2012-08-17 19:40 ` Benoît Thébaudeau
2012-08-17 20:25 ` Stefano Babic
2 siblings, 1 reply; 15+ messages in thread
From: Matt Sealey @ 2012-08-17 19:10 UTC (permalink / raw)
To: u-boot
On Tue, Aug 14, 2012 at 10:46 AM, Beno?t Th?baudeau
<benoit.thebaudeau@advansee.com> wrote:
> Create default pin initialization functions for the default iomux function
> assignments of the main peripherals.
>
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> .../arch/arm/cpu/armv7/mx5/soc.c | 139 ++++++++++++++++++++
> .../arch/arm/include/asm/arch-mx5/sys_proto.h | 5 +
> 2 files changed, 144 insertions(+)
>
> diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/soc.c u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/soc.c
> index 3f5a4f7..ee19b54 100644
> --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/soc.c
> +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/soc.c
> @@ -25,6 +25,8 @@
>
> #include <common.h>
> #include <asm/arch/imx-regs.h>
> +#include <asm/arch/mx5x_pins.h>
> +#include <asm/arch/iomux.h>
> #include <asm/arch/clock.h>
> #include <asm/arch/sys_proto.h>
>
> @@ -71,6 +73,143 @@ u32 get_cpu_rev(void)
> return system_rev;
> }
>
> +#ifdef CONFIG_MXC_UART
> +#if CONFIG_MXC_UART_BASE == UART1_BASE
> +#ifdef CONFIG_MX51
> +void mx51_uart1_init_pins(void)
> +{
> + int in_pad, out_pad;
> +
> + /* Set up pins for UART1. */
> + mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
> +
> + mxc_iomux_set_input(MX51_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
> + INPUT_CTL_PATH0);
> + mxc_iomux_set_input(MX51_UART1_IPP_UART_RTS_B_SELECT_INPUT,
> + INPUT_CTL_PATH0);
> +
> + in_pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
> + PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
> + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW;
> + out_pad = PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE |
> + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH |
> + PAD_CTL_SRE_SLOW;
If we're nitpicking - none of the UART1_* pads on MX51 have valid ODE
bits, it's a reserved area. Even though you're setting it to 0 here,
including it in the pad settings is bad behavior.
--
Matt Sealey <matt@genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 2/2] mx5: Use default pin initializers
2012-08-17 18:53 ` Matt Sealey
@ 2012-08-17 19:26 ` Benoît Thébaudeau
0 siblings, 0 replies; 15+ messages in thread
From: Benoît Thébaudeau @ 2012-08-17 19:26 UTC (permalink / raw)
To: u-boot
Dear Matt Sealey,
> On Thu, Aug 16, 2012 at 5:51 PM, Beno?t Th?baudeau
> <benoit.thebaudeau@advansee.com> wrote:
> > Dear Matt Sealey,
> >
> >> On Thu, Aug 16, 2012 at 3:09 PM, Beno?t Th?baudeau
> >> <benoit.thebaudeau@advansee.com> wrote:
> >
> > To improve code quality... And because I have local boards that
> > also needed the
> > same functions, so it avoided more duplications.
> >
> >> For i.MX we have two iomux models and function sets available for
> >> doing identical stuff. Isn't that kind of wasteful?
> >
> > There's probably room for improvement on iomux, but we have to
> > start cleanup
> > with something. If you want, you can submit patches and rebase
> > after mine.
>
> Done, to a degree :)
Seen it.
> > would avoid you to duplicate your patch code for all boards. These
> > are two
> > different topics, and my change comes logically first.
>
> See patches. On Marex's recommendation I based against u-boot-imx
> master rather than trying to fit it on top of your stuff. In the end,
> I would prefer that boards specifically implement pad settings in
> their own board files rather than assuming that some common function
> in the driver will suit them; we have an MX6 board here that uses the
> SD4 pads for UART2 for debug console. This is absolutely not common
> at
> all to any other MX6 board, so it would have to do UART pad setup and
> not use the generic function.
The purpose of the functions that I added is only to handle the standard pin
initializations, i.e. with the default IOMUX functions of the pins and proper
pad settings for these functions. For non-standard settings, the boards of
course need their own code.
> With pads defined as reasonable defaults, and NEW_PAD_CTRL available
> to modify pads per-board this is a more flexible setup and exactly
> why
> it was coded this way in Linux and why Freescale seemed to see fit to
> backport it to U-Boot (and why it was accepted to mainline for MX6).
> There's still some cleanup, all the other boards, and obviously MX53
> needs to be added to make it more useful.
Sure. It's much better for code clarity, size, etc. than having tons of function
calls.
> If we wish to continue with functions like mx51_uart1_setup() or so,
> then that function can reference these values, but I think you will
> find it more likely that someone in the future modifies it to take
> reference to an iomux_v3_cfg_t array so they can configure their
> board
> properly to something that doesn't meet your assumed defaults, or
> defines the pad setup internally to their board and skips calling
> your
> setup function. Then there would be no difference between calling
> mx51_uart1_setup vs. imx_iomux_v3_setup_multiple_pads anyway..
> reducing the need for it.
Yes. I don't know if it's really worth keeping my functions with the new pin
settings definitions. That would still avoid duplicating the standard init array
but on the other hand it would also mean more function calls than with a single
board pin array. Another solution could be to #define for each i.MX the part of
the array initializer corresponding to each standard peripheral pin setup, like:
iomux-mx51.h:
#define MX51_UART1_PAD_SETUP \
MX51_PAD_UART1_RXD__UART1_RXD, \
MX51_PAD_UART1_TXD__UART1_TXD, \
MX51_PAD_UART1_RTS__UART1_RTS, \
MX51_PAD_UART1_CTS__UART1_CTS,
some board.c:
static iomux_v3_cfg_t board_pads[] = {
MX51_UART1_PAD_SETUP,
MX51_PAD_...,
};
imx_iomux_v3_setup_multiple_pads(board_pads, ARRAY_SIZE(board_pads));
> I kept the redefinition of the pads for UART etc, even though POR
> defaults work fine, just to keep within your assumption that we
> shouldn't trust POR defaults.. although I don't think that loading
> code via JTAG and executing it (i.e. skipping the i.MX boot ROM) is a
> very common process at all as it just flies in the face of what
> Freescale intend to be the boot process for the chip, and in any
> case,
> the defaults are part of the SoC logic (and are correct in the
> documentation as far as I have checked), not some pre-U-Boot software
> configuration. Given the dangers inherent in doing this anyway, I
> don't think it would be fitting to make sure things are configured
> how
> you want (and in any case, why would someone configure UART pads
> differently to your expectations, and then let U-Boot reconfigure
> them
> on boot?)
It was only an example. You can also have interfering test code, ROM bootloader
code, datasheet errors, etc.
Best regards,
Beno?t
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 1/2] mx5: Add default pin initializers
2012-08-17 19:10 ` [U-Boot] [PATCH 1/2] mx5: Add " Matt Sealey
@ 2012-08-17 19:40 ` Benoît Thébaudeau
0 siblings, 0 replies; 15+ messages in thread
From: Benoît Thébaudeau @ 2012-08-17 19:40 UTC (permalink / raw)
To: u-boot
Dear Matt Sealey,
> On Tue, Aug 14, 2012 at 10:46 AM, Beno?t Th?baudeau
> <benoit.thebaudeau@advansee.com> wrote:
> > Create default pin initialization functions for the default iomux
> > function
> > assignments of the main peripherals.
> >
> > Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> > Cc: Stefano Babic <sbabic@denx.de>
> > ---
> > .../arch/arm/cpu/armv7/mx5/soc.c | 139
> > ++++++++++++++++++++
> > .../arch/arm/include/asm/arch-mx5/sys_proto.h | 5 +
> > 2 files changed, 144 insertions(+)
> >
> > diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/soc.c
> > u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/soc.c
> > index 3f5a4f7..ee19b54 100644
> > --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/soc.c
> > +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/soc.c
> > @@ -25,6 +25,8 @@
> >
> > #include <common.h>
> > #include <asm/arch/imx-regs.h>
> > +#include <asm/arch/mx5x_pins.h>
> > +#include <asm/arch/iomux.h>
> > #include <asm/arch/clock.h>
> > #include <asm/arch/sys_proto.h>
> >
> > @@ -71,6 +73,143 @@ u32 get_cpu_rev(void)
> > return system_rev;
> > }
> >
> > +#ifdef CONFIG_MXC_UART
> > +#if CONFIG_MXC_UART_BASE == UART1_BASE
> > +#ifdef CONFIG_MX51
> > +void mx51_uart1_init_pins(void)
> > +{
> > + int in_pad, out_pad;
> > +
> > + /* Set up pins for UART1. */
> > + mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
> > + mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
> > + mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
> > + mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
> > +
> > +
> > mxc_iomux_set_input(MX51_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
> > + INPUT_CTL_PATH0);
> > + mxc_iomux_set_input(MX51_UART1_IPP_UART_RTS_B_SELECT_INPUT,
> > + INPUT_CTL_PATH0);
> > +
> > + in_pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
> > PAD_CTL_PUE_PULL |
> > + PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
> > + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW;
> > + out_pad = PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE |
> > + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH |
> > + PAD_CTL_SRE_SLOW;
>
> If we're nitpicking - none of the UART1_* pads on MX51 have valid ODE
> bits, it's a reserved area.
I know that.
> Even though you're setting it to 0 here,
Indeed.
> including it in the pad settings is bad behavior.
No, it's here to emphasize the pad settings that are used. Moreover, in some
cases, the same pad value is used for several pads that do not all have the same
bits available or not, so that wouldn't make sense to have the same pad setting
written in many different ways only because of that.
This kind of thing will also very likely occur in your new iomux-mx51.h.
Best regards,
Beno?t
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 1/2] mx5: Add default pin initializers
2012-08-14 15:46 [U-Boot] [PATCH 1/2] mx5: Add default pin initializers Benoît Thébaudeau
2012-08-14 15:47 ` [U-Boot] [PATCH 2/2] mx5: Use " Benoît Thébaudeau
2012-08-17 19:10 ` [U-Boot] [PATCH 1/2] mx5: Add " Matt Sealey
@ 2012-08-17 20:25 ` Stefano Babic
2012-08-17 20:38 ` Matt Sealey
2 siblings, 1 reply; 15+ messages in thread
From: Stefano Babic @ 2012-08-17 20:25 UTC (permalink / raw)
To: u-boot
On 14/08/2012 17:46, Beno?t Th?baudeau wrote:
> Create default pin initialization functions for the default iomux function
> assignments of the main peripherals.
>
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
Hi Beno?t,
> .../arch/arm/cpu/armv7/mx5/soc.c | 139 ++++++++++++++++++++
> .../arch/arm/include/asm/arch-mx5/sys_proto.h | 5 +
> 2 files changed, 144 insertions(+)
>
> diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/soc.c u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/soc.c
> index 3f5a4f7..ee19b54 100644
> --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/soc.c
> +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/soc.c
> @@ -25,6 +25,8 @@
>
> #include <common.h>
> #include <asm/arch/imx-regs.h>
> +#include <asm/arch/mx5x_pins.h>
> +#include <asm/arch/iomux.h>
> #include <asm/arch/clock.h>
> #include <asm/arch/sys_proto.h>
>
> @@ -71,6 +73,143 @@ u32 get_cpu_rev(void)
> return system_rev;
> }
>
> +#ifdef CONFIG_MXC_UART
> +#if CONFIG_MXC_UART_BASE == UART1_BASE
> +#ifdef CONFIG_MX51
> +void mx51_uart1_init_pins(void)
> +{
> + int in_pad, out_pad;
> +
> + /* Set up pins for UART1. */
> + mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
> +
> + mxc_iomux_set_input(MX51_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
> + INPUT_CTL_PATH0);
> + mxc_iomux_set_input(MX51_UART1_IPP_UART_RTS_B_SELECT_INPUT,
> + INPUT_CTL_PATH0);
> +
> + in_pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
> + PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
> + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW;
> + out_pad = PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE |
> + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH |
> + PAD_CTL_SRE_SLOW;
> +
> + mxc_iomux_set_pad(MX51_PIN_UART1_RXD, in_pad);
> + mxc_iomux_set_pad(MX51_PIN_UART1_TXD, out_pad);
> + mxc_iomux_set_pad(MX51_PIN_UART1_RTS, in_pad);
> + mxc_iomux_set_pad(MX51_PIN_UART1_CTS, out_pad);
> +}
Yes, the intention is surely to rationalize code and to avoid
duplication. But it requires to add such kind of function for any
instance of a peripheral (mx51_uart2_init_pins, for example) and cannot
worked on all boards. For example, a board will not use RTS and CTS, and
these pins are GPIOs (very common example). Or it can use other pins for
RX and TXD: the SOC allows this, and maybe someone want to use it.
The other thing I see (not in this patch, but checking the current
implementation in mainline) is that we have different implementation for
MX51, MX53 / MX6. This is bad.
I think that setting each pin with mxc_request_iomux() is not a great
idea. Maybe another solution would be to provide a table with the pinmux
for the whole SOC and a funtion to set all of them, as
imx_iomux_v3_setup_multiple_pads. This is also similar to the current
implementation in u-boot for other SOCs, for example TI.
IMHO to improve the current situation in i.MX pinmux code we should try
to use the same code, or at least, the same API for the board
maintainer, and putting the pinmux configuration in a table. This is
also what the legacy kernel does, putting in the table only the pins
required by u-boot itself (current kernel sets itself the pinmux, via
device tree or initializing the board when dts is not available).
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 1/2] mx5: Add default pin initializers
2012-08-17 20:25 ` Stefano Babic
@ 2012-08-17 20:38 ` Matt Sealey
0 siblings, 0 replies; 15+ messages in thread
From: Matt Sealey @ 2012-08-17 20:38 UTC (permalink / raw)
To: u-boot
On Fri, Aug 17, 2012 at 3:25 PM, Stefano Babic <sbabic@denx.de> wrote:
> On 14/08/2012 17:46, Beno?t Th?baudeau wrote:
>> Create default pin initialization functions for the default iomux function
>> assignments of the main peripherals.
>>
>> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
>> Cc: Stefano Babic <sbabic@denx.de>
>> ---
>
> I think that setting each pin with mxc_request_iomux() is not a great
> idea. Maybe another solution would be to provide a table with the pinmux
> for the whole SOC and a funtion to set all of them, as
> imx_iomux_v3_setup_multiple_pads. This is also similar to the current
> implementation in u-boot for other SOCs, for example TI.
Done and submitted for MX51 - and Efika MX is ported and through QA.
Can you review?
Benoit has some valid suggestions for changes, which can come later,
but for now moving to that for MX51 boards should be a net zero
difference for all implemented boards. I don't have space on my desk
to fire up my MX53 Quickstart or EVK to test those, but porting the
files for MX53 from Linux should not be a big deal and further
combining the 3 implementations differences (moving GPIO_NUMBER to
imx-common/iomux-v3.h instead of it being SoC-specific for example) is
something that would better be done once everything's in and working.
--
Matt Sealey <matt@genesi-usa.com>
Product Development Analyst, Genesi USA, Inc.
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH 2/2] mx5: Use default pin initializers
2012-08-16 21:25 ` Matt Sealey
2012-08-16 22:51 ` Benoît Thébaudeau
@ 2012-08-17 21:08 ` Stefano Babic
1 sibling, 0 replies; 15+ messages in thread
From: Stefano Babic @ 2012-08-17 21:08 UTC (permalink / raw)
To: u-boot
On 16/08/2012 23:25, Matt Sealey wrote:
> On Thu, Aug 16, 2012 at 3:09 PM, Beno?t Th?baudeau
> <benoit.thebaudeau@advansee.com> wrote:
>> Dear Matt Sealey,
>>
Hi Matt,
>>> I'm gonna NACK this because most of these pin settings are actually
>>> the POR defaults anyway (UART1 is
>>> the example I can easily pick out).
>>>
>>> .. unless someone's setting them up wrong between warn reboots, or
>>> changing a UART into something else
>>> later in boot.. which is unfathomable.. we don't need to even touch
>>> the iomux controller to get a working UART
>>> on MX51, Efika MX or anything.
>>>
>>> Why bother touching them?
>>
>> I agree, but the purpose of this patch is not to add this code, only to move it
>> to a common place... Why didn't you NAK the addition of these boards because of
>> that?
>
I am coming a little later in the discussion, sorry.
> Why bother changing it in the first place if it's already doing the
> same thing? :)
>
> I have a MAJOR nit that is going to ruin your day; this is from
> mx51_uart1_init_pins, just one line:
>
> mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
>
> Why are you using the old mxc_request_iomux model, when MX6 and
> Sabrelite for example uses the newer iomux_v3_configure_pad model?
This is a point I see as an improvement for the current pinmux in i.MX.
At least MX53 and MX6 share the same code, but MX51 was not upgraded to
work as the other ones.
My personal point for the pinmux is that it is *very* difficult to set
the same pin configuration for a function, such as spi1 or uart1 as done
in this patchset. The hardware developer can have used a different
pinout as "normal", because they need to do this.
So the pinmux must always be customized for each board.
>
> Surely someone should be thinking of putting that into place for MX51
> and MX53 first so these pin init things can be done on the newer one.
> I already ported 2012.07 for Efika MX and have an include (Troy
> Kisky's got a copy of it too, we sent it there hoping for a little
> review but he doesn't have our board to test IIRC) and a working tree.
>
> What's stopping us submitting this already? Churn. Also, we thought we
> could get away with U-Boot doing the grunt work of configuring pins
> where needed, and the Linux DT guys vetoed it in favor of needlessly
> reconfiguring the pins U-Boot already set up by redefining them for
> reconfiguration in the DT anyway -
The kernel rule is to set itself the pinmux and not rely on the setup of
the bootloader. This makes completely sense. U-Boot should set only the
pins it really needs.
> For i.MX we have two iomux models and function sets available for
> doing identical stuff. Isn't that kind of wasteful?
It is bad - my point is that we can concentrate efforts to have only one
implementation reducing current confusion ;-)
>
> No, there was never a good reason for it. It's there because whoever
> wrote the very, very original code in the first place (Pegatron)
> didn't read the docs properly and just set everything up regardless of
> whether it was already set up, then whoever put the Efika MX support
> in mainline didn't read the docs either and just reformatted what was
> there in our source release and/or read the schematics without fact
> checking.
>
> It's a hideous legacy being perpetuated here. I am fully in favor of
> you leaving Efika MX out to languish in the deep dark recesses of
> boards that might compile but are basically doing weird stuff, and
> nobody uses anyway, until we work out the situation to actually
> support the board 100% in the most efficient way possible.
>
> I'll throw a patchset out to add the iomux-mx51.h file (with all the
> pins Efika MX needs at least.
I see now your patchset - I put it in my queue for review, rather it is
a long queue..
>
> As for problems during reboots, well, unsupported configurations are
> unsupported configurations. If your kernel muxes out DIFFERENT pins to
> U-Boot, expect U-Boot to burn the board.
All SOCs have a default value for the IOMUX after a reset. Freescale
guarantees (apart the errata..) that the pins have always the same value
after a reset.
It is then duty of the hardware developer to make certain that the board
does not burn after a reset - even if u-boot could fix something, it is
not assured how much time it can take after a reset.
> As it stands, the old
> "linux-legacy" kernels don't make too heavy a set of changes (maybe
> just drive strength and hysteresis stuff that is totally pointless).
> If you boot U-Boot from POR and then boot a DT linux kernel, it'll all
> be exactly the same on every reboot. Boot an old kernel and it'll
> still work.
And if it does not work, the fix should be in kernel, not in u-boot.
> You can't be too careful here, and by that I mean, you
> can't keep reconfiguring the chip just because you think there may be
> the possibility of some idiot doing something wrong.
We all know that this is impossible because idiots are very creative ;-)
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2012-08-17 21:08 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-08-14 15:46 [U-Boot] [PATCH 1/2] mx5: Add default pin initializers Benoît Thébaudeau
2012-08-14 15:47 ` [U-Boot] [PATCH 2/2] mx5: Use " Benoît Thébaudeau
2012-08-15 14:37 ` Benoît Thébaudeau
2012-08-16 19:46 ` Matt Sealey
2012-08-16 20:09 ` Benoît Thébaudeau
2012-08-16 21:25 ` Matt Sealey
2012-08-16 22:51 ` Benoît Thébaudeau
2012-08-17 18:53 ` Matt Sealey
2012-08-17 19:26 ` Benoît Thébaudeau
2012-08-17 21:08 ` Stefano Babic
2012-08-16 20:19 ` Marek Vasut
2012-08-17 19:10 ` [U-Boot] [PATCH 1/2] mx5: Add " Matt Sealey
2012-08-17 19:40 ` Benoît Thébaudeau
2012-08-17 20:25 ` Stefano Babic
2012-08-17 20:38 ` Matt Sealey
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