From mboxrd@z Thu Jan  1 00:00:00 1970
From: Stephen Warren <swarren@wwwdotorg.org>
Date: Mon, 20 Aug 2012 12:19:54 -0600
Subject: [U-Boot] [PATCH 2/3] tegra20: add clock_set_pllout function
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References: <1345392496-28739-1-git-send-email-dev@lynxeye.de>
	<1345392496-28739-3-git-send-email-dev@lynxeye.de>
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On 08/19/2012 10:08 AM, Lucas Stach wrote:
> Common practice on Tegra 2 boards is to use the pllp_out4 FO
> to generate the ULPI reference clock. For this to work we have
> to override the default hardware generated output divider.
> 
> This function adds a clean way to do so.

> diff --git a/arch/arm/cpu/tegra20-common/clock.c b/arch/arm/cpu/tegra20-common/clock.c

> +int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
> +{
> +	struct clk_pll *pll = get_pll(clkid);
> +	int data = 0, div = 0, offset = 0;
> +
> +	if (!clock_id_is_pll(clkid))
> +		return -1;

If you're going to error-check; you may as well limit the range of
pllout too; not all PLLs have 4 outputs.

Other than that, I think this seems OK.